* [RFC PATCH] drm/xe/ggtt: Cut GGTT initialization from 900 ms to 37 ms
@ 2026-10-28 4:50 Daniel Colascione
2026-10-28 13:09 ` ✗ LGCI.VerificationFailed: failure for " Patchwork
` (5 more replies)
0 siblings, 6 replies; 8+ messages in thread
From: Daniel Colascione @ 2026-10-28 4:50 UTC (permalink / raw)
To: intel-xe; +Cc: Matthew Brost, Thomas Hellstrom, Rodrigo Vivi, dri-devel
We initialize the GGTT GPU page tables on startup. On my LNL, doing
this one PTE at a time through the BAR takes about 900 ms and involves
a million small writes.
Use the GPU's copy engine to fill the PTEs in batches. We build
MI_UPDATE_GTT commands in normal memory, then send them to the GPU for
execution. This way, we avoid the per-PTE MMIO write and do the PTE fill
in 36.77 ms, ~24x faster.
The new path is enabled by default. xe.ggtt_init_gpu=0 uses the old
CPU-driven path.
LNL-only because I can test only LNL. Might it work elsewhere?
Signed-off-by: Daniel Colascione <dancol@dancol.org>
---
drivers/gpu/drm/xe/instructions/xe_mi_commands.h | 2 +
drivers/gpu/drm/xe/xe_ggtt.c | 128 +++++++++++++++++++++--
drivers/gpu/drm/xe/xe_ggtt.h | 1 +
drivers/gpu/drm/xe/xe_gt.c | 3 +-
drivers/gpu/drm/xe/xe_module.c | 5 +
drivers/gpu/drm/xe/xe_module.h | 1 +
6 files changed, 130 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
index 835ef75bbeb1..04bd4225adef 100644
--- a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
+++ b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
@@ -62,6 +62,8 @@
#define MI_LRI_FORCE_POSTED REG_BIT(12)
#define MI_LRI_LEN(x) (((x) & 0xff) + 1)
+#define MI_UPDATE_GTT __MI_INSTR(0x23)
+
#define MI_STORE_REGISTER_MEM (__MI_INSTR(0x24) | XE_INSTR_NUM_DW(4))
#define MI_SRM_USE_GGTT REG_BIT(22)
#define MI_SRM_ADD_CS_OFFSET REG_BIT(19)
diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
index 773777afc68a..3737d085ae68 100644
--- a/drivers/gpu/drm/xe/xe_ggtt.c
+++ b/drivers/gpu/drm/xe/xe_ggtt.c
@@ -15,20 +15,25 @@
#include <drm/intel/i915_drm.h>
#include <generated/xe_wa_oob.h>
+#include "instructions/xe_mi_commands.h"
#include "regs/xe_gt_regs.h"
#include "regs/xe_gtt_defs.h"
#include "regs/xe_regs.h"
#include "xe_assert.h"
+#include "xe_bb.h"
#include "xe_bo.h"
+#include "xe_exec_queue.h"
#include "xe_gt.h"
#include "xe_gt_printk.h"
#include "xe_gt_types.h"
#include "xe_log.h"
#include "xe_map.h"
#include "xe_mmio.h"
+#include "xe_module.h"
#include "xe_pat.h"
#include "xe_pm.h"
#include "xe_res_cursor.h"
+#include "xe_sched_job.h"
#include "xe_sriov.h"
#include "xe_tile_printk.h"
#include "xe_tile_sriov_vf.h"
@@ -384,9 +389,9 @@ static void dev_fini_ggtt(void *arg)
* @ggtt: the &xe_ggtt to be initialized
*
* It allows to create new mappings usable by the GuC.
- * Mappings are not usable by the HW engines, as it doesn't have scratch nor
- * initial clear done to it yet. That will happen in the regular, non-early
- * GGTT initialization.
+ * HW engines may only access explicitly mapped bootstrap buffers until the
+ * remaining holes have been cleared. Normally xe_ggtt_init() does this;
+ * the GPU clear finishes this work in xe_ggtt_init_late().
*
* Return: 0 on success or a negative error code on failure.
*/
@@ -456,18 +461,119 @@ ALLOW_ERROR_INJECTION(xe_ggtt_init_early, ERRNO); /* See xe_pci_probe() */
static void xe_ggtt_invalidate(struct xe_ggtt *ggtt);
static void xe_ggtt_invalidate_engine(struct xe_ggtt *ggtt);
-static void xe_ggtt_initial_clear(struct xe_ggtt *ggtt)
+static bool ggtt_use_gpu(struct xe_device *xe)
{
+ return xe_modparam.ggtt_init_gpu && xe->info.platform == XE_LUNARLAKE;
+}
+
+/*
+ * MI_UPDATE_GTT takes at most 511 inline PTEs (ACM PRM, Vol. 2a,
+ * pp. 1096-1097). Limit batches to 512K to fit the kernel batch pool.
+ */
+#define GGTT_INIT_PTES_PER_PACKET 511
+#define GGTT_INIT_BATCH_DWORDS (128 * (2 + 2 * GGTT_INIT_PTES_PER_PACKET))
+
+static int ggtt_clear_gpu(struct xe_exec_queue *q, struct xe_bb *bb,
+ u64 pte, u64 start, u64 end)
+{
+ while (start < end) {
+ struct xe_sched_job *job;
+ int err;
+
+ bb->len = 0;
+ while (start < end && bb->len < GGTT_INIT_BATCH_DWORDS) {
+ u32 count = min_t(u64, (end - start) >> XE_PTE_SHIFT,
+ GGTT_INIT_PTES_PER_PACKET);
+
+ bb->cs[bb->len++] = MI_UPDATE_GTT | (2 * count);
+ bb->cs[bb->len++] = start;
+ memset64((u64 *)&bb->cs[bb->len], pte, count);
+ bb->len += 2 * count;
+ start += (u64)count << XE_PTE_SHIFT;
+ }
+
+ job = xe_bb_create_job(q, bb);
+ if (IS_ERR(job))
+ return PTR_ERR(job);
+
+ xe_sched_job_arm(job);
+ xe_sched_job_get(job);
+ xe_sched_job_push(job);
+
+ dma_fence_wait(&job->drm.s_fence->finished, false);
+ err = dma_fence_get_status(&job->drm.s_fence->finished);
+ xe_sched_job_put(job);
+ if (err < 0)
+ return err;
+ }
+
+ return 0;
+}
+
+static int xe_ggtt_initial_clear(struct xe_ggtt *ggtt, struct xe_hw_engine *hwe)
+{
+ struct xe_device *xe = tile_to_xe(ggtt->tile);
+ struct xe_exec_queue *q = NULL;
+ struct xe_bb *bb = NULL;
struct drm_mm_node *hole;
- u64 start, end;
+ u16 pat_index = xe_cache_pat_idx(xe, XE_CACHE_WB);
+ u64 start, end, pte = 0;
+ int err = 0;
+
+ if (hwe) {
+ q = xe_exec_queue_create(xe, NULL, BIT(hwe->logical_instance), 1,
+ hwe, EXEC_QUEUE_FLAG_KERNEL, 0);
+ if (IS_ERR(q))
+ return PTR_ERR(q);
+
+ bb = xe_bb_new(hwe->gt, GGTT_INIT_BATCH_DWORDS, false);
+ if (IS_ERR(bb)) {
+ err = PTR_ERR(bb);
+ goto put_queue;
+ }
+ }
- /* Display may have allocated inside ggtt, so be careful with clearing here */
+ if (ggtt->scratch)
+ pte = xe_bo_addr(ggtt->scratch, 0, XE_PAGE_SIZE) |
+ ggtt->pt_ops->pte_encode_flags(ggtt->scratch, pat_index);
+
+ /* Preserve boot mappings and exclude allocator changes until completion. */
mutex_lock(&ggtt->lock);
- drm_mm_for_each_hole(hole, &ggtt->mm, start, end)
- xe_ggtt_clear(ggtt, ggtt->start + start, end - start);
+ drm_mm_for_each_hole(hole, &ggtt->mm, start, end) {
+ if (q)
+ err = ggtt_clear_gpu(q, bb, pte, ggtt->start + start, ggtt->start + end);
+ else
+ xe_ggtt_clear(ggtt, ggtt->start + start, end - start);
+ if (err)
+ goto unlock;
+ }
xe_ggtt_invalidate(ggtt);
+unlock:
mutex_unlock(&ggtt->lock);
+ xe_bb_free(bb, NULL);
+put_queue:
+ if (q)
+ xe_exec_queue_put(q);
+ return err;
+}
+
+/**
+ * xe_ggtt_init_late - Finish deferred GGTT initialization after GuC startup
+ * @ggtt: GGTT to initialize
+ *
+ * All default contexts must be recorded before waiting for a GPU clear with
+ * the GGTT mutex held, so reset recovery need not allocate context mappings.
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+int xe_ggtt_init_late(struct xe_ggtt *ggtt)
+{
+ if (!ggtt_use_gpu(tile_to_xe(ggtt->tile)))
+ return 0;
+
+ return xe_ggtt_initial_clear(ggtt, xe_gt_hw_engine(ggtt->tile->primary_gt,
+ XE_ENGINE_CLASS_COPY, 0, false));
}
static void ggtt_node_fini(struct xe_ggtt_node *node)
@@ -536,6 +642,9 @@ void xe_ggtt_node_remove(struct xe_ggtt_node *node, bool invalidate)
* xe_ggtt_init - Regular non-early GGTT initialization
* @ggtt: the &xe_ggtt to be initialized
*
+ * Allocate the scratch page if needed and clear unused entries, or defer
+ * the clear to xe_ggtt_init_late() when GPU initialization is enabled.
+ *
* Return: 0 on success or a negative error code on failure.
*/
int xe_ggtt_init(struct xe_ggtt *ggtt)
@@ -572,7 +681,8 @@ int xe_ggtt_init(struct xe_ggtt *ggtt)
xe_bo_size(ggtt->scratch));
}
- xe_ggtt_initial_clear(ggtt);
+ if (!ggtt_use_gpu(xe))
+ xe_ggtt_initial_clear(ggtt, NULL);
return devm_add_action_or_reset(xe->drm.dev, ggtt_fini, ggtt);
err:
diff --git a/drivers/gpu/drm/xe/xe_ggtt.h b/drivers/gpu/drm/xe/xe_ggtt.h
index c864cc975a69..cae8600d7142 100644
--- a/drivers/gpu/drm/xe/xe_ggtt.h
+++ b/drivers/gpu/drm/xe/xe_ggtt.h
@@ -17,6 +17,7 @@ struct xe_ggtt *xe_ggtt_alloc(struct xe_tile *tile);
int xe_ggtt_init_early(struct xe_ggtt *ggtt);
int xe_ggtt_init_kunit(struct xe_ggtt *ggtt, u32 reserved, u32 size);
int xe_ggtt_init(struct xe_ggtt *ggtt);
+int xe_ggtt_init_late(struct xe_ggtt *ggtt);
void xe_ggtt_shift_nodes(struct xe_ggtt *ggtt, u64 new_base);
u64 xe_ggtt_start(struct xe_ggtt *ggtt);
diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index 45fb074812a2..d1c14a02de66 100644
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -686,7 +686,8 @@ static int gt_init_with_all_forcewake(struct xe_gt *gt)
if (err)
return err;
- return 0;
+ return xe_gt_is_main_type(gt) ?
+ xe_ggtt_init_late(gt_to_tile(gt)->mem.ggtt) : 0;
}
static void xe_gt_fini(void *arg)
diff --git a/drivers/gpu/drm/xe/xe_module.c b/drivers/gpu/drm/xe/xe_module.c
index 897724cb5cfb..44cc0107cf53 100644
--- a/drivers/gpu/drm/xe/xe_module.c
+++ b/drivers/gpu/drm/xe/xe_module.c
@@ -22,6 +22,7 @@
#include "xe_sched_job.h"
struct xe_modparam xe_modparam = {
+ .ggtt_init_gpu = true,
.probe_display = XE_DEFAULT_PROBE_DISPLAY,
.guc_log_level = XE_DEFAULT_GUC_LOG_LEVEL,
.force_probe = XE_DEFAULT_FORCE_PROBE,
@@ -34,6 +35,10 @@ struct xe_modparam xe_modparam = {
/* the rest are 0 by default */
};
+module_param_named(ggtt_init_gpu, xe_modparam.ggtt_init_gpu, bool, 0444);
+MODULE_PARM_DESC(ggtt_init_gpu,
+ "GPU GGTT initialization on Lunar Lake (default: true)");
+
module_param_named(svm_notifier_size, xe_modparam.svm_notifier_size, uint, 0600);
MODULE_PARM_DESC(svm_notifier_size, "Set the svm notifier size in MiB, must be power of 2 "
"[default=" __stringify(XE_DEFAULT_SVM_NOTIFIER_SIZE) "]");
diff --git a/drivers/gpu/drm/xe/xe_module.h b/drivers/gpu/drm/xe/xe_module.h
index 6272d9e41207..8aa91822c35c 100644
--- a/drivers/gpu/drm/xe/xe_module.h
+++ b/drivers/gpu/drm/xe/xe_module.h
@@ -12,6 +12,7 @@ struct work_struct;
/* Module modprobe variables */
struct xe_modparam {
+ bool ggtt_init_gpu;
bool probe_display;
int force_vram_bar_size;
int guc_log_level;
^ permalink raw reply related [flat|nested] 8+ messages in thread
* ✗ LGCI.VerificationFailed: failure for drm/xe/ggtt: Cut GGTT initialization from 900 ms to 37 ms
2026-10-28 4:50 [RFC PATCH] drm/xe/ggtt: Cut GGTT initialization from 900 ms to 37 ms Daniel Colascione
@ 2026-10-28 13:09 ` Patchwork
2026-10-28 13:23 ` [RFC PATCH] " sashiko-bot
` (4 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2026-10-28 13:09 UTC (permalink / raw)
To: Daniel Colascione; +Cc: intel-xe
== Series Details ==
Series: drm/xe/ggtt: Cut GGTT initialization from 900 ms to 37 ms
URL : https://patchwork.freedesktop.org/series/177030/
State : failure
== Summary ==
Series author address 'dancol@dancol.org' is not on the allowlist, which prevents CI from being automatically triggered.
If you want CI to run for this series, ask Patchwork project owners to click 'retest' on the series in Patchwork.
Exception occurred during validation, bailing out!
Build URL: http://intel-gfx-ci-public.igk.intel.com:8080/job/xe_pw_trigger/1325670/ (on master)
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [RFC PATCH] drm/xe/ggtt: Cut GGTT initialization from 900 ms to 37 ms
2026-10-28 4:50 [RFC PATCH] drm/xe/ggtt: Cut GGTT initialization from 900 ms to 37 ms Daniel Colascione
2026-10-28 13:09 ` ✗ LGCI.VerificationFailed: failure for " Patchwork
@ 2026-10-28 13:23 ` sashiko-bot
2026-10-28 15:37 ` ✓ CI.KUnit: success for drm/xe/ggtt: Cut GGTT initialization from 900 ms to 37 ms (rev2) Patchwork
` (3 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: sashiko-bot @ 2026-10-28 13:23 UTC (permalink / raw)
To: Daniel Colascione, intel-xe; +Cc: dri-devel
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] drm/xe/ggtt: fs_reclaim lock inversion in ggtt_clear_gpu() under ggtt->lock
- [Low] drm/xe: missing kernel-parameters.txt entry for xe.ggtt_init_gpu
--
commit ed4c9843bc7f8d6478d283f57c556b54c7d8a262
Author: Daniel Colascione <dancol@dancol.org>
drm/xe/ggtt: Cut GGTT initialization from 900 ms to 37 ms
This patch uses the GPU copy engine to initialize GGTT page tables in batches
via MI_UPDATE_GTT commands on Lunar Lake, deferring the initial GGTT hole
clear to xe_ggtt_init_late() after GuC startup. It also adds the
xe.ggtt_init_gpu module parameter to toggle this behavior.
> diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
> index 9ef2ce743770f..47d12e5e95458 100644
> --- a/drivers/gpu/drm/xe/xe_ggtt.c
> +++ b/drivers/gpu/drm/xe/xe_ggtt.c
[ ... ]
> @@ -456,18 +461,119 @@ ALLOW_ERROR_INJECTION(xe_ggtt_init_early, ERRNO); /* See xe_pci_probe() */
[ ... ]
> +static int ggtt_clear_gpu(struct xe_exec_queue *q, struct xe_bb *bb,
> + u64 pte, u64 start, u64 end)
> +{
> + while (start < end) {
> + struct xe_sched_job *job;
> + int err;
> +
> + bb->len = 0;
> + while (start < end && bb->len < GGTT_INIT_BATCH_DWORDS) {
> + u32 count = min_t(u64, (end - start) >> XE_PTE_SHIFT,
> + GGTT_INIT_PTES_PER_PACKET);
> +
> + bb->cs[bb->len++] = MI_UPDATE_GTT | (2 * count);
> + bb->cs[bb->len++] = start;
> + memset64((u64 *)&bb->cs[bb->len], pte, count);
> + bb->len += 2 * count;
> + start += (u64)count << XE_PTE_SHIFT;
> + }
> +
> + job = xe_bb_create_job(q, bb);
> + if (IS_ERR(job))
> + return PTR_ERR(job);
[ ... ]
> +static int xe_ggtt_initial_clear(struct xe_ggtt *ggtt, struct xe_hw_engine *hwe)
> +{
[ ... ]
> + /* Preserve boot mappings and exclude allocator changes until completion. */
> mutex_lock(&ggtt->lock);
> - drm_mm_for_each_hole(hole, &ggtt->mm, start, end)
> - xe_ggtt_clear(ggtt, ggtt->start + start, end - start);
> + drm_mm_for_each_hole(hole, &ggtt->mm, start, end) {
> + if (q)
> + err = ggtt_clear_gpu(q, bb, pte, ggtt->start + start, ggtt->start + end);
> + else
> + xe_ggtt_clear(ggtt, ggtt->start + start, end - start);
> + if (err)
> + goto unlock;
> + }
[Severity: High]
Does calling ggtt_clear_gpu() while holding ggtt->lock cause an fs_reclaim
lock inversion?
During allocation in xe_ggtt_alloc(), primelockdep() in
drivers/gpu/drm/xe/xe_ggtt.c establishes the ordering fs_reclaim ->
ggtt->lock because BO destruction during memory reclaim acquires ggtt->lock:
static void primelockdep(struct xe_ggtt *ggtt)
{
if (!IS_ENABLED(CONFIG_LOCKDEP))
return;
fs_reclaim_acquire(GFP_KERNEL);
might_lock(&ggtt->lock);
fs_reclaim_release(GFP_KERNEL);
}
However, on Lunar Lake with xe.ggtt_init_gpu enabled,
gt_init_with_all_forcewake() -> xe_ggtt_init_late() -> xe_ggtt_initial_clear()
acquires ggtt->lock and calls ggtt_clear_gpu(), which invokes
xe_bb_create_job() -> __xe_bb_create_job() -> xe_sched_job_create().
Inside xe_sched_job_create(), several GFP_KERNEL allocations occur under
ggtt->lock, including job_alloc() in drivers/gpu/drm/xe/xe_sched_job.c:
static struct xe_sched_job *job_alloc(bool parallel)
{
return kmem_cache_zalloc(parallel ? xe_sched_job_parallel_slab :
xe_sched_job_slab, GFP_KERNEL);
}
as well as drm_sched_job_init() and xe_lrc_alloc_seqno_fence() ->
xe_hw_fence_alloc() -> fence_alloc() in drivers/gpu/drm/xe/xe_hw_fence.c:
return kmem_cache_zalloc(xe_hw_fence_slab, GFP_KERNEL);
Wouldn't this violate the fs_reclaim -> ggtt->lock hierarchy, triggering a
lockdep circular locking warning under CONFIG_PROVE_LOCKING during probe and
risking a reclaim deadlock if direct reclaim attempts to free a GGTT-mapped
BO?
> diff --git a/drivers/gpu/drm/xe/xe_module.c b/drivers/gpu/drm/xe/xe_module.c
> index 897724cb5cfb8..44cc0107cf53a 100644
> --- a/drivers/gpu/drm/xe/xe_module.c
> +++ b/drivers/gpu/drm/xe/xe_module.c
> @@ -22,6 +22,7 @@
> #include "xe_sched_job.h"
>
> struct xe_modparam xe_modparam = {
> + .ggtt_init_gpu = true,
> .probe_display = XE_DEFAULT_PROBE_DISPLAY,
> .guc_log_level = XE_DEFAULT_GUC_LOG_LEVEL,
> .force_probe = XE_DEFAULT_FORCE_PROBE,
> @@ -34,6 +35,10 @@ struct xe_modparam xe_modparam = {
> /* the rest are 0 by default */
> };
>
> +module_param_named(ggtt_init_gpu, xe_modparam.ggtt_init_gpu, bool, 0444);
> +MODULE_PARM_DESC(ggtt_init_gpu,
> + "GPU GGTT initialization on Lunar Lake (default: true)");
[Severity: Low]
Should this new xe.ggtt_init_gpu module parameter also be documented in
Documentation/admin-guide/kernel-parameters.txt?
--
Sashiko AI review · https://sashiko.dev/#/patchset/87v76m1l9k.fsf@dancol.org?part=1
^ permalink raw reply [flat|nested] 8+ messages in thread
* ✓ CI.KUnit: success for drm/xe/ggtt: Cut GGTT initialization from 900 ms to 37 ms (rev2)
2026-10-28 4:50 [RFC PATCH] drm/xe/ggtt: Cut GGTT initialization from 900 ms to 37 ms Daniel Colascione
2026-10-28 13:09 ` ✗ LGCI.VerificationFailed: failure for " Patchwork
2026-10-28 13:23 ` [RFC PATCH] " sashiko-bot
@ 2026-10-28 15:37 ` Patchwork
2026-10-28 16:11 ` ✗ Xe.CI.BAT: failure " Patchwork
` (2 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2026-10-28 15:37 UTC (permalink / raw)
To: Daniel Colascione; +Cc: intel-xe
== Series Details ==
Series: drm/xe/ggtt: Cut GGTT initialization from 900 ms to 37 ms (rev2)
URL : https://patchwork.freedesktop.org/series/177030/
State : success
== Summary ==
+ trap cleanup EXIT
+ kunitconfigs=('/kernel/drivers/gpu/tests/.kunitconfig' '/kernel/drivers/gpu/drm/xe/.kunitconfig' '/kernel/drivers/gpu/drm/tests/.kunitconfig' '/kernel/drivers/gpu/drm/ttm/tests/.kunitconfig' '/kernel/drivers/dma-buf/.kunitconfig')
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/tests/.kunitconfig
[15:34:52] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[15:34:56] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[15:35:17] Starting KUnit Kernel (1/1)...
[15:35:17] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[15:35:17] ================= gpu_buddy (14 subtests) ==================
[15:35:17] [PASSED] gpu_test_buddy_alloc_limit
[15:35:17] [PASSED] gpu_test_buddy_alloc_optimistic
[15:35:17] [PASSED] gpu_test_buddy_alloc_pessimistic
[15:35:17] [PASSED] gpu_test_buddy_alloc_pathological
[15:35:17] [PASSED] gpu_test_buddy_alloc_contiguous
[15:35:17] [PASSED] gpu_test_buddy_alloc_clear
[15:35:17] [PASSED] gpu_test_buddy_alloc_range
[15:35:17] [PASSED] gpu_test_buddy_alloc_range_bias
[15:35:18] [PASSED] gpu_test_buddy_fragmentation_performance
[15:35:18] [PASSED] gpu_test_buddy_dirty_tracker_performance
[15:35:18] [PASSED] gpu_test_buddy_alloc_exceeds_max_order
[15:35:18] [PASSED] gpu_test_buddy_offset_aligned_allocation
[15:35:18] [PASSED] gpu_test_buddy_subtree_offset_alignment_stress
[15:35:18] [PASSED] gpu_test_buddy_addr_to_block
[15:35:18] ==================== [PASSED] gpu_buddy ====================
[15:35:18] ============================================================
[15:35:18] Testing complete. Ran 14 tests: passed: 14
[15:35:18] Elapsed time: 26.519s total, 4.438s configuring, 20.214s building, 1.823s running
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/xe/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[15:35:19] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[15:35:20] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[15:36:00] Starting KUnit Kernel (1/1)...
[15:36:00] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[15:36:00] ================== guc_buf (11 subtests) ===================
[15:36:00] [PASSED] test_smallest
[15:36:00] [PASSED] test_largest
[15:36:00] [PASSED] test_granular
[15:36:00] [PASSED] test_unique
[15:36:00] [PASSED] test_overlap
[15:36:00] [PASSED] test_reusable
[15:36:00] [PASSED] test_too_big
[15:36:00] [PASSED] test_flush
[15:36:00] [PASSED] test_lookup
[15:36:00] [PASSED] test_data
[15:36:00] [PASSED] test_class
[15:36:00] ===================== [PASSED] guc_buf =====================
[15:36:00] =================== guc_dbm (7 subtests) ===================
[15:36:00] [PASSED] test_empty
[15:36:00] [PASSED] test_default
[15:36:00] ======================== test_size ========================
[15:36:00] [PASSED] 4
[15:36:00] [PASSED] 8
[15:36:00] [PASSED] 32
[15:36:00] [PASSED] 256
[15:36:00] ==================== [PASSED] test_size ====================
[15:36:00] ======================= test_reuse ========================
[15:36:00] [PASSED] 4
[15:36:00] [PASSED] 8
[15:36:00] [PASSED] 32
[15:36:00] [PASSED] 256
[15:36:00] =================== [PASSED] test_reuse ====================
[15:36:00] =================== test_range_overlap ====================
[15:36:00] [PASSED] 4
[15:36:00] [PASSED] 8
[15:36:00] [PASSED] 32
[15:36:00] [PASSED] 256
[15:36:00] =============== [PASSED] test_range_overlap ================
[15:36:00] =================== test_range_compact ====================
[15:36:00] [PASSED] 4
[15:36:00] [PASSED] 8
[15:36:00] [PASSED] 32
[15:36:00] [PASSED] 256
[15:36:00] =============== [PASSED] test_range_compact ================
[15:36:00] ==================== test_range_spare =====================
[15:36:00] [PASSED] 4
[15:36:00] [PASSED] 8
[15:36:00] [PASSED] 32
[15:36:00] [PASSED] 256
[15:36:00] ================ [PASSED] test_range_spare =================
[15:36:00] ===================== [PASSED] guc_dbm =====================
[15:36:00] ================== guc_idm (22 subtests) ===================
[15:36:00] [PASSED] bad_init
[15:36:00] [PASSED] no_init
[15:36:00] [PASSED] init_fini
[15:36:00] [PASSED] check_init_small
[15:36:00] [PASSED] check_init_shared
[15:36:00] [PASSED] check_used
[15:36:00] [PASSED] check_quota
[15:36:00] [PASSED] check_all
[15:36:00] [PASSED] check_limits
[15:36:00] [PASSED] check_overlap
[15:36:00] [PASSED] check_overlap_alloc
[15:36:00] [PASSED] check_overlap_release
[15:36:00] [PASSED] check_overlap_partial_init
[15:36:00] [PASSED] check_overlap_partial_shared_range_blocking
[15:36:00] [PASSED] check_used_usable
[15:36:00] [PASSED] check_used_shareable
[15:36:00] [PASSED] check_used_mixed
[15:36:00] [PASSED] check_release_usable_range
[15:36:00] [PASSED] check_release_shareable_range
[15:36:00] [PASSED] check_split_boundaries
[15:36:00] [PASSED] check_shareable_spare
[15:36:00] [PASSED] check_shareable_spare_fragmented_tail
[15:36:00] ===================== [PASSED] guc_idm =====================
[15:36:00] ============== guc_klv_helpers (13 subtests) ===============
[15:36:00] [PASSED] test_count
[15:36:00] [PASSED] test_encode_u32
[15:36:00] [PASSED] test_encode_u64
[15:36:00] [PASSED] test_encode_string
[15:36:00] [PASSED] test_encode_object_raw
[15:36:00] [PASSED] test_encode_object_klv
[15:36:00] [PASSED] test_encode_object_nested
[15:36:00] [PASSED] test_encode_object_basic
[15:36:00] ===================== test_decode_u16 =====================
[15:36:00] [PASSED] empty
[15:36:00] [PASSED] valid
[15:36:00] [PASSED] max
[15:36:00] [PASSED] big
[15:36:00] [PASSED] long
[15:36:00] ================= [PASSED] test_decode_u16 =================
[15:36:00] ===================== test_decode_u32 =====================
[15:36:00] [PASSED] empty
[15:36:00] [PASSED] valid
[15:36:00] [PASSED] max
[15:36:00] [PASSED] long
[15:36:00] ================= [PASSED] test_decode_u32 =================
[15:36:00] ===================== test_decode_u64 =====================
[15:36:00] [PASSED] empty
[15:36:00] [PASSED] short
[15:36:00] [PASSED] valid
[15:36:00] [PASSED] max
[15:36:00] [PASSED] long
[15:36:00] ================= [PASSED] test_decode_u64 =================
[15:36:00] ===================== test_decode_str =====================
[15:36:00] [PASSED] empty
[15:36:00] [PASSED] one
[15:36:00] [PASSED] one_trash
[15:36:00] [PASSED] two
[15:36:00] [PASSED] two_trash
[15:36:00] [PASSED] three
[15:36:00] [PASSED] dword
[15:36:00] [PASSED] four
[15:36:00] [PASSED] five
[15:36:00] [PASSED] six
[15:36:00] [PASSED] seven
[15:36:00] [PASSED] qword
[15:36:00] ================= [PASSED] test_decode_str =================
[15:36:00] [PASSED] test_print
[15:36:00] ================= [PASSED] guc_klv_helpers =================
[15:36:00] =================== xe_log (4 subtests) ====================
[15:36:00] [PASSED] demo_cper
[15:36:00] [PASSED] demo_dmesg
[15:36:00] ======================= test_dmesg ========================
[15:36:00] [PASSED] test_fatal
[15:36:00] [PASSED] test_fatal_tile
[15:36:00] [PASSED] test_fatal_gt
[15:36:00] [PASSED] test_fatal_comp
[15:36:00] [PASSED] test_fatal_comp_tile
[15:36:00] [PASSED] test_fatal_comp_gt
[15:36:00] [PASSED] test_fatal_all
[15:36:00] [PASSED] test_recoverable
[15:36:00] [PASSED] test_recoverable_tile
[15:36:00] [PASSED] test_recoverable_gt
[15:36:00] [PASSED] test_recoverable_comp
[15:36:00] [PASSED] test_recoverable_comp_tile
[15:36:00] [PASSED] test_recoverable_comp_gt
[15:36:00] [PASSED] test_recoverable_all
[15:36:00] [PASSED] test_info
[15:36:00] [PASSED] test_info_tile
[15:36:00] [PASSED] test_info_gt
[15:36:00] [PASSED] test_info_err
[15:36:00] [PASSED] test_info_comp
[15:36:00] [PASSED] test_info_comp_tile
[15:36:00] [PASSED] test_info_comp_gt
[15:36:00] [PASSED] test_info_all
[15:36:00] [PASSED] test_hw_fatal
[15:36:00] [PASSED] test_hw_recoverable
[15:36:00] [PASSED] test_hw_corrected
[15:36:00] [PASSED] test_hw_informational
[15:36:00] =================== [PASSED] test_dmesg ====================
[15:36:00] ====================== test_invalid =======================
[15:36:00] [SKIPPED] no-component no-location no-warn (requires CONFIG_DRM_XE_DEBUG)
[15:36:00] [SKIPPED] reserved location (requires CONFIG_DRM_XE_DEBUG)
[15:36:00] [SKIPPED] unknown location (requires CONFIG_DRM_XE_DEBUG)
[15:36:00] [SKIPPED] nonzero-device-id location (requires CONFIG_DRM_XE_DEBUG)
[15:36:00] [SKIPPED] invalid-tile-id location (requires CONFIG_DRM_XE_DEBUG)
[15:36:00] [SKIPPED] invalid-gt-id location (requires CONFIG_DRM_XE_DEBUG)
[15:36:00] [SKIPPED] unknown component class (requires CONFIG_DRM_XE_DEBUG)
[15:36:00] [SKIPPED] unknown system component (requires CONFIG_DRM_XE_DEBUG)
[15:36:00] [SKIPPED] unknown hardware component (requires CONFIG_DRM_XE_DEBUG)
[15:36:00] [SKIPPED] unknown component and location (requires CONFIG_DRM_XE_DEBUG)
[15:36:00] ================== [SKIPPED] test_invalid ==================
[15:36:00] ===================== [PASSED] xe_log ======================
[15:36:00] ================== no_relay (3 subtests) ===================
[15:36:00] [PASSED] xe_drops_guc2pf_if_not_ready
[15:36:00] [PASSED] xe_drops_guc2vf_if_not_ready
[15:36:00] [PASSED] xe_rejects_send_if_not_ready
[15:36:00] ==================== [PASSED] no_relay =====================
[15:36:00] ================== pf_relay (14 subtests) ==================
[15:36:00] [PASSED] pf_rejects_guc2pf_too_short
[15:36:00] [PASSED] pf_rejects_guc2pf_too_long
[15:36:00] [PASSED] pf_rejects_guc2pf_no_payload
[15:36:00] [PASSED] pf_fails_no_payload
[15:36:00] [PASSED] pf_fails_bad_origin
[15:36:00] [PASSED] pf_fails_bad_type
[15:36:00] [PASSED] pf_txn_reports_error
[15:36:00] [PASSED] pf_txn_sends_pf2guc
[15:36:00] [PASSED] pf_sends_pf2guc
[15:36:00] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[15:36:00] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[15:36:00] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[15:36:00] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[15:36:00] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[15:36:00] ==================== [PASSED] pf_relay =====================
[15:36:00] ================== vf_relay (3 subtests) ===================
[15:36:00] [PASSED] vf_rejects_guc2vf_too_short
[15:36:00] [PASSED] vf_rejects_guc2vf_too_long
[15:36:00] [PASSED] vf_rejects_guc2vf_no_payload
[15:36:00] ==================== [PASSED] vf_relay =====================
[15:36:00] ================ pf_gt_config (9 subtests) =================
[15:36:00] [PASSED] fair_contexts_1vf
[15:36:00] [PASSED] fair_doorbells_1vf
[15:36:00] [PASSED] fair_ggtt_1vf
[15:36:00] ====================== fair_vram_1vf ======================
[15:36:00] [PASSED] 3.50 GiB
[15:36:00] [PASSED] 11.5 GiB
[15:36:00] [PASSED] 15.5 GiB
[15:36:00] [PASSED] 31.5 GiB
[15:36:00] [PASSED] 63.5 GiB
[15:36:00] [PASSED] 1.91 GiB
[15:36:00] ================== [PASSED] fair_vram_1vf ==================
[15:36:00] ================ fair_vram_1vf_admin_only =================
[15:36:00] [PASSED] 3.50 GiB
[15:36:00] [PASSED] 11.5 GiB
[15:36:00] [PASSED] 15.5 GiB
[15:36:00] [PASSED] 31.5 GiB
[15:36:00] [PASSED] 63.5 GiB
[15:36:00] [PASSED] 1.91 GiB
[15:36:00] ============ [PASSED] fair_vram_1vf_admin_only =============
[15:36:00] ====================== fair_contexts ======================
[15:36:00] [PASSED] 1 VF
[15:36:00] [PASSED] 2 VFs
[15:36:00] [PASSED] 3 VFs
[15:36:00] [PASSED] 4 VFs
[15:36:00] [PASSED] 5 VFs
[15:36:00] [PASSED] 6 VFs
[15:36:00] [PASSED] 7 VFs
[15:36:00] [PASSED] 8 VFs
[15:36:00] [PASSED] 9 VFs
[15:36:00] [PASSED] 10 VFs
[15:36:00] [PASSED] 11 VFs
[15:36:00] [PASSED] 12 VFs
[15:36:00] [PASSED] 13 VFs
[15:36:00] [PASSED] 14 VFs
[15:36:00] [PASSED] 15 VFs
[15:36:00] [PASSED] 16 VFs
[15:36:00] [PASSED] 17 VFs
[15:36:00] [PASSED] 18 VFs
[15:36:00] [PASSED] 19 VFs
[15:36:00] [PASSED] 20 VFs
[15:36:00] [PASSED] 21 VFs
[15:36:00] [PASSED] 22 VFs
[15:36:00] [PASSED] 23 VFs
[15:36:00] [PASSED] 24 VFs
[15:36:00] [PASSED] 25 VFs
[15:36:00] [PASSED] 26 VFs
[15:36:00] [PASSED] 27 VFs
[15:36:00] [PASSED] 28 VFs
[15:36:00] [PASSED] 29 VFs
[15:36:00] [PASSED] 30 VFs
[15:36:00] [PASSED] 31 VFs
[15:36:00] [PASSED] 32 VFs
[15:36:00] [PASSED] 33 VFs
[15:36:00] [PASSED] 34 VFs
[15:36:00] [PASSED] 35 VFs
[15:36:00] [PASSED] 36 VFs
[15:36:00] [PASSED] 37 VFs
[15:36:00] [PASSED] 38 VFs
[15:36:00] [PASSED] 39 VFs
[15:36:00] [PASSED] 40 VFs
[15:36:00] [PASSED] 41 VFs
[15:36:00] [PASSED] 42 VFs
[15:36:00] [PASSED] 43 VFs
[15:36:00] [PASSED] 44 VFs
[15:36:00] [PASSED] 45 VFs
[15:36:00] [PASSED] 46 VFs
[15:36:00] [PASSED] 47 VFs
[15:36:00] [PASSED] 48 VFs
[15:36:00] [PASSED] 49 VFs
[15:36:00] [PASSED] 50 VFs
[15:36:00] [PASSED] 51 VFs
[15:36:00] [PASSED] 52 VFs
[15:36:00] [PASSED] 53 VFs
[15:36:00] [PASSED] 54 VFs
[15:36:00] [PASSED] 55 VFs
[15:36:00] [PASSED] 56 VFs
[15:36:00] [PASSED] 57 VFs
[15:36:00] [PASSED] 58 VFs
[15:36:00] [PASSED] 59 VFs
[15:36:00] [PASSED] 60 VFs
[15:36:00] [PASSED] 61 VFs
[15:36:00] [PASSED] 62 VFs
[15:36:00] [PASSED] 63 VFs
[15:36:00] ================== [PASSED] fair_contexts ==================
[15:36:00] ===================== fair_doorbells ======================
[15:36:00] [PASSED] 1 VF
[15:36:00] [PASSED] 2 VFs
[15:36:00] [PASSED] 3 VFs
[15:36:00] [PASSED] 4 VFs
[15:36:00] [PASSED] 5 VFs
[15:36:00] [PASSED] 6 VFs
[15:36:00] [PASSED] 7 VFs
[15:36:00] [PASSED] 8 VFs
[15:36:00] [PASSED] 9 VFs
[15:36:00] [PASSED] 10 VFs
[15:36:00] [PASSED] 11 VFs
[15:36:00] [PASSED] 12 VFs
[15:36:00] [PASSED] 13 VFs
[15:36:00] [PASSED] 14 VFs
[15:36:00] [PASSED] 15 VFs
[15:36:00] [PASSED] 16 VFs
[15:36:00] [PASSED] 17 VFs
[15:36:00] [PASSED] 18 VFs
[15:36:00] [PASSED] 19 VFs
[15:36:00] [PASSED] 20 VFs
[15:36:00] [PASSED] 21 VFs
[15:36:00] [PASSED] 22 VFs
[15:36:00] [PASSED] 23 VFs
[15:36:00] [PASSED] 24 VFs
[15:36:00] [PASSED] 25 VFs
[15:36:00] [PASSED] 26 VFs
[15:36:00] [PASSED] 27 VFs
[15:36:00] [PASSED] 28 VFs
[15:36:00] [PASSED] 29 VFs
[15:36:00] [PASSED] 30 VFs
[15:36:00] [PASSED] 31 VFs
[15:36:00] [PASSED] 32 VFs
[15:36:00] [PASSED] 33 VFs
[15:36:00] [PASSED] 34 VFs
[15:36:00] [PASSED] 35 VFs
[15:36:00] [PASSED] 36 VFs
[15:36:00] [PASSED] 37 VFs
[15:36:00] [PASSED] 38 VFs
[15:36:00] [PASSED] 39 VFs
[15:36:00] [PASSED] 40 VFs
[15:36:00] [PASSED] 41 VFs
[15:36:00] [PASSED] 42 VFs
[15:36:00] [PASSED] 43 VFs
[15:36:00] [PASSED] 44 VFs
[15:36:00] [PASSED] 45 VFs
[15:36:00] [PASSED] 46 VFs
[15:36:00] [PASSED] 47 VFs
[15:36:00] [PASSED] 48 VFs
[15:36:00] [PASSED] 49 VFs
[15:36:00] [PASSED] 50 VFs
[15:36:00] [PASSED] 51 VFs
[15:36:00] [PASSED] 52 VFs
[15:36:00] [PASSED] 53 VFs
[15:36:00] [PASSED] 54 VFs
[15:36:00] [PASSED] 55 VFs
[15:36:00] [PASSED] 56 VFs
[15:36:00] [PASSED] 57 VFs
[15:36:00] [PASSED] 58 VFs
[15:36:00] [PASSED] 59 VFs
[15:36:00] [PASSED] 60 VFs
[15:36:00] [PASSED] 61 VFs
[15:36:00] [PASSED] 62 VFs
[15:36:00] [PASSED] 63 VFs
[15:36:00] ================= [PASSED] fair_doorbells ==================
[15:36:00] ======================== fair_ggtt ========================
[15:36:00] [PASSED] 1 VF
[15:36:00] [PASSED] 2 VFs
[15:36:00] [PASSED] 3 VFs
[15:36:00] [PASSED] 4 VFs
[15:36:00] [PASSED] 5 VFs
[15:36:00] [PASSED] 6 VFs
[15:36:00] [PASSED] 7 VFs
[15:36:00] [PASSED] 8 VFs
[15:36:00] [PASSED] 9 VFs
[15:36:00] [PASSED] 10 VFs
[15:36:00] [PASSED] 11 VFs
[15:36:00] [PASSED] 12 VFs
[15:36:00] [PASSED] 13 VFs
[15:36:00] [PASSED] 14 VFs
[15:36:00] [PASSED] 15 VFs
[15:36:00] [PASSED] 16 VFs
[15:36:00] [PASSED] 17 VFs
[15:36:00] [PASSED] 18 VFs
[15:36:00] [PASSED] 19 VFs
[15:36:00] [PASSED] 20 VFs
[15:36:00] [PASSED] 21 VFs
[15:36:00] [PASSED] 22 VFs
[15:36:00] [PASSED] 23 VFs
[15:36:00] [PASSED] 24 VFs
[15:36:00] [PASSED] 25 VFs
[15:36:00] [PASSED] 26 VFs
[15:36:00] [PASSED] 27 VFs
[15:36:00] [PASSED] 28 VFs
[15:36:00] [PASSED] 29 VFs
[15:36:00] [PASSED] 30 VFs
[15:36:00] [PASSED] 31 VFs
[15:36:00] [PASSED] 32 VFs
[15:36:00] [PASSED] 33 VFs
[15:36:00] [PASSED] 34 VFs
[15:36:00] [PASSED] 35 VFs
[15:36:00] [PASSED] 36 VFs
[15:36:00] [PASSED] 37 VFs
[15:36:00] [PASSED] 38 VFs
[15:36:00] [PASSED] 39 VFs
[15:36:00] [PASSED] 40 VFs
[15:36:00] [PASSED] 41 VFs
[15:36:00] [PASSED] 42 VFs
[15:36:00] [PASSED] 43 VFs
[15:36:00] [PASSED] 44 VFs
[15:36:00] [PASSED] 45 VFs
[15:36:00] [PASSED] 46 VFs
[15:36:00] [PASSED] 47 VFs
[15:36:00] [PASSED] 48 VFs
[15:36:00] [PASSED] 49 VFs
[15:36:00] [PASSED] 50 VFs
[15:36:00] [PASSED] 51 VFs
[15:36:00] [PASSED] 52 VFs
[15:36:00] [PASSED] 53 VFs
[15:36:00] [PASSED] 54 VFs
[15:36:00] [PASSED] 55 VFs
[15:36:00] [PASSED] 56 VFs
[15:36:00] [PASSED] 57 VFs
[15:36:00] [PASSED] 58 VFs
[15:36:00] [PASSED] 59 VFs
[15:36:00] [PASSED] 60 VFs
[15:36:00] [PASSED] 61 VFs
[15:36:00] [PASSED] 62 VFs
[15:36:00] [PASSED] 63 VFs
[15:36:00] ==================== [PASSED] fair_ggtt ====================
[15:36:00] ======================== fair_vram ========================
[15:36:00] [PASSED] 1 VF
[15:36:00] [PASSED] 2 VFs
[15:36:00] [PASSED] 3 VFs
[15:36:00] [PASSED] 4 VFs
[15:36:00] [PASSED] 5 VFs
[15:36:00] [PASSED] 6 VFs
[15:36:00] [PASSED] 7 VFs
[15:36:00] [PASSED] 8 VFs
[15:36:00] [PASSED] 9 VFs
[15:36:00] [PASSED] 10 VFs
[15:36:00] [PASSED] 11 VFs
[15:36:00] [PASSED] 12 VFs
[15:36:00] [PASSED] 13 VFs
[15:36:00] [PASSED] 14 VFs
[15:36:00] [PASSED] 15 VFs
[15:36:00] [PASSED] 16 VFs
[15:36:00] [PASSED] 17 VFs
[15:36:00] [PASSED] 18 VFs
[15:36:00] [PASSED] 19 VFs
[15:36:00] [PASSED] 20 VFs
[15:36:00] [PASSED] 21 VFs
[15:36:00] [PASSED] 22 VFs
[15:36:00] [PASSED] 23 VFs
[15:36:00] [PASSED] 24 VFs
[15:36:00] [PASSED] 25 VFs
[15:36:00] [PASSED] 26 VFs
[15:36:00] [PASSED] 27 VFs
[15:36:00] [PASSED] 28 VFs
[15:36:00] [PASSED] 29 VFs
[15:36:00] [PASSED] 30 VFs
[15:36:00] [PASSED] 31 VFs
[15:36:00] [PASSED] 32 VFs
[15:36:00] [PASSED] 33 VFs
[15:36:00] [PASSED] 34 VFs
[15:36:00] [PASSED] 35 VFs
[15:36:00] [PASSED] 36 VFs
[15:36:00] [PASSED] 37 VFs
[15:36:00] [PASSED] 38 VFs
[15:36:00] [PASSED] 39 VFs
[15:36:00] [PASSED] 40 VFs
[15:36:00] [PASSED] 41 VFs
[15:36:00] [PASSED] 42 VFs
[15:36:00] [PASSED] 43 VFs
[15:36:00] [PASSED] 44 VFs
[15:36:00] [PASSED] 45 VFs
[15:36:00] [PASSED] 46 VFs
[15:36:00] [PASSED] 47 VFs
[15:36:00] [PASSED] 48 VFs
[15:36:00] [PASSED] 49 VFs
[15:36:00] [PASSED] 50 VFs
[15:36:00] [PASSED] 51 VFs
[15:36:00] [PASSED] 52 VFs
[15:36:00] [PASSED] 53 VFs
[15:36:00] [PASSED] 54 VFs
[15:36:00] [PASSED] 55 VFs
[15:36:00] [PASSED] 56 VFs
[15:36:00] [PASSED] 57 VFs
[15:36:00] [PASSED] 58 VFs
[15:36:00] [PASSED] 59 VFs
[15:36:00] [PASSED] 60 VFs
[15:36:00] [PASSED] 61 VFs
[15:36:00] [PASSED] 62 VFs
[15:36:00] [PASSED] 63 VFs
[15:36:00] ==================== [PASSED] fair_vram ====================
[15:36:00] ================== [PASSED] pf_gt_config ===================
[15:36:00] ===================== lmtt (1 subtest) =====================
[15:36:00] ======================== test_ops =========================
[15:36:00] [PASSED] 2-level
[15:36:00] [PASSED] multi-level
[15:36:00] ==================== [PASSED] test_ops =====================
[15:36:00] ====================== [PASSED] lmtt =======================
[15:36:00] ================= sriov_packet (1 subtest) =================
[15:36:00] [PASSED] test_descriptor_init
[15:36:00] ================== [PASSED] sriov_packet ===================
[15:36:00] ================= pf_service (11 subtests) =================
[15:36:00] [PASSED] pf_negotiate_any
[15:36:00] [PASSED] pf_negotiate_base_match
[15:36:00] [PASSED] pf_negotiate_base_newer
[15:36:00] [PASSED] pf_negotiate_base_next
[15:36:00] [SKIPPED] pf_negotiate_base_older (no older minor)
[15:36:00] [PASSED] pf_negotiate_base_prev
[15:36:00] [PASSED] pf_negotiate_latest_match
[15:36:00] [PASSED] pf_negotiate_latest_newer
[15:36:00] [PASSED] pf_negotiate_latest_next
[15:36:00] [SKIPPED] pf_negotiate_latest_older (no older minor)
[15:36:00] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[15:36:00] =================== [PASSED] pf_service ====================
[15:36:00] ================= xe_guc_g2g (2 subtests) ==================
[15:36:00] ============== xe_live_guc_g2g_kunit_default ==============
[15:36:00] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[15:36:00] ============== xe_live_guc_g2g_kunit_allmem ===============
[15:36:00] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[15:36:00] =================== [SKIPPED] xe_guc_g2g ===================
[15:36:00] =================== xe_mocs (2 subtests) ===================
[15:36:00] ================ xe_live_mocs_kernel_kunit ================
[15:36:00] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[15:36:00] ================ xe_live_mocs_reset_kunit =================
[15:36:00] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[15:36:00] ==================== [SKIPPED] xe_mocs =====================
[15:36:00] ================= xe_migrate (3 subtests) ==================
[15:36:00] ================= xe_migrate_sanity_kunit =================
[15:36:00] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[15:36:00] ================== xe_validate_ccs_kunit ==================
[15:36:00] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[15:36:00] ============= xe_migrate_access_memory_kunit ==============
[15:36:00] ========= [SKIPPED] xe_migrate_access_memory_kunit =========
[15:36:00] =================== [SKIPPED] xe_migrate ===================
[15:36:00] ================== xe_dma_buf (1 subtest) ==================
[15:36:00] ==================== xe_dma_buf_kunit =====================
[15:36:00] ================ [SKIPPED] xe_dma_buf_kunit ================
[15:36:00] =================== [SKIPPED] xe_dma_buf ===================
[15:36:00] ================= xe_bo_shrink (1 subtest) =================
[15:36:00] =================== xe_bo_shrink_kunit ====================
[15:36:00] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[15:36:00] ================== [SKIPPED] xe_bo_shrink ==================
[15:36:00] ==================== xe_bo (2 subtests) ====================
[15:36:00] ================== xe_ccs_migrate_kunit ===================
[15:36:00] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[15:36:00] ==================== xe_bo_evict_kunit ====================
[15:36:00] =============== [SKIPPED] xe_bo_evict_kunit ================
[15:36:00] ===================== [SKIPPED] xe_bo ======================
[15:36:00] =================== xe_any (9 subtests) ====================
[15:36:00] [PASSED] test_to_xe
[15:36:00] [PASSED] test_to_dev
[15:36:00] [PASSED] test_to_pdev
[15:36:00] [PASSED] test_to_drm
[15:36:00] [PASSED] test_if_pdev
[15:36:00] [PASSED] test_if_xe
[15:36:00] [PASSED] test_if_tile
[15:36:00] [PASSED] test_if_gt
[15:36:00] [PASSED] test_to_id
[15:36:00] ===================== [PASSED] xe_any ======================
[15:36:00] ==================== args (13 subtests) ====================
[15:36:00] [PASSED] count_args_test
[15:36:00] [PASSED] call_args_example
[15:36:00] [PASSED] call_args_test
[15:36:00] [PASSED] drop_first_arg_example
[15:36:00] [PASSED] drop_first_arg_test
[15:36:00] [PASSED] first_arg_example
[15:36:00] [PASSED] first_arg_test
[15:36:00] [PASSED] last_arg_example
[15:36:00] [PASSED] last_arg_test
[15:36:00] [PASSED] pick_arg_example
[15:36:00] [PASSED] if_args_example
[15:36:00] [PASSED] if_args_test
[15:36:00] [PASSED] sep_comma_example
[15:36:00] ====================== [PASSED] args =======================
[15:36:00] =================== xe_pci (3 subtests) ====================
[15:36:00] ==================== check_graphics_ip ====================
[15:36:00] [PASSED] 12.00 Xe_LP
[15:36:00] [PASSED] 12.10 Xe_LP+
[15:36:00] [PASSED] 12.55 Xe_HPG
[15:36:00] [PASSED] 12.60 Xe_HPC
[15:36:00] [PASSED] 12.70 Xe_LPG
[15:36:00] [PASSED] 12.71 Xe_LPG
[15:36:00] [PASSED] 12.74 Xe_LPG+
[15:36:00] [PASSED] 20.01 Xe2_HPG
[15:36:00] [PASSED] 20.02 Xe2_HPG
[15:36:00] [PASSED] 20.04 Xe2_LPG
[15:36:00] [PASSED] 30.00 Xe3_LPG
[15:36:00] [PASSED] 30.01 Xe3_LPG
[15:36:00] [PASSED] 30.03 Xe3_LPG
[15:36:00] [PASSED] 30.04 Xe3_LPG
[15:36:00] [PASSED] 30.05 Xe3_LPG
[15:36:00] [PASSED] 35.10 Xe3p_LPG
[15:36:00] [PASSED] 35.11 Xe3p_XPC
[15:36:00] ================ [PASSED] check_graphics_ip ================
[15:36:00] ===================== check_media_ip ======================
[15:36:00] [PASSED] 12.00 Xe_M
[15:36:00] [PASSED] 12.55 Xe_HPM
[15:36:00] [PASSED] 13.00 Xe_LPM+
[15:36:00] [PASSED] 13.01 Xe2_HPM
[15:36:00] [PASSED] 20.00 Xe2_LPM
[15:36:00] [PASSED] 30.00 Xe3_LPM
[15:36:00] [PASSED] 30.02 Xe3_LPM
[15:36:00] [PASSED] 35.00 Xe3p_LPM
[15:36:00] [PASSED] 35.03 Xe3p_HPM
[15:36:00] ================= [PASSED] check_media_ip ==================
[15:36:00] =================== check_platform_desc ===================
[15:36:00] [PASSED] 0x9A60 (TIGERLAKE)
[15:36:00] [PASSED] 0x9A68 (TIGERLAKE)
[15:36:00] [PASSED] 0x9A70 (TIGERLAKE)
[15:36:00] [PASSED] 0x9A40 (TIGERLAKE)
[15:36:00] [PASSED] 0x9A49 (TIGERLAKE)
[15:36:00] [PASSED] 0x9A59 (TIGERLAKE)
[15:36:00] [PASSED] 0x9A78 (TIGERLAKE)
[15:36:00] [PASSED] 0x9AC0 (TIGERLAKE)
[15:36:00] [PASSED] 0x9AC9 (TIGERLAKE)
[15:36:00] [PASSED] 0x9AD9 (TIGERLAKE)
[15:36:00] [PASSED] 0x9AF8 (TIGERLAKE)
[15:36:00] [PASSED] 0x4C80 (ROCKETLAKE)
[15:36:00] [PASSED] 0x4C8A (ROCKETLAKE)
[15:36:00] [PASSED] 0x4C8B (ROCKETLAKE)
[15:36:00] [PASSED] 0x4C8C (ROCKETLAKE)
[15:36:00] [PASSED] 0x4C90 (ROCKETLAKE)
[15:36:00] [PASSED] 0x4C9A (ROCKETLAKE)
[15:36:00] [PASSED] 0x4680 (ALDERLAKE_S)
[15:36:00] [PASSED] 0x4682 (ALDERLAKE_S)
[15:36:00] [PASSED] 0x4688 (ALDERLAKE_S)
[15:36:00] [PASSED] 0x468A (ALDERLAKE_S)
[15:36:00] [PASSED] 0x468B (ALDERLAKE_S)
[15:36:00] [PASSED] 0x4690 (ALDERLAKE_S)
[15:36:00] [PASSED] 0x4692 (ALDERLAKE_S)
[15:36:00] [PASSED] 0x4693 (ALDERLAKE_S)
[15:36:00] [PASSED] 0x46A0 (ALDERLAKE_P)
[15:36:00] [PASSED] 0x46A1 (ALDERLAKE_P)
[15:36:00] [PASSED] 0x46A2 (ALDERLAKE_P)
[15:36:00] [PASSED] 0x46A3 (ALDERLAKE_P)
[15:36:00] [PASSED] 0x46A6 (ALDERLAKE_P)
[15:36:00] [PASSED] 0x46A8 (ALDERLAKE_P)
[15:36:00] [PASSED] 0x46AA (ALDERLAKE_P)
[15:36:00] [PASSED] 0x462A (ALDERLAKE_P)
[15:36:00] [PASSED] 0x4626 (ALDERLAKE_P)
[15:36:00] [PASSED] 0x4628 (ALDERLAKE_P)
[15:36:00] [PASSED] 0x46B0 (ALDERLAKE_P)
[15:36:00] [PASSED] 0x46B1 (ALDERLAKE_P)
[15:36:00] [PASSED] 0x46B2 (ALDERLAKE_P)
[15:36:00] [PASSED] 0x46B3 (ALDERLAKE_P)
[15:36:00] [PASSED] 0x46C0 (ALDERLAKE_P)
[15:36:00] [PASSED] 0x46C1 (ALDERLAKE_P)
[15:36:00] [PASSED] 0x46C2 (ALDERLAKE_P)
[15:36:00] [PASSED] 0x46C3 (ALDERLAKE_P)
[15:36:00] [PASSED] 0x46D0 (ALDERLAKE_N)
[15:36:00] [PASSED] 0x46D1 (ALDERLAKE_N)
[15:36:00] [PASSED] 0x46D2 (ALDERLAKE_N)
[15:36:00] [PASSED] 0x46D3 (ALDERLAKE_N)
[15:36:00] [PASSED] 0x46D4 (ALDERLAKE_N)
[15:36:00] [PASSED] 0xA721 (ALDERLAKE_P)
[15:36:00] [PASSED] 0xA7A1 (ALDERLAKE_P)
[15:36:00] [PASSED] 0xA7A9 (ALDERLAKE_P)
[15:36:00] [PASSED] 0xA7AC (ALDERLAKE_P)
[15:36:00] [PASSED] 0xA7AD (ALDERLAKE_P)
[15:36:00] [PASSED] 0xA720 (ALDERLAKE_P)
[15:36:00] [PASSED] 0xA7A0 (ALDERLAKE_P)
[15:36:00] [PASSED] 0xA7A8 (ALDERLAKE_P)
[15:36:00] [PASSED] 0xA7AA (ALDERLAKE_P)
[15:36:00] [PASSED] 0xA7AB (ALDERLAKE_P)
[15:36:00] [PASSED] 0xA780 (ALDERLAKE_S)
[15:36:00] [PASSED] 0xA781 (ALDERLAKE_S)
[15:36:00] [PASSED] 0xA782 (ALDERLAKE_S)
[15:36:00] [PASSED] 0xA783 (ALDERLAKE_S)
[15:36:00] [PASSED] 0xA788 (ALDERLAKE_S)
[15:36:00] [PASSED] 0xA789 (ALDERLAKE_S)
[15:36:00] [PASSED] 0xA78A (ALDERLAKE_S)
[15:36:00] [PASSED] 0xA78B (ALDERLAKE_S)
[15:36:00] [PASSED] 0x4905 (DG1)
[15:36:00] [PASSED] 0x4906 (DG1)
[15:36:00] [PASSED] 0x4907 (DG1)
[15:36:00] [PASSED] 0x4908 (DG1)
[15:36:00] [PASSED] 0x4909 (DG1)
[15:36:00] [PASSED] 0x56C0 (DG2)
[15:36:00] [PASSED] 0x56C2 (DG2)
[15:36:00] [PASSED] 0x56C1 (DG2)
[15:36:00] [PASSED] 0x7D51 (METEORLAKE)
[15:36:00] [PASSED] 0x7DD1 (METEORLAKE)
[15:36:00] [PASSED] 0x7D41 (METEORLAKE)
[15:36:00] [PASSED] 0x7D67 (METEORLAKE)
[15:36:00] [PASSED] 0xB640 (METEORLAKE)
[15:36:00] [PASSED] 0x56A0 (DG2)
[15:36:00] [PASSED] 0x56A1 (DG2)
[15:36:00] [PASSED] 0x56A2 (DG2)
[15:36:00] [PASSED] 0x56BE (DG2)
[15:36:00] [PASSED] 0x56BF (DG2)
[15:36:00] [PASSED] 0x5690 (DG2)
[15:36:00] [PASSED] 0x5691 (DG2)
[15:36:00] [PASSED] 0x5692 (DG2)
[15:36:00] [PASSED] 0x56A5 (DG2)
[15:36:00] [PASSED] 0x56A6 (DG2)
[15:36:00] [PASSED] 0x56B0 (DG2)
[15:36:00] [PASSED] 0x56B1 (DG2)
[15:36:00] [PASSED] 0x56BA (DG2)
[15:36:00] [PASSED] 0x56BB (DG2)
[15:36:00] [PASSED] 0x56BC (DG2)
[15:36:00] [PASSED] 0x56BD (DG2)
[15:36:00] [PASSED] 0x5693 (DG2)
[15:36:00] [PASSED] 0x5694 (DG2)
[15:36:00] [PASSED] 0x5695 (DG2)
[15:36:00] [PASSED] 0x56A3 (DG2)
[15:36:00] [PASSED] 0x56A4 (DG2)
[15:36:00] [PASSED] 0x56B2 (DG2)
[15:36:00] [PASSED] 0x56B3 (DG2)
[15:36:00] [PASSED] 0x5696 (DG2)
[15:36:00] [PASSED] 0x5697 (DG2)
[15:36:00] [PASSED] 0xB69 (PVC)
[15:36:00] [PASSED] 0xB6E (PVC)
[15:36:00] [PASSED] 0xBD4 (PVC)
[15:36:00] [PASSED] 0xBD5 (PVC)
[15:36:00] [PASSED] 0xBD6 (PVC)
[15:36:00] [PASSED] 0xBD7 (PVC)
[15:36:00] [PASSED] 0xBD8 (PVC)
[15:36:00] [PASSED] 0xBD9 (PVC)
[15:36:00] [PASSED] 0xBDA (PVC)
[15:36:00] [PASSED] 0xBDB (PVC)
[15:36:00] [PASSED] 0xBE0 (PVC)
[15:36:00] [PASSED] 0xBE1 (PVC)
[15:36:00] [PASSED] 0xBE5 (PVC)
[15:36:00] [PASSED] 0x7D40 (METEORLAKE)
[15:36:00] [PASSED] 0x7D45 (METEORLAKE)
[15:36:00] [PASSED] 0x7D55 (METEORLAKE)
[15:36:00] [PASSED] 0x7D60 (METEORLAKE)
[15:36:00] [PASSED] 0x7DD5 (METEORLAKE)
[15:36:00] [PASSED] 0x6420 (LUNARLAKE)
[15:36:00] [PASSED] 0x64A0 (LUNARLAKE)
[15:36:00] [PASSED] 0x64B0 (LUNARLAKE)
[15:36:00] [PASSED] 0xE202 (BATTLEMAGE)
[15:36:00] [PASSED] 0xE209 (BATTLEMAGE)
[15:36:00] [PASSED] 0xE20B (BATTLEMAGE)
[15:36:00] [PASSED] 0xE20C (BATTLEMAGE)
[15:36:00] [PASSED] 0xE20D (BATTLEMAGE)
[15:36:00] [PASSED] 0xE210 (BATTLEMAGE)
[15:36:00] [PASSED] 0xE211 (BATTLEMAGE)
[15:36:00] [PASSED] 0xE212 (BATTLEMAGE)
[15:36:00] [PASSED] 0xE216 (BATTLEMAGE)
[15:36:00] [PASSED] 0xE220 (BATTLEMAGE)
[15:36:00] [PASSED] 0xE221 (BATTLEMAGE)
[15:36:00] [PASSED] 0xE222 (BATTLEMAGE)
[15:36:00] [PASSED] 0xE223 (BATTLEMAGE)
[15:36:00] [PASSED] 0xB080 (PANTHERLAKE)
[15:36:00] [PASSED] 0xB081 (PANTHERLAKE)
[15:36:00] [PASSED] 0xB082 (PANTHERLAKE)
[15:36:00] [PASSED] 0xB083 (PANTHERLAKE)
[15:36:00] [PASSED] 0xB084 (PANTHERLAKE)
[15:36:00] [PASSED] 0xB085 (PANTHERLAKE)
[15:36:00] [PASSED] 0xB086 (PANTHERLAKE)
[15:36:00] [PASSED] 0xB087 (PANTHERLAKE)
[15:36:00] [PASSED] 0xB08F (PANTHERLAKE)
[15:36:00] [PASSED] 0xB090 (PANTHERLAKE)
[15:36:00] [PASSED] 0xB0A0 (PANTHERLAKE)
[15:36:00] [PASSED] 0xB0A1 (PANTHERLAKE)
[15:36:00] [PASSED] 0xB0B0 (PANTHERLAKE)
[15:36:00] [PASSED] 0xFD80 (PANTHERLAKE)
[15:36:00] [PASSED] 0xFD81 (PANTHERLAKE)
[15:36:00] [PASSED] 0xD740 (NOVALAKE_S)
[15:36:00] [PASSED] 0xD741 (NOVALAKE_S)
[15:36:00] [PASSED] 0xD742 (NOVALAKE_S)
[15:36:00] [PASSED] 0xD743 (NOVALAKE_S)
[15:36:00] [PASSED] 0xD745 (NOVALAKE_S)
[15:36:00] [PASSED] 0xD74A (NOVALAKE_S)
[15:36:00] [PASSED] 0xD74B (NOVALAKE_S)
[15:36:00] [PASSED] 0x674C (CRESCENTISLAND)
[15:36:00] [PASSED] 0x674D (CRESCENTISLAND)
[15:36:00] [PASSED] 0x674E (CRESCENTISLAND)
[15:36:00] [PASSED] 0x674F (CRESCENTISLAND)
[15:36:00] [PASSED] 0x6750 (CRESCENTISLAND)
[15:36:00] [PASSED] 0x6751 (CRESCENTISLAND)
[15:36:00] [PASSED] 0x6752 (CRESCENTISLAND)
[15:36:00] [PASSED] 0xD750 (NOVALAKE_P)
[15:36:00] [PASSED] 0xD751 (NOVALAKE_P)
[15:36:00] [PASSED] 0xD752 (NOVALAKE_P)
[15:36:00] [PASSED] 0xD753 (NOVALAKE_P)
[15:36:00] [PASSED] 0xD754 (NOVALAKE_P)
[15:36:00] [PASSED] 0xD755 (NOVALAKE_P)
[15:36:00] [PASSED] 0xD756 (NOVALAKE_P)
[15:36:00] [PASSED] 0xD757 (NOVALAKE_P)
[15:36:00] [PASSED] 0xD75F (NOVALAKE_P)
[15:36:00] =============== [PASSED] check_platform_desc ===============
[15:36:00] ===================== [PASSED] xe_pci ======================
[15:36:00] ============= xe_rtp_tables_test (5 subtests) ==============
[15:36:00] ================== xe_rtp_table_gt_test ===================
[15:36:00] [PASSED] gt_was/14011060649
[15:36:00] [PASSED] gt_was/14011059788
[15:36:00] [PASSED] gt_was/14015795083
[15:36:00] [PASSED] gt_was/16021867713
[15:36:00] [PASSED] gt_was/14019449301
[15:36:00] [PASSED] gt_was/16028005424
[15:36:00] [PASSED] gt_was/14026578760
[15:36:00] [PASSED] gt_was/1409420604
[15:36:00] [PASSED] gt_was/1408615072
[15:36:00] [PASSED] gt_was/22010523718
[15:36:00] [PASSED] gt_was/14011006942
[15:36:00] [PASSED] gt_was/14014830051
[15:36:00] [PASSED] gt_was/18018781329
[15:36:00] [PASSED] gt_was/1509235366
[15:36:00] [PASSED] gt_was/18018781329
[15:36:00] [PASSED] gt_was/16016694945
[15:36:00] [PASSED] gt_was/14018575942
[15:36:00] [PASSED] gt_was/22016670082
[15:36:00] [PASSED] gt_was/22016670082
[15:36:00] [PASSED] gt_was/14017421178
[15:36:00] [PASSED] gt_was/16025250150
[15:36:00] [PASSED] gt_was/14021871409
[15:36:00] [PASSED] gt_was/16021865536
[15:36:00] [PASSED] gt_was/14021486841
[15:36:00] [PASSED] gt_was/14025160223
[15:36:00] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[15:36:00] [PASSED] gt_was/14025635424
[15:36:00] [PASSED] gt_was/16028005424
[15:36:00] ============== [PASSED] xe_rtp_table_gt_test ===============
[15:36:00] ================== xe_rtp_table_gt_test ===================
[15:36:00] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[15:36:00] [PASSED] gt_tunings/Tuning: 32B Access Enable
[15:36:00] [PASSED] gt_tunings/Tuning: L3 cache
[15:36:00] [PASSED] gt_tunings/Tuning: L3 cache - media
[15:36:00] [PASSED] gt_tunings/Tuning: Compression Overfetch
[15:36:00] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[15:36:00] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[15:36:00] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[15:36:00] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[15:36:00] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[15:36:00] [PASSED] gt_tunings/Tuning: Stateless compression control
[15:36:00] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[15:36:00] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[15:36:00] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[15:36:00] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[15:36:00] [PASSED] gt_tunings/Tuning: Force All Non-Compressible Memory Reads to be 256B Overfetches
[15:36:00] ============== [PASSED] xe_rtp_table_gt_test ===============
[15:36:00] ================== xe_rtp_table_oob_test ==================
[15:36:00] [PASSED] oob_was/1607983814
[15:36:00] [PASSED] oob_was/16010904313
[15:36:00] [PASSED] oob_was/18022495364
[15:36:00] [PASSED] oob_was/22012773006
[15:36:00] [PASSED] oob_was/14014475959
[15:36:00] [PASSED] oob_was/22011391025
[15:36:00] [PASSED] oob_was/22012727170
[15:36:00] [PASSED] oob_was/22012727685
[15:36:00] [PASSED] oob_was/22016596838
[15:36:00] [PASSED] oob_was/18020744125
[15:36:00] [PASSED] oob_was/1409600907
[15:36:00] [PASSED] oob_was/22014953428
[15:36:00] [PASSED] oob_was/16017236439
[15:36:00] [PASSED] oob_was/14019821291
[15:36:00] [PASSED] oob_was/14015076503
[15:36:00] [PASSED] oob_was/22016122933
[15:36:00] [PASSED] oob_was/14018913170
[15:36:00] [PASSED] oob_was/14018094691
[15:36:00] [PASSED] oob_was/18024947630
[15:36:00] [PASSED] oob_was/16022287689
[15:36:00] [PASSED] oob_was/13011645652
[15:36:00] [PASSED] oob_was/14022293748
[15:36:00] [PASSED] oob_was/22019794406
[15:36:00] [PASSED] oob_was/22019338487
[15:36:00] [PASSED] oob_was/16023588340
[15:36:00] [PASSED] oob_was/14019789679
[15:36:00] [PASSED] oob_was/14022866841
[15:36:00] [PASSED] oob_was/16021333562
[15:36:00] [PASSED] oob_was/14016712196
[15:36:00] [PASSED] oob_was/14015568240
[15:36:00] [PASSED] oob_was/18013179988
[15:36:00] [PASSED] oob_was/1508761755
[15:36:00] [PASSED] oob_was/16023105232
[15:36:00] [PASSED] oob_was/16026508708
[15:36:00] [PASSED] oob_was/14020001231
[15:36:00] [PASSED] oob_was/16023683509
[15:36:00] [PASSED] oob_was/14025515070
[15:36:00] [PASSED] oob_was/15015404425_disable
[15:36:00] [PASSED] oob_was/16026007364
[15:36:00] [PASSED] oob_was/14020316580
[15:36:00] [PASSED] oob_was/14025883347
[15:36:00] [PASSED] oob_was/16029380221
[15:36:00] [PASSED] oob_was/22022079272
[15:36:00] [PASSED] oob_was/16029897822
[15:36:00] [PASSED] oob_was/14026539277
[15:36:00] [PASSED] oob_was/14027054324
[15:36:00] [PASSED] oob_was/14025941587
[15:36:00] [PASSED] oob_was/16030224309
[15:36:00] ============== [PASSED] xe_rtp_table_oob_test ==============
[15:36:00] ================ xe_rtp_table_dev_oob_test ================
[15:36:00] [PASSED] device_oob_was/22010954014
[15:36:00] [PASSED] device_oob_was/15015404425
[15:36:00] [PASSED] device_oob_was/22019338487_display
[15:36:00] [PASSED] device_oob_was/14022085890
[15:36:00] [PASSED] device_oob_was/14026633728
[15:36:00] [PASSED] device_oob_was/14026746987
[15:36:00] [PASSED] device_oob_was/14026779378
[15:36:00] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[15:36:00] ========== xe_rtp_table_missing_upper_bound_test ==========
[15:36:00] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[15:36:00] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[15:36:00] [PASSED] register_whitelist/1806527549
[15:36:00] [PASSED] register_whitelist/allow_read_ctx_timestamp
[15:36:00] [PASSED] register_whitelist/allow_read_queue_timestamp
[15:36:00] [PASSED] register_whitelist/16014440446
[15:36:00] [PASSED] register_whitelist/16017236439
[15:36:00] [PASSED] register_whitelist/16020183090
[15:36:00] [PASSED] register_whitelist/14024997852
[15:36:00] [PASSED] register_whitelist/14024997852
[15:36:00] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[15:36:00] =============== [PASSED] xe_rtp_tables_test ================
[15:36:00] =================== xe_rtp (3 subtests) ====================
[15:36:00] =================== xe_rtp_rules_tests ====================
[15:36:00] [PASSED] no
[15:36:00] [PASSED] yes
[15:36:00] [PASSED] no-and-no
[15:36:00] [PASSED] no-and-yes
[15:36:00] [PASSED] yes-and-no
[15:36:00] [PASSED] yes-and-yes
[15:36:00] [PASSED] no-or-no
[15:36:00] [PASSED] no-or-yes
[15:36:00] [PASSED] yes-or-no
[15:36:00] [PASSED] yes-or-yes
[15:36:00] [PASSED] no-yes-or-yes-no
[15:36:00] [PASSED] no-yes-or-yes-yes
[15:36:00] [PASSED] yes-yes-or-no-yes
[15:36:00] [PASSED] yes-yes-or-yes-yes
[15:36:00] [PASSED] no-no-or-yes-or-no
[15:36:00] [PASSED] or
[15:36:00] [PASSED] or-yes
[15:36:00] [PASSED] or-no
[15:36:00] [PASSED] yes-or
[15:36:00] [PASSED] no-or
[15:36:00] [PASSED] no-or-or-yes
[15:36:00] [PASSED] yes-or-or-no
[15:36:00] [PASSED] no-or-or-no
[15:36:00] [PASSED] missing-context-engine-class
[15:36:00] [PASSED] missing-context-engine-class-or-yes
[15:36:00] [PASSED] missing-context-engine-class-or-or-yes
[15:36:00] =============== [PASSED] xe_rtp_rules_tests ================
[15:36:00] =============== xe_rtp_process_to_sr_tests ================
[15:36:00] [PASSED] coalesce-same-reg
[15:36:00] [PASSED] coalesce-same-reg-literal-and-func
[15:36:00] [PASSED] no-match-no-add
[15:36:00] [PASSED] two-regs-two-entries
[15:36:00] [PASSED] clr-one-set-other
[15:36:00] [PASSED] set-field
[15:36:00] [PASSED] conflict-duplicate
[15:36:00] [PASSED] conflict-not-disjoint
[15:36:00] [PASSED] conflict-not-disjoint-literal-and-func
[15:36:00] [PASSED] conflict-reg-type
[15:36:00] [PASSED] bad-mcr-reg-forced-to-regular
[15:36:00] [PASSED] bad-regular-reg-forced-to-mcr
[15:36:00] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[15:36:00] ================== xe_rtp_process_tests ===================
[15:36:00] [PASSED] active1
[15:36:00] [PASSED] active2
[15:36:00] [PASSED] active-inactive
[15:36:00] [PASSED] inactive-active
[15:36:00] [PASSED] inactive-active-inactive
[15:36:00] [PASSED] inactive-inactive-inactive
[15:36:00] ============== [PASSED] xe_rtp_process_tests ===============
[15:36:00] ===================== [PASSED] xe_rtp ======================
[15:36:00] ==================== xe_wa (1 subtest) =====================
[15:36:00] ======================== xe_wa_gt =========================
[15:36:00] [PASSED] TIGERLAKE B0
[15:36:00] [PASSED] DG1 A0
[15:36:00] [PASSED] DG1 B0
[15:36:00] [PASSED] ALDERLAKE_S A0
[15:36:00] [PASSED] ALDERLAKE_S B0
[15:36:00] [PASSED] ALDERLAKE_S C0
[15:36:00] [PASSED] ALDERLAKE_S D0
[15:36:00] [PASSED] ALDERLAKE_P A0
[15:36:00] [PASSED] ALDERLAKE_P B0
[15:36:00] [PASSED] ALDERLAKE_P C0
[15:36:00] [PASSED] ALDERLAKE_S RPLS D0
[15:36:00] [PASSED] ALDERLAKE_P RPLU E0
[15:36:00] [PASSED] DG2 G10 C0
[15:36:00] [PASSED] DG2 G11 B1
[15:36:00] [PASSED] DG2 G12 A1
[15:36:00] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[15:36:00] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[15:36:00] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[15:36:00] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[15:36:00] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[15:36:00] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[15:36:00] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[15:36:00] ==================== [PASSED] xe_wa_gt =====================
[15:36:00] ====================== [PASSED] xe_wa ======================
[15:36:00] ============================================================
[15:36:00] Testing complete. Ran 839 tests: passed: 810, skipped: 29
[15:36:00] Elapsed time: 41.755s total, 1.836s configuring, 39.153s building, 0.729s running
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[15:36:00] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[15:36:02] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[15:36:27] Starting KUnit Kernel (1/1)...
[15:36:27] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[15:36:27] ============ drm_test_pick_cmdline (2 subtests) ============
[15:36:27] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[15:36:27] =============== drm_test_pick_cmdline_named ===============
[15:36:27] [PASSED] NTSC
[15:36:27] [PASSED] NTSC-J
[15:36:27] [PASSED] PAL
[15:36:27] [PASSED] PAL-M
[15:36:27] =========== [PASSED] drm_test_pick_cmdline_named ===========
[15:36:27] ============== [PASSED] drm_test_pick_cmdline ==============
[15:36:27] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[15:36:27] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[15:36:27] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[15:36:27] =========== drm_validate_clone_mode (2 subtests) ===========
[15:36:27] ============== drm_test_check_in_clone_mode ===============
[15:36:27] [PASSED] in_clone_mode
[15:36:27] [PASSED] not_in_clone_mode
[15:36:27] ========== [PASSED] drm_test_check_in_clone_mode ===========
[15:36:27] =============== drm_test_check_valid_clones ===============
[15:36:27] [PASSED] not_in_clone_mode
[15:36:27] [PASSED] valid_clone
[15:36:27] [PASSED] invalid_clone
[15:36:27] =========== [PASSED] drm_test_check_valid_clones ===========
[15:36:27] ============= [PASSED] drm_validate_clone_mode =============
[15:36:27] ============= drm_validate_modeset (1 subtest) =============
[15:36:27] [PASSED] drm_test_check_connector_changed_modeset
[15:36:27] ============== [PASSED] drm_validate_modeset ===============
[15:36:27] ====== drm_test_bridge_get_current_state (1 subtest) =======
[15:36:27] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[15:36:27] ======== [PASSED] drm_test_bridge_get_current_state ========
[15:36:27] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[15:36:27] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[15:36:27] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[15:36:27] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[15:36:27] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[15:36:27] ============== drm_bridge_alloc (2 subtests) ===============
[15:36:27] [PASSED] drm_test_drm_bridge_alloc_basic
[15:36:27] [PASSED] drm_test_drm_bridge_alloc_get_put
[15:36:27] ================ [PASSED] drm_bridge_alloc =================
[15:36:27] ============= drm_bridge_bus_fmt (5 subtests) ==============
[15:36:27] [PASSED] drm_test_bridge_rgb_yuv_rgb
[15:36:27] [PASSED] drm_test_bridge_must_convert_to_yuv444
[15:36:27] [PASSED] drm_test_bridge_hdmi_auto_rgb
[15:36:27] [PASSED] drm_test_bridge_auto_first
[15:36:27] [PASSED] drm_test_bridge_rgb_yuv_no_path
[15:36:27] =============== [PASSED] drm_bridge_bus_fmt ================
[15:36:27] ============= drm_cmdline_parser (40 subtests) =============
[15:36:27] [PASSED] drm_test_cmdline_force_d_only
[15:36:27] [PASSED] drm_test_cmdline_force_D_only_dvi
[15:36:27] [PASSED] drm_test_cmdline_force_D_only_hdmi
[15:36:27] [PASSED] drm_test_cmdline_force_D_only_not_digital
[15:36:27] [PASSED] drm_test_cmdline_force_e_only
[15:36:27] [PASSED] drm_test_cmdline_res
[15:36:27] [PASSED] drm_test_cmdline_res_vesa
[15:36:27] [PASSED] drm_test_cmdline_res_vesa_rblank
[15:36:27] [PASSED] drm_test_cmdline_res_rblank
[15:36:27] [PASSED] drm_test_cmdline_res_bpp
[15:36:27] [PASSED] drm_test_cmdline_res_refresh
[15:36:27] [PASSED] drm_test_cmdline_res_bpp_refresh
[15:36:27] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[15:36:27] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[15:36:27] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[15:36:27] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[15:36:27] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[15:36:27] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[15:36:27] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[15:36:27] [PASSED] drm_test_cmdline_res_margins_force_on
[15:36:27] [PASSED] drm_test_cmdline_res_vesa_margins
[15:36:27] [PASSED] drm_test_cmdline_name
[15:36:27] [PASSED] drm_test_cmdline_name_bpp
[15:36:27] [PASSED] drm_test_cmdline_name_option
[15:36:27] [PASSED] drm_test_cmdline_name_bpp_option
[15:36:27] [PASSED] drm_test_cmdline_rotate_0
[15:36:27] [PASSED] drm_test_cmdline_rotate_90
[15:36:27] [PASSED] drm_test_cmdline_rotate_180
[15:36:27] [PASSED] drm_test_cmdline_rotate_270
[15:36:27] [PASSED] drm_test_cmdline_hmirror
[15:36:27] [PASSED] drm_test_cmdline_vmirror
[15:36:27] [PASSED] drm_test_cmdline_margin_options
[15:36:27] [PASSED] drm_test_cmdline_multiple_options
[15:36:27] [PASSED] drm_test_cmdline_bpp_extra_and_option
[15:36:27] [PASSED] drm_test_cmdline_extra_and_option
[15:36:27] [PASSED] drm_test_cmdline_freestanding_options
[15:36:27] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[15:36:27] [PASSED] drm_test_cmdline_panel_orientation
[15:36:27] ================ drm_test_cmdline_invalid =================
[15:36:27] [PASSED] margin_only
[15:36:27] [PASSED] interlace_only
[15:36:27] [PASSED] res_missing_x
[15:36:27] [PASSED] res_missing_y
[15:36:27] [PASSED] res_bad_y
[15:36:27] [PASSED] res_missing_y_bpp
[15:36:27] [PASSED] res_bad_bpp
[15:36:27] [PASSED] res_bad_refresh
[15:36:27] [PASSED] res_bpp_refresh_force_on_off
[15:36:27] [PASSED] res_invalid_mode
[15:36:27] [PASSED] res_bpp_wrong_place_mode
[15:36:27] [PASSED] name_bpp_refresh
[15:36:27] [PASSED] name_refresh
[15:36:27] [PASSED] name_refresh_wrong_mode
[15:36:27] [PASSED] name_refresh_invalid_mode
[15:36:27] [PASSED] rotate_multiple
[15:36:27] [PASSED] rotate_invalid_val
[15:36:27] [PASSED] rotate_truncated
[15:36:27] [PASSED] invalid_option
[15:36:27] [PASSED] invalid_tv_option
[15:36:27] [PASSED] truncated_tv_option
[15:36:27] ============ [PASSED] drm_test_cmdline_invalid =============
[15:36:27] =============== drm_test_cmdline_tv_options ===============
[15:36:27] [PASSED] NTSC
[15:36:27] [PASSED] NTSC_443
[15:36:27] [PASSED] NTSC_J
[15:36:27] [PASSED] PAL
[15:36:27] [PASSED] PAL_M
[15:36:27] [PASSED] PAL_N
[15:36:27] [PASSED] SECAM
[15:36:27] [PASSED] MONO_525
[15:36:27] [PASSED] MONO_625
[15:36:27] =========== [PASSED] drm_test_cmdline_tv_options ===========
[15:36:27] =============== [PASSED] drm_cmdline_parser ================
[15:36:27] ========== drmm_connector_hdmi_init (20 subtests) ==========
[15:36:27] [PASSED] drm_test_connector_hdmi_init_valid
[15:36:27] [PASSED] drm_test_connector_hdmi_init_bpc_8
[15:36:27] [PASSED] drm_test_connector_hdmi_init_bpc_10
[15:36:27] [PASSED] drm_test_connector_hdmi_init_bpc_12
[15:36:27] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[15:36:27] [PASSED] drm_test_connector_hdmi_init_bpc_null
[15:36:27] [PASSED] drm_test_connector_hdmi_init_formats_empty
[15:36:27] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[15:36:27] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[15:36:27] [PASSED] supported_formats=0x9 yuv420_allowed=1
[15:36:27] [PASSED] supported_formats=0x9 yuv420_allowed=0
[15:36:27] [PASSED] supported_formats=0x5 yuv420_allowed=1
[15:36:27] [PASSED] supported_formats=0x5 yuv420_allowed=0
[15:36:27] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[15:36:27] [PASSED] drm_test_connector_hdmi_init_null_ddc
[15:36:27] [PASSED] drm_test_connector_hdmi_init_null_product
[15:36:27] [PASSED] drm_test_connector_hdmi_init_null_vendor
[15:36:27] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[15:36:27] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[15:36:27] [PASSED] drm_test_connector_hdmi_init_product_valid
[15:36:27] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[15:36:27] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[15:36:27] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[15:36:27] ========= drm_test_connector_hdmi_init_type_valid =========
[15:36:27] [PASSED] HDMI-A
[15:36:27] [PASSED] HDMI-B
[15:36:27] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[15:36:27] ======== drm_test_connector_hdmi_init_type_invalid ========
[15:36:27] [PASSED] Unknown
[15:36:27] [PASSED] VGA
[15:36:27] [PASSED] DVI-I
[15:36:27] [PASSED] DVI-D
[15:36:27] [PASSED] DVI-A
[15:36:27] [PASSED] Composite
[15:36:27] [PASSED] SVIDEO
[15:36:27] [PASSED] LVDS
[15:36:27] [PASSED] Component
[15:36:27] [PASSED] DIN
[15:36:27] [PASSED] DP
[15:36:27] [PASSED] TV
[15:36:27] [PASSED] eDP
[15:36:27] [PASSED] Virtual
[15:36:27] [PASSED] DSI
[15:36:27] [PASSED] DPI
[15:36:27] [PASSED] Writeback
[15:36:27] [PASSED] SPI
[15:36:27] [PASSED] USB
[15:36:27] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[15:36:27] ============ [PASSED] drmm_connector_hdmi_init =============
[15:36:27] ============= drmm_connector_init (3 subtests) =============
[15:36:27] [PASSED] drm_test_drmm_connector_init
[15:36:27] [PASSED] drm_test_drmm_connector_init_null_ddc
[15:36:27] ========= drm_test_drmm_connector_init_type_valid =========
[15:36:27] [PASSED] Unknown
[15:36:27] [PASSED] VGA
[15:36:27] [PASSED] DVI-I
[15:36:27] [PASSED] DVI-D
[15:36:27] [PASSED] DVI-A
[15:36:27] [PASSED] Composite
[15:36:27] [PASSED] SVIDEO
[15:36:27] [PASSED] LVDS
[15:36:27] [PASSED] Component
[15:36:27] [PASSED] DIN
[15:36:27] [PASSED] DP
[15:36:27] [PASSED] HDMI-A
[15:36:27] [PASSED] HDMI-B
[15:36:27] [PASSED] TV
[15:36:27] [PASSED] eDP
[15:36:27] [PASSED] Virtual
[15:36:27] [PASSED] DSI
[15:36:27] [PASSED] DPI
[15:36:27] [PASSED] Writeback
[15:36:27] [PASSED] SPI
[15:36:27] [PASSED] USB
[15:36:27] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[15:36:27] =============== [PASSED] drmm_connector_init ===============
[15:36:27] ========= drm_connector_dynamic_init (6 subtests) ==========
[15:36:27] [PASSED] drm_test_drm_connector_dynamic_init
[15:36:27] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[15:36:27] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[15:36:27] [PASSED] drm_test_drm_connector_dynamic_init_properties
[15:36:27] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[15:36:27] [PASSED] Unknown
[15:36:27] [PASSED] VGA
[15:36:27] [PASSED] DVI-I
[15:36:27] [PASSED] DVI-D
[15:36:27] [PASSED] DVI-A
[15:36:27] [PASSED] Composite
[15:36:27] [PASSED] SVIDEO
[15:36:27] [PASSED] LVDS
[15:36:27] [PASSED] Component
[15:36:27] [PASSED] DIN
[15:36:27] [PASSED] DP
[15:36:27] [PASSED] HDMI-A
[15:36:27] [PASSED] HDMI-B
[15:36:27] [PASSED] TV
[15:36:27] [PASSED] eDP
[15:36:27] [PASSED] Virtual
[15:36:27] [PASSED] DSI
[15:36:27] [PASSED] DPI
[15:36:27] [PASSED] Writeback
[15:36:27] [PASSED] SPI
[15:36:27] [PASSED] USB
[15:36:27] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[15:36:27] ======== drm_test_drm_connector_dynamic_init_name =========
[15:36:27] [PASSED] Unknown
[15:36:27] [PASSED] VGA
[15:36:27] [PASSED] DVI-I
[15:36:27] [PASSED] DVI-D
[15:36:27] [PASSED] DVI-A
[15:36:27] [PASSED] Composite
[15:36:27] [PASSED] SVIDEO
[15:36:27] [PASSED] LVDS
[15:36:27] [PASSED] Component
[15:36:27] [PASSED] DIN
[15:36:27] [PASSED] DP
[15:36:27] [PASSED] HDMI-A
[15:36:27] [PASSED] HDMI-B
[15:36:27] [PASSED] TV
[15:36:27] [PASSED] eDP
[15:36:27] [PASSED] Virtual
[15:36:27] [PASSED] DSI
[15:36:27] [PASSED] DPI
[15:36:27] [PASSED] Writeback
[15:36:27] [PASSED] SPI
[15:36:27] [PASSED] USB
[15:36:27] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[15:36:27] =========== [PASSED] drm_connector_dynamic_init ============
[15:36:27] ==== drm_connector_dynamic_register_early (4 subtests) =====
[15:36:27] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[15:36:27] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[15:36:27] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[15:36:27] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[15:36:27] ====== [PASSED] drm_connector_dynamic_register_early =======
[15:36:27] ======= drm_connector_dynamic_register (7 subtests) ========
[15:36:27] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[15:36:27] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[15:36:27] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[15:36:27] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[15:36:27] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[15:36:27] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[15:36:27] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[15:36:27] ========= [PASSED] drm_connector_dynamic_register ==========
[15:36:27] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[15:36:27] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[15:36:27] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[15:36:27] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[15:36:27] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[15:36:27] ========== drm_test_get_tv_mode_from_name_valid ===========
[15:36:27] [PASSED] NTSC
[15:36:27] [PASSED] NTSC-443
[15:36:27] [PASSED] NTSC-J
[15:36:27] [PASSED] PAL
[15:36:27] [PASSED] PAL-M
[15:36:27] [PASSED] PAL-N
[15:36:27] [PASSED] SECAM
[15:36:27] [PASSED] Mono
[15:36:27] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[15:36:27] [PASSED] drm_test_get_tv_mode_from_name_truncated
[15:36:27] ============ [PASSED] drm_get_tv_mode_from_name ============
[15:36:27] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[15:36:27] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[15:36:27] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[15:36:27] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[15:36:27] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[15:36:27] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[15:36:27] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[15:36:27] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[15:36:27] [PASSED] VIC 96
[15:36:27] [PASSED] VIC 97
[15:36:27] [PASSED] VIC 101
[15:36:27] [PASSED] VIC 102
[15:36:27] [PASSED] VIC 106
[15:36:27] [PASSED] VIC 107
[15:36:27] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[15:36:27] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[15:36:27] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[15:36:27] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[15:36:27] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[15:36:27] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[15:36:27] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[15:36:27] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[15:36:27] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[15:36:27] [PASSED] Automatic
[15:36:27] [PASSED] Full
[15:36:27] [PASSED] Limited 16:235
[15:36:27] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[15:36:27] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[15:36:27] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[15:36:27] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[15:36:27] === drm_test_drm_hdmi_connector_get_output_format_name ====
[15:36:27] [PASSED] RGB
[15:36:27] [PASSED] YUV 4:2:0
[15:36:27] [PASSED] YUV 4:2:2
[15:36:27] [PASSED] YUV 4:4:4
[15:36:27] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[15:36:27] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[15:36:27] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[15:36:27] ============= drm_damage_helper (21 subtests) ==============
[15:36:27] [PASSED] drm_test_damage_iter_no_damage
[15:36:27] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[15:36:27] [PASSED] drm_test_damage_iter_no_damage_src_moved
[15:36:27] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[15:36:27] [PASSED] drm_test_damage_iter_no_damage_not_visible
[15:36:27] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[15:36:27] [PASSED] drm_test_damage_iter_no_damage_no_fb
[15:36:27] [PASSED] drm_test_damage_iter_simple_damage
[15:36:27] [PASSED] drm_test_damage_iter_single_damage
[15:36:27] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[15:36:27] [PASSED] drm_test_damage_iter_single_damage_outside_src
[15:36:27] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[15:36:27] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[15:36:27] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[15:36:27] [PASSED] drm_test_damage_iter_single_damage_src_moved
[15:36:27] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[15:36:27] [PASSED] drm_test_damage_iter_damage
[15:36:27] [PASSED] drm_test_damage_iter_damage_one_intersect
[15:36:27] [PASSED] drm_test_damage_iter_damage_one_outside
[15:36:27] [PASSED] drm_test_damage_iter_damage_src_moved
[15:36:27] [PASSED] drm_test_damage_iter_damage_not_visible
[15:36:27] ================ [PASSED] drm_damage_helper ================
[15:36:27] ============== drm_dp_mst_helper (3 subtests) ==============
[15:36:27] ============== drm_test_dp_mst_calc_pbn_mode ==============
[15:36:27] [PASSED] Clock 154000 BPP 30 DSC disabled
[15:36:27] [PASSED] Clock 234000 BPP 30 DSC disabled
[15:36:27] [PASSED] Clock 297000 BPP 24 DSC disabled
[15:36:27] [PASSED] Clock 332880 BPP 24 DSC enabled
[15:36:27] [PASSED] Clock 324540 BPP 24 DSC enabled
[15:36:27] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[15:36:27] ============== drm_test_dp_mst_calc_pbn_div ===============
[15:36:27] [PASSED] Link rate 2000000 lane count 4
[15:36:27] [PASSED] Link rate 2000000 lane count 2
[15:36:27] [PASSED] Link rate 2000000 lane count 1
[15:36:27] [PASSED] Link rate 1350000 lane count 4
[15:36:27] [PASSED] Link rate 1350000 lane count 2
[15:36:27] [PASSED] Link rate 1350000 lane count 1
[15:36:27] [PASSED] Link rate 1000000 lane count 4
[15:36:27] [PASSED] Link rate 1000000 lane count 2
[15:36:27] [PASSED] Link rate 1000000 lane count 1
[15:36:27] [PASSED] Link rate 810000 lane count 4
[15:36:27] [PASSED] Link rate 810000 lane count 2
[15:36:27] [PASSED] Link rate 810000 lane count 1
[15:36:27] [PASSED] Link rate 540000 lane count 4
[15:36:27] [PASSED] Link rate 540000 lane count 2
[15:36:27] [PASSED] Link rate 540000 lane count 1
[15:36:27] [PASSED] Link rate 270000 lane count 4
[15:36:27] [PASSED] Link rate 270000 lane count 2
[15:36:27] [PASSED] Link rate 270000 lane count 1
[15:36:27] [PASSED] Link rate 162000 lane count 4
[15:36:27] [PASSED] Link rate 162000 lane count 2
[15:36:27] [PASSED] Link rate 162000 lane count 1
[15:36:27] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[15:36:27] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[15:36:27] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[15:36:27] [PASSED] DP_POWER_UP_PHY with port number
[15:36:27] [PASSED] DP_POWER_DOWN_PHY with port number
[15:36:27] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[15:36:27] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[15:36:27] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[15:36:27] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[15:36:27] [PASSED] DP_QUERY_PAYLOAD with port number
[15:36:27] [PASSED] DP_QUERY_PAYLOAD with VCPI
[15:36:27] [PASSED] DP_REMOTE_DPCD_READ with port number
[15:36:27] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[15:36:27] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[15:36:27] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[15:36:27] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[15:36:27] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[15:36:27] [PASSED] DP_REMOTE_I2C_READ with port number
[15:36:27] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[15:36:27] [PASSED] DP_REMOTE_I2C_READ with transactions array
[15:36:27] [PASSED] DP_REMOTE_I2C_WRITE with port number
[15:36:27] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[15:36:27] [PASSED] DP_REMOTE_I2C_WRITE with data array
[15:36:27] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[15:36:27] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[15:36:27] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[15:36:27] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[15:36:27] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[15:36:27] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[15:36:27] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[15:36:27] ================ [PASSED] drm_dp_mst_helper ================
[15:36:27] ================== drm_exec (7 subtests) ===================
[15:36:27] [PASSED] sanitycheck
[15:36:27] [PASSED] test_lock
[15:36:27] [PASSED] test_lock_unlock
[15:36:27] [PASSED] test_duplicates
[15:36:27] [PASSED] test_prepare
[15:36:27] [PASSED] test_prepare_array
[15:36:27] [PASSED] test_multiple_loops
[15:36:27] ==================== [PASSED] drm_exec =====================
[15:36:27] =========== drm_format_helper_test (17 subtests) ===========
[15:36:27] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[15:36:27] [PASSED] single_pixel_source_buffer
[15:36:27] [PASSED] single_pixel_clip_rectangle
[15:36:27] [PASSED] well_known_colors
[15:36:27] [PASSED] destination_pitch
[15:36:27] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[15:36:27] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[15:36:27] [PASSED] single_pixel_source_buffer
[15:36:27] [PASSED] single_pixel_clip_rectangle
[15:36:27] [PASSED] well_known_colors
[15:36:27] [PASSED] destination_pitch
[15:36:27] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[15:36:27] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[15:36:27] [PASSED] single_pixel_source_buffer
[15:36:27] [PASSED] single_pixel_clip_rectangle
[15:36:27] [PASSED] well_known_colors
[15:36:27] [PASSED] destination_pitch
[15:36:27] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[15:36:27] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[15:36:27] [PASSED] single_pixel_source_buffer
[15:36:27] [PASSED] single_pixel_clip_rectangle
[15:36:27] [PASSED] well_known_colors
[15:36:27] [PASSED] destination_pitch
[15:36:27] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[15:36:27] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[15:36:27] [PASSED] single_pixel_source_buffer
[15:36:27] [PASSED] single_pixel_clip_rectangle
[15:36:27] [PASSED] well_known_colors
[15:36:27] [PASSED] destination_pitch
[15:36:27] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[15:36:27] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[15:36:27] [PASSED] single_pixel_source_buffer
[15:36:27] [PASSED] single_pixel_clip_rectangle
[15:36:27] [PASSED] well_known_colors
[15:36:27] [PASSED] destination_pitch
[15:36:27] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[15:36:27] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[15:36:27] [PASSED] single_pixel_source_buffer
[15:36:27] [PASSED] single_pixel_clip_rectangle
[15:36:27] [PASSED] well_known_colors
[15:36:27] [PASSED] destination_pitch
[15:36:27] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[15:36:27] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[15:36:27] [PASSED] single_pixel_source_buffer
[15:36:27] [PASSED] single_pixel_clip_rectangle
[15:36:27] [PASSED] well_known_colors
[15:36:27] [PASSED] destination_pitch
[15:36:27] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[15:36:27] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[15:36:27] [PASSED] single_pixel_source_buffer
[15:36:27] [PASSED] single_pixel_clip_rectangle
[15:36:27] [PASSED] well_known_colors
[15:36:27] [PASSED] destination_pitch
[15:36:27] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[15:36:27] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[15:36:27] [PASSED] single_pixel_source_buffer
[15:36:27] [PASSED] single_pixel_clip_rectangle
[15:36:27] [PASSED] well_known_colors
[15:36:27] [PASSED] destination_pitch
[15:36:27] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[15:36:27] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[15:36:27] [PASSED] single_pixel_source_buffer
[15:36:27] [PASSED] single_pixel_clip_rectangle
[15:36:27] [PASSED] well_known_colors
[15:36:27] [PASSED] destination_pitch
[15:36:27] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[15:36:27] ============== drm_test_fb_xrgb8888_to_mono ===============
[15:36:27] [PASSED] single_pixel_source_buffer
[15:36:27] [PASSED] single_pixel_clip_rectangle
[15:36:27] [PASSED] well_known_colors
[15:36:27] [PASSED] destination_pitch
[15:36:27] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[15:36:27] ==================== drm_test_fb_swab =====================
[15:36:27] [PASSED] single_pixel_source_buffer
[15:36:27] [PASSED] single_pixel_clip_rectangle
[15:36:27] [PASSED] well_known_colors
[15:36:27] [PASSED] destination_pitch
[15:36:27] ================ [PASSED] drm_test_fb_swab =================
[15:36:27] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[15:36:27] [PASSED] single_pixel_source_buffer
[15:36:27] [PASSED] single_pixel_clip_rectangle
[15:36:27] [PASSED] well_known_colors
[15:36:27] [PASSED] destination_pitch
[15:36:27] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[15:36:27] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[15:36:27] [PASSED] single_pixel_source_buffer
[15:36:27] [PASSED] single_pixel_clip_rectangle
[15:36:27] [PASSED] well_known_colors
[15:36:27] [PASSED] destination_pitch
[15:36:27] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[15:36:27] ================= drm_test_fb_clip_offset =================
[15:36:27] [PASSED] pass through
[15:36:27] [PASSED] horizontal offset
[15:36:27] [PASSED] vertical offset
[15:36:27] [PASSED] horizontal and vertical offset
[15:36:27] [PASSED] horizontal offset (custom pitch)
[15:36:27] [PASSED] vertical offset (custom pitch)
[15:36:27] [PASSED] horizontal and vertical offset (custom pitch)
[15:36:27] ============= [PASSED] drm_test_fb_clip_offset =============
[15:36:27] =================== drm_test_fb_memcpy ====================
[15:36:27] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[15:36:27] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[15:36:27] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[15:36:27] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[15:36:27] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[15:36:27] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[15:36:27] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[15:36:27] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[15:36:27] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[15:36:27] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[15:36:27] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[15:36:27] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[15:36:27] =============== [PASSED] drm_test_fb_memcpy ================
[15:36:27] ============= [PASSED] drm_format_helper_test ==============
[15:36:27] ================= drm_format (18 subtests) =================
[15:36:27] [PASSED] drm_test_format_block_width_invalid
[15:36:27] [PASSED] drm_test_format_block_width_one_plane
[15:36:27] [PASSED] drm_test_format_block_width_two_plane
[15:36:27] [PASSED] drm_test_format_block_width_three_plane
[15:36:27] [PASSED] drm_test_format_block_width_tiled
[15:36:27] [PASSED] drm_test_format_block_height_invalid
[15:36:27] [PASSED] drm_test_format_block_height_one_plane
[15:36:27] [PASSED] drm_test_format_block_height_two_plane
[15:36:27] [PASSED] drm_test_format_block_height_three_plane
[15:36:27] [PASSED] drm_test_format_block_height_tiled
[15:36:27] [PASSED] drm_test_format_min_pitch_invalid
[15:36:27] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[15:36:27] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[15:36:27] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[15:36:27] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[15:36:27] [PASSED] drm_test_format_min_pitch_two_plane
[15:36:27] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[15:36:27] [PASSED] drm_test_format_min_pitch_tiled
[15:36:27] =================== [PASSED] drm_format ====================
[15:36:27] ============== drm_framebuffer (10 subtests) ===============
[15:36:27] ========== drm_test_framebuffer_check_src_coords ==========
[15:36:27] [PASSED] Success: source fits into fb
[15:36:27] [PASSED] Fail: overflowing fb with x-axis coordinate
[15:36:27] [PASSED] Fail: overflowing fb with y-axis coordinate
[15:36:27] [PASSED] Fail: overflowing fb with source width
[15:36:27] [PASSED] Fail: overflowing fb with source height
[15:36:27] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[15:36:27] [PASSED] drm_test_framebuffer_cleanup
[15:36:27] =============== drm_test_framebuffer_create ===============
[15:36:27] [PASSED] ABGR8888 normal sizes
[15:36:27] [PASSED] ABGR8888 max sizes
[15:36:27] [PASSED] ABGR8888 pitch greater than min required
[15:36:27] [PASSED] ABGR8888 pitch less than min required
[15:36:27] [PASSED] ABGR8888 Invalid width
[15:36:27] [PASSED] ABGR8888 Invalid buffer handle
[15:36:27] [PASSED] No pixel format
[15:36:27] [PASSED] ABGR8888 Width 0
[15:36:27] [PASSED] ABGR8888 Height 0
[15:36:27] [PASSED] ABGR8888 Out of bound height * pitch combination
[15:36:27] [PASSED] ABGR8888 Large buffer offset
[15:36:27] [PASSED] ABGR8888 Buffer offset for inexistent plane
[15:36:27] [PASSED] ABGR8888 Invalid flag
[15:36:27] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[15:36:27] [PASSED] ABGR8888 Valid buffer modifier
[15:36:27] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[15:36:27] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[15:36:27] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[15:36:27] [PASSED] NV12 Normal sizes
[15:36:27] [PASSED] NV12 Max sizes
[15:36:27] [PASSED] NV12 Invalid pitch
[15:36:27] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[15:36:27] [PASSED] NV12 different modifier per-plane
[15:36:27] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[15:36:27] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[15:36:27] [PASSED] NV12 Modifier for inexistent plane
[15:36:27] [PASSED] NV12 Handle for inexistent plane
[15:36:27] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[15:36:27] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[15:36:27] [PASSED] YVU420 Normal sizes
[15:36:27] [PASSED] YVU420 Max sizes
[15:36:27] [PASSED] YVU420 Invalid pitch
[15:36:27] [PASSED] YVU420 Different pitches
[15:36:27] [PASSED] YVU420 Different buffer offsets/pitches
[15:36:27] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[15:36:27] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[15:36:27] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[15:36:27] [PASSED] YVU420 Valid modifier
[15:36:27] [PASSED] YVU420 Different modifiers per plane
[15:36:27] [PASSED] YVU420 Modifier for inexistent plane
[15:36:27] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[15:36:27] [PASSED] X0L2 Normal sizes
[15:36:27] [PASSED] X0L2 Max sizes
[15:36:27] [PASSED] X0L2 Invalid pitch
[15:36:27] [PASSED] X0L2 Pitch greater than minimum required
[15:36:27] [PASSED] X0L2 Handle for inexistent plane
[15:36:27] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[15:36:27] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[15:36:27] [PASSED] X0L2 Valid modifier
[15:36:27] [PASSED] X0L2 Modifier for inexistent plane
[15:36:27] =========== [PASSED] drm_test_framebuffer_create ===========
[15:36:27] [PASSED] drm_test_framebuffer_free
[15:36:27] [PASSED] drm_test_framebuffer_init
[15:36:27] [PASSED] drm_test_framebuffer_init_bad_format
[15:36:27] [PASSED] drm_test_framebuffer_init_dev_mismatch
[15:36:27] [PASSED] drm_test_framebuffer_lookup
[15:36:27] [PASSED] drm_test_framebuffer_lookup_inexistent
[15:36:27] [PASSED] drm_test_framebuffer_modifiers_not_supported
[15:36:27] ================= [PASSED] drm_framebuffer =================
[15:36:27] ================ drm_gem_shmem (8 subtests) ================
[15:36:27] [PASSED] drm_gem_shmem_test_obj_create
[15:36:27] [PASSED] drm_gem_shmem_test_obj_create_private
[15:36:27] [PASSED] drm_gem_shmem_test_pin_pages
[15:36:27] [PASSED] drm_gem_shmem_test_vmap
[15:36:27] [PASSED] drm_gem_shmem_test_get_sg_table
[15:36:27] [PASSED] drm_gem_shmem_test_get_pages_sgt
[15:36:27] [PASSED] drm_gem_shmem_test_madvise
[15:36:27] [PASSED] drm_gem_shmem_test_purge
[15:36:27] ================== [PASSED] drm_gem_shmem ==================
[15:36:27] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[15:36:27] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[15:36:27] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[15:36:27] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[15:36:27] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[15:36:27] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[15:36:27] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[15:36:27] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[15:36:27] [PASSED] Automatic
[15:36:27] [PASSED] Full
[15:36:27] [PASSED] Limited 16:235
[15:36:27] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[15:36:27] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[15:36:27] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[15:36:27] [PASSED] drm_test_check_disable_connector
[15:36:27] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[15:36:27] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[15:36:27] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[15:36:27] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[15:36:27] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[15:36:27] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[15:36:27] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[15:36:27] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[15:36:27] [PASSED] drm_test_check_output_bpc_dvi
[15:36:27] [PASSED] drm_test_check_output_bpc_format_vic_1
[15:36:27] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[15:36:27] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[15:36:27] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[15:36:27] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[15:36:27] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[15:36:27] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[15:36:27] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[15:36:27] ============ drm_test_check_hdmi_color_format =============
[15:36:27] [PASSED] AUTO -> RGB
[15:36:27] [PASSED] YCBCR422 -> YUV422
[15:36:27] [PASSED] YCBCR420 -> YUV420
[15:36:27] [PASSED] YCBCR444 -> YUV444
[15:36:27] [PASSED] RGB -> RGB
[15:36:27] ======== [PASSED] drm_test_check_hdmi_color_format =========
[15:36:27] ======== drm_test_check_hdmi_color_format_420_only ========
[15:36:27] [PASSED] RGB should fail
[15:36:27] [PASSED] YUV444 should fail
[15:36:27] [PASSED] YUV422 should fail
[15:36:27] [PASSED] YUV420 should work
[15:36:27] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[15:36:27] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[15:36:27] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[15:36:27] [PASSED] drm_test_check_broadcast_rgb_value
[15:36:27] [PASSED] drm_test_check_bpc_8_value
[15:36:27] [PASSED] drm_test_check_bpc_10_value
[15:36:27] [PASSED] drm_test_check_bpc_12_value
[15:36:27] [PASSED] drm_test_check_format_value
[15:36:27] [PASSED] drm_test_check_tmds_char_value
[15:36:27] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[15:36:27] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[15:36:27] [PASSED] drm_test_check_mode_valid
[15:36:27] [PASSED] drm_test_check_mode_valid_reject
[15:36:27] [PASSED] drm_test_check_mode_valid_reject_rate
[15:36:27] [PASSED] drm_test_check_mode_valid_reject_max_clock
[15:36:27] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[15:36:27] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[15:36:27] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[15:36:27] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[15:36:27] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[15:36:27] [PASSED] drm_test_check_infoframes
[15:36:27] [PASSED] drm_test_check_reject_avi_infoframe
[15:36:27] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[15:36:27] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[15:36:27] [PASSED] drm_test_check_reject_audio_infoframe
[15:36:27] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[15:36:27] ================= drm_managed (2 subtests) =================
[15:36:27] [PASSED] drm_test_managed_release_action
[15:36:27] [PASSED] drm_test_managed_run_action
[15:36:27] =================== [PASSED] drm_managed ===================
[15:36:27] =================== drm_mm (6 subtests) ====================
[15:36:27] [PASSED] drm_test_mm_init
[15:36:27] [PASSED] drm_test_mm_debug
[15:36:27] [PASSED] drm_test_mm_align32
[15:36:27] [PASSED] drm_test_mm_align64
[15:36:27] [PASSED] drm_test_mm_lowest
[15:36:27] [PASSED] drm_test_mm_highest
[15:36:27] ===================== [PASSED] drm_mm ======================
[15:36:27] ============= drm_modes_analog_tv (5 subtests) =============
[15:36:27] [PASSED] drm_test_modes_analog_tv_mono_576i
[15:36:27] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[15:36:27] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[15:36:27] [PASSED] drm_test_modes_analog_tv_pal_576i
[15:36:27] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[15:36:27] =============== [PASSED] drm_modes_analog_tv ===============
[15:36:27] ============== drm_panic_helper (3 subtests) ===============
[15:36:27] ============= drm_test_panic_screen_user_map ==============
[15:36:27] [PASSED] Panic screen user, mode: 1024 x 768 XR24 little-endian (0x34325258)
[15:36:27] [PASSED] Panic screen user, mode: 494 x 494 XR24 little-endian (0x34325258)
[15:36:27] [PASSED] Panic screen user, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[15:36:27] [PASSED] Panic screen user, mode: 1024 x 768 RG16 little-endian (0x36314752)
[15:36:27] [PASSED] Panic screen user, mode: 1024 x 768 RG24 little-endian (0x34324752)
[15:36:27] [PASSED] Panic screen kmsg, mode: 1024 x 768 XR24 little-endian (0x34325258)
[15:36:27] [PASSED] Panic screen kmsg, mode: 494 x 494 XR24 little-endian (0x34325258)
[15:36:27] [PASSED] Panic screen kmsg, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[15:36:27] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG16 little-endian (0x36314752)
[15:36:27] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG24 little-endian (0x34324752)
[15:36:27] ========= [PASSED] drm_test_panic_screen_user_map ==========
[15:36:27] ============= drm_test_panic_screen_user_page =============
[15:36:27] [PASSED] Panic screen user, mode: 1024 x 768 XR24 little-endian (0x34325258)
[15:36:27] [PASSED] Panic screen user, mode: 494 x 494 XR24 little-endian (0x34325258)
[15:36:27] [PASSED] Panic screen user, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[15:36:27] [PASSED] Panic screen user, mode: 1024 x 768 RG16 little-endian (0x36314752)
[15:36:27] [PASSED] Panic screen user, mode: 1024 x 768 RG24 little-endian (0x34324752)
[15:36:27] [PASSED] Panic screen kmsg, mode: 1024 x 768 XR24 little-endian (0x34325258)
[15:36:27] [PASSED] Panic screen kmsg, mode: 494 x 494 XR24 little-endian (0x34325258)
[15:36:27] [PASSED] Panic screen kmsg, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[15:36:27] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG16 little-endian (0x36314752)
[15:36:27] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG24 little-endian (0x34324752)
[15:36:27] ========= [PASSED] drm_test_panic_screen_user_page =========
[15:36:27] ========== drm_test_panic_screen_user_set_pixel ===========
[15:36:27] [PASSED] Panic screen user, mode: 1024 x 768 XR24 little-endian (0x34325258)
[15:36:27] [PASSED] Panic screen user, mode: 494 x 494 XR24 little-endian (0x34325258)
[15:36:27] [PASSED] Panic screen user, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[15:36:27] [PASSED] Panic screen user, mode: 1024 x 768 RG16 little-endian (0x36314752)
[15:36:27] [PASSED] Panic screen user, mode: 1024 x 768 RG24 little-endian (0x34324752)
[15:36:27] [PASSED] Panic screen kmsg, mode: 1024 x 768 XR24 little-endian (0x34325258)
[15:36:27] [PASSED] Panic screen kmsg, mode: 494 x 494 XR24 little-endian (0x34325258)
[15:36:27] [PASSED] Panic screen kmsg, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[15:36:27] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG16 little-endian (0x36314752)
[15:36:27] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG24 little-endian (0x34324752)
[15:36:27] ====== [PASSED] drm_test_panic_screen_user_set_pixel =======
[15:36:27] ================ [PASSED] drm_panic_helper =================
[15:36:27] ============== drm_plane_helper (2 subtests) ===============
[15:36:27] =============== drm_test_check_plane_state ================
[15:36:27] [PASSED] clipping_simple
[15:36:27] [PASSED] clipping_rotate_reflect
[15:36:27] [PASSED] positioning_simple
[15:36:27] [PASSED] upscaling
[15:36:27] [PASSED] downscaling
[15:36:27] [PASSED] rounding1
[15:36:27] [PASSED] rounding2
[15:36:27] [PASSED] rounding3
[15:36:27] [PASSED] rounding4
[15:36:27] =========== [PASSED] drm_test_check_plane_state ============
[15:36:27] =========== drm_test_check_invalid_plane_state ============
[15:36:27] [PASSED] positioning_invalid
[15:36:27] [PASSED] upscaling_invalid
[15:36:27] [PASSED] downscaling_invalid
[15:36:27] ======= [PASSED] drm_test_check_invalid_plane_state ========
[15:36:27] ================ [PASSED] drm_plane_helper =================
[15:36:27] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[15:36:27] ====== drm_test_connector_helper_tv_get_modes_check =======
[15:36:27] [PASSED] None
[15:36:27] [PASSED] PAL
[15:36:27] [PASSED] NTSC
[15:36:27] [PASSED] Both, NTSC Default
[15:36:27] [PASSED] Both, PAL Default
[15:36:27] [PASSED] Both, NTSC Default, with PAL on command-line
[15:36:27] [PASSED] Both, PAL Default, with NTSC on command-line
[15:36:27] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[15:36:27] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[15:36:27] ================== drm_rect (9 subtests) ===================
[15:36:27] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[15:36:27] [PASSED] drm_test_rect_clip_scaled_not_clipped
[15:36:27] [PASSED] drm_test_rect_clip_scaled_clipped
[15:36:27] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[15:36:27] ================= drm_test_rect_intersect =================
[15:36:27] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[15:36:27] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[15:36:27] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[15:36:27] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[15:36:27] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[15:36:27] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[15:36:27] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[15:36:27] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[15:36:27] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[15:36:27] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[15:36:27] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[15:36:27] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[15:36:27] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[15:36:27] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[15:36:27] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[15:36:27] ============= [PASSED] drm_test_rect_intersect =============
[15:36:27] ================ drm_test_rect_calc_hscale ================
[15:36:27] [PASSED] normal use
[15:36:27] [PASSED] out of max range
[15:36:27] [PASSED] out of min range
[15:36:27] [PASSED] zero dst
[15:36:27] [PASSED] negative src
[15:36:27] [PASSED] negative dst
[15:36:27] ============ [PASSED] drm_test_rect_calc_hscale ============
[15:36:27] ================ drm_test_rect_calc_vscale ================
[15:36:27] [PASSED] normal use
[15:36:27] [PASSED] out of max range
[15:36:27] [PASSED] out of min range
[15:36:27] [PASSED] zero dst
[15:36:27] [PASSED] negative src
[15:36:27] [PASSED] negative dst
[15:36:27] ============ [PASSED] drm_test_rect_calc_vscale ============
[15:36:27] ================== drm_test_rect_rotate ===================
[15:36:27] [PASSED] reflect-x
[15:36:27] [PASSED] reflect-y
[15:36:27] [PASSED] rotate-0
[15:36:27] [PASSED] rotate-90
[15:36:27] [PASSED] rotate-180
[15:36:27] [PASSED] rotate-270
[15:36:27] ============== [PASSED] drm_test_rect_rotate ===============
[15:36:27] ================ drm_test_rect_rotate_inv =================
[15:36:27] [PASSED] reflect-x
[15:36:27] [PASSED] reflect-y
[15:36:27] [PASSED] rotate-0
[15:36:27] [PASSED] rotate-90
[15:36:27] [PASSED] rotate-180
[15:36:27] [PASSED] rotate-270
[15:36:27] ============ [PASSED] drm_test_rect_rotate_inv =============
[15:36:27] ==================== [PASSED] drm_rect =====================
[15:36:27] ============ drm_sysfb_modeset_test (1 subtest) ============
[15:36:27] ============ drm_test_sysfb_build_fourcc_list =============
[15:36:27] [PASSED] no native formats
[15:36:27] [PASSED] XRGB8888 as native format
[15:36:27] [PASSED] remove duplicates
[15:36:27] [PASSED] convert alpha formats
[15:36:27] [PASSED] random formats
[15:36:27] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[15:36:27] ============= [PASSED] drm_sysfb_modeset_test ==============
[15:36:27] ================== drm_fixp (2 subtests) ===================
[15:36:27] [PASSED] drm_test_int2fixp
[15:36:27] [PASSED] drm_test_sm2fixp
[15:36:27] ==================== [PASSED] drm_fixp =====================
[15:36:27] ============================================================
[15:36:27] Testing complete. Ran 667 tests: passed: 667
[15:36:27] Elapsed time: 26.865s total, 1.782s configuring, 24.666s building, 0.411s running
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[15:36:27] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[15:36:29] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[15:36:39] Starting KUnit Kernel (1/1)...
[15:36:39] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[15:36:40] ================= ttm_device (5 subtests) ==================
[15:36:40] [PASSED] ttm_device_init_basic
[15:36:40] [PASSED] ttm_device_init_multiple
[15:36:40] [PASSED] ttm_device_fini_basic
[15:36:40] [PASSED] ttm_device_init_no_vma_man
[15:36:40] ================== ttm_device_init_pools ==================
[15:36:40] [PASSED] No DMA allocations, no DMA32 required
[15:36:40] [PASSED] DMA allocations, DMA32 required
[15:36:40] [PASSED] No DMA allocations, DMA32 required
[15:36:40] [PASSED] DMA allocations, no DMA32 required
[15:36:40] ============== [PASSED] ttm_device_init_pools ==============
[15:36:40] =================== [PASSED] ttm_device ====================
[15:36:40] ================== ttm_pool (8 subtests) ===================
[15:36:40] ================== ttm_pool_alloc_basic ===================
[15:36:40] [PASSED] One page
[15:36:40] [PASSED] More than one page
[15:36:40] [PASSED] Above the allocation limit
[15:36:40] [PASSED] One page, with coherent DMA mappings enabled
[15:36:40] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[15:36:40] ============== [PASSED] ttm_pool_alloc_basic ===============
[15:36:40] ============== ttm_pool_alloc_basic_dma_addr ==============
[15:36:40] [PASSED] One page
[15:36:40] [PASSED] More than one page
[15:36:40] [PASSED] Above the allocation limit
[15:36:40] [PASSED] One page, with coherent DMA mappings enabled
[15:36:40] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[15:36:40] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[15:36:40] [PASSED] ttm_pool_alloc_order_caching_match
[15:36:40] [PASSED] ttm_pool_alloc_caching_mismatch
[15:36:40] [PASSED] ttm_pool_alloc_order_mismatch
[15:36:40] [PASSED] ttm_pool_free_dma_alloc
[15:36:40] [PASSED] ttm_pool_free_no_dma_alloc
[15:36:40] [PASSED] ttm_pool_fini_basic
[15:36:40] ==================== [PASSED] ttm_pool =====================
[15:36:40] ================ ttm_resource (8 subtests) =================
[15:36:40] ================= ttm_resource_init_basic =================
[15:36:40] [PASSED] Init resource in TTM_PL_SYSTEM
[15:36:40] [PASSED] Init resource in TTM_PL_VRAM
[15:36:40] [PASSED] Init resource in a private placement
[15:36:40] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[15:36:40] ============= [PASSED] ttm_resource_init_basic =============
[15:36:40] [PASSED] ttm_resource_init_pinned
[15:36:40] [PASSED] ttm_resource_fini_basic
[15:36:40] [PASSED] ttm_resource_manager_init_basic
[15:36:40] [PASSED] ttm_resource_manager_usage_basic
[15:36:40] [PASSED] ttm_resource_manager_set_used_basic
[15:36:40] [PASSED] ttm_sys_man_alloc_basic
[15:36:40] [PASSED] ttm_sys_man_free_basic
[15:36:40] ================== [PASSED] ttm_resource ===================
[15:36:40] =================== ttm_tt (15 subtests) ===================
[15:36:40] ==================== ttm_tt_init_basic ====================
[15:36:40] [PASSED] Page-aligned size
[15:36:40] [PASSED] Extra pages requested
[15:36:40] ================ [PASSED] ttm_tt_init_basic ================
[15:36:40] [PASSED] ttm_tt_init_misaligned
[15:36:40] [PASSED] ttm_tt_fini_basic
[15:36:40] [PASSED] ttm_tt_fini_sg
[15:36:40] [PASSED] ttm_tt_fini_shmem
[15:36:40] [PASSED] ttm_tt_create_basic
[15:36:40] [PASSED] ttm_tt_create_invalid_bo_type
[15:36:40] [PASSED] ttm_tt_create_ttm_exists
[15:36:40] [PASSED] ttm_tt_create_failed
[15:36:40] [PASSED] ttm_tt_destroy_basic
[15:36:40] [PASSED] ttm_tt_populate_null_ttm
[15:36:40] [PASSED] ttm_tt_populate_populated_ttm
[15:36:40] [PASSED] ttm_tt_unpopulate_basic
[15:36:40] [PASSED] ttm_tt_unpopulate_empty_ttm
[15:36:40] [PASSED] ttm_tt_swapin_basic
[15:36:40] ===================== [PASSED] ttm_tt ======================
[15:36:40] =================== ttm_bo (14 subtests) ===================
[15:36:40] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[15:36:40] [PASSED] Cannot be interrupted and sleeps
[15:36:40] [PASSED] Cannot be interrupted, locks straight away
[15:36:40] [PASSED] Can be interrupted, sleeps
[15:36:40] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[15:36:40] [PASSED] ttm_bo_reserve_locked_no_sleep
[15:36:40] [PASSED] ttm_bo_reserve_no_wait_ticket
[15:36:40] [PASSED] ttm_bo_reserve_double_resv
[15:36:40] [PASSED] ttm_bo_reserve_interrupted
[15:36:40] [PASSED] ttm_bo_reserve_deadlock
[15:36:40] [PASSED] ttm_bo_unreserve_basic
[15:36:40] [PASSED] ttm_bo_unreserve_pinned
[15:36:40] [PASSED] ttm_bo_unreserve_bulk
[15:36:40] [PASSED] ttm_bo_fini_basic
[15:36:40] [PASSED] ttm_bo_fini_shared_resv
[15:36:40] [PASSED] ttm_bo_pin_basic
[15:36:40] [PASSED] ttm_bo_pin_unpin_resource
[15:36:40] [PASSED] ttm_bo_multiple_pin_one_unpin
[15:36:40] ===================== [PASSED] ttm_bo ======================
[15:36:40] ============== ttm_bo_validate (22 subtests) ===============
[15:36:40] ============== ttm_bo_init_reserved_sys_man ===============
[15:36:40] [PASSED] Buffer object for userspace
[15:36:40] [PASSED] Kernel buffer object
[15:36:40] [PASSED] Shared buffer object
[15:36:40] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[15:36:40] ============== ttm_bo_init_reserved_mock_man ==============
[15:36:40] [PASSED] Buffer object for userspace
[15:36:40] [PASSED] Kernel buffer object
[15:36:40] [PASSED] Shared buffer object
[15:36:40] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[15:36:40] [PASSED] ttm_bo_init_reserved_resv
[15:36:40] ================== ttm_bo_validate_basic ==================
[15:36:40] [PASSED] Buffer object for userspace
[15:36:40] [PASSED] Kernel buffer object
[15:36:40] [PASSED] Shared buffer object
[15:36:40] ============== [PASSED] ttm_bo_validate_basic ==============
[15:36:40] [PASSED] ttm_bo_validate_invalid_placement
[15:36:40] ============= ttm_bo_validate_same_placement ==============
[15:36:40] [PASSED] System manager
[15:36:40] [PASSED] VRAM manager
[15:36:40] ========= [PASSED] ttm_bo_validate_same_placement ==========
[15:36:40] [PASSED] ttm_bo_validate_failed_alloc
[15:36:40] [PASSED] ttm_bo_validate_pinned
[15:36:40] [PASSED] ttm_bo_validate_busy_placement
[15:36:40] ================ ttm_bo_validate_multihop =================
[15:36:40] [PASSED] Buffer object for userspace
[15:36:40] [PASSED] Kernel buffer object
[15:36:40] [PASSED] Shared buffer object
[15:36:40] ============ [PASSED] ttm_bo_validate_multihop =============
[15:36:40] ========== ttm_bo_validate_no_placement_signaled ==========
[15:36:40] [PASSED] Buffer object in system domain, no page vector
[15:36:40] [PASSED] Buffer object in system domain with an existing page vector
[15:36:40] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[15:36:40] ======== ttm_bo_validate_no_placement_not_signaled ========
[15:36:40] [PASSED] Buffer object for userspace
[15:36:40] [PASSED] Kernel buffer object
[15:36:40] [PASSED] Shared buffer object
[15:36:40] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[15:36:40] [PASSED] ttm_bo_validate_move_fence_signaled
[15:36:40] ========= ttm_bo_validate_move_fence_not_signaled =========
[15:36:40] [PASSED] Waits for GPU
[15:36:40] [PASSED] Tries to lock straight away
[15:36:40] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[15:36:40] [PASSED] ttm_bo_validate_swapout
[15:36:40] [PASSED] ttm_bo_validate_happy_evict
[15:36:40] [PASSED] ttm_bo_validate_all_pinned_evict
[15:36:40] [PASSED] ttm_bo_validate_allowed_only_evict
[15:36:40] [PASSED] ttm_bo_validate_deleted_evict
[15:36:40] [PASSED] ttm_bo_validate_busy_domain_evict
[15:36:40] [PASSED] ttm_bo_validate_evict_gutting
[15:36:40] [PASSED] ttm_bo_validate_recrusive_evict
[15:36:40] ================= [PASSED] ttm_bo_validate =================
[15:36:40] ============================================================
[15:36:40] Testing complete. Ran 102 tests: passed: 102
[15:36:40] Elapsed time: 12.178s total, 1.804s configuring, 10.159s building, 0.175s running
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/dma-buf/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[15:36:40] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[15:36:42] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[15:36:50] Starting KUnit Kernel (1/1)...
[15:36:50] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[15:36:51] =============== dma-buf-fence (12 subtests) ================
[15:36:51] [PASSED] test_sanitycheck
[15:36:51] [PASSED] test_signaling
[15:36:51] [PASSED] test_add_callback
[15:36:51] [PASSED] test_late_add_callback
[15:36:51] [PASSED] test_rm_callback
[15:36:51] [PASSED] test_late_rm_callback
[15:36:51] [PASSED] test_status
[15:36:51] [PASSED] test_error
[15:36:51] [PASSED] test_wait
[15:36:51] [PASSED] test_wait_timeout
[15:36:51] [PASSED] test_stub
[15:36:51] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[15:36:51] ================== [PASSED] dma-buf-fence ==================
[15:36:51] ============ dma-buf-fence-chain (11 subtests) =============
[15:36:51] [PASSED] test_sanitycheck
[15:36:51] [PASSED] test_find_seqno
[15:36:51] [PASSED] test_find_signaled
[15:36:51] [PASSED] test_find_out_of_order
[15:36:56] [PASSED] test_find_gap
[15:36:56] [PASSED] test_find_race
[15:36:56] [PASSED] test_signal_forward
[15:36:56] [PASSED] test_signal_backward
[15:36:56] [PASSED] test_wait_forward
[15:36:56] [PASSED] test_wait_backward
[15:36:56] [PASSED] test_wait_random
[15:36:56] =============== [PASSED] dma-buf-fence-chain ===============
[15:36:56] ============ dma-buf-fence-unwrap (11 subtests) ============
[15:36:56] [PASSED] test_sanitycheck
[15:36:56] [PASSED] test_unwrap_array
[15:36:56] [PASSED] test_unwrap_chain
[15:36:56] [PASSED] test_unwrap_chain_array
[15:36:56] [PASSED] test_unwrap_merge
[15:36:56] [PASSED] test_unwrap_merge_duplicate
[15:36:56] [PASSED] test_unwrap_merge_seqno
[15:36:56] [PASSED] test_unwrap_merge_order
[15:36:56] [PASSED] test_unwrap_merge_complex
[15:36:56] [PASSED] test_unwrap_merge_complex_seqno
[15:36:56] [PASSED] test_dedup_empty
[15:36:56] ============== [PASSED] dma-buf-fence-unwrap ===============
[15:36:56] ================ dma-buf-resv (5 subtests) =================
[15:36:56] [PASSED] test_sanitycheck
[15:36:56] ===================== test_signaling ======================
[15:36:56] [PASSED] kernel
[15:36:56] [PASSED] write
[15:36:56] [PASSED] read
[15:36:56] [PASSED] bookkeep
[15:36:56] ================= [PASSED] test_signaling ==================
[15:36:56] ====================== test_for_each ======================
[15:36:56] [PASSED] kernel
[15:36:56] [PASSED] write
[15:36:56] [PASSED] read
[15:36:56] [PASSED] bookkeep
[15:36:56] ================== [PASSED] test_for_each ==================
[15:36:56] ================= test_for_each_unlocked ==================
[15:36:56] [PASSED] kernel
[15:36:56] [PASSED] write
[15:36:56] [PASSED] read
[15:36:56] [PASSED] bookkeep
[15:36:56] ============= [PASSED] test_for_each_unlocked ==============
[15:36:56] ===================== test_get_fences =====================
[15:36:56] [PASSED] kernel
[15:36:56] [PASSED] write
[15:36:56] [PASSED] read
[15:36:56] [PASSED] bookkeep
[15:36:56] ================= [PASSED] test_get_fences =================
[15:36:56] ================== [PASSED] dma-buf-resv ===================
[15:36:56] ============================================================
[15:36:56] Testing complete. Ran 51 tests: passed: 50, skipped: 1
[15:36:56] Elapsed time: 15.986s total, 1.885s configuring, 8.729s building, 5.337s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 8+ messages in thread
* ✗ Xe.CI.BAT: failure for drm/xe/ggtt: Cut GGTT initialization from 900 ms to 37 ms (rev2)
2026-10-28 4:50 [RFC PATCH] drm/xe/ggtt: Cut GGTT initialization from 900 ms to 37 ms Daniel Colascione
` (2 preceding siblings ...)
2026-10-28 15:37 ` ✓ CI.KUnit: success for drm/xe/ggtt: Cut GGTT initialization from 900 ms to 37 ms (rev2) Patchwork
@ 2026-10-28 16:11 ` Patchwork
2026-10-29 2:06 ` ✗ Xe.CI.FULL: " Patchwork
2026-10-29 15:16 ` [RFC PATCH] drm/xe/ggtt: Cut GGTT initialization from 900 ms to 37 ms Matthew Brost
5 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2026-10-28 16:11 UTC (permalink / raw)
To: Daniel Colascione; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 2691 bytes --]
== Series Details ==
Series: drm/xe/ggtt: Cut GGTT initialization from 900 ms to 37 ms (rev2)
URL : https://patchwork.freedesktop.org/series/177030/
State : failure
== Summary ==
CI Bug Log - changes from xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10_BAT -> xe-pw-177030v2_BAT
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-177030v2_BAT absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-177030v2_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (15 -> 15)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-177030v2_BAT:
### IGT changes ###
#### Possible regressions ####
* igt@xe_module_load@load:
- bat-lnl-1: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10/bat-lnl-1/igt@xe_module_load@load.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/bat-lnl-1/igt@xe_module_load@load.html
- bat-lnl-2: [PASS][3] -> [ABORT][4]
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10/bat-lnl-2/igt@xe_module_load@load.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/bat-lnl-2/igt@xe_module_load@load.html
Known issues
------------
Here are the changes found in xe-pw-177030v2_BAT that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@xe_live_ktest@xe_migrate@xe_migrate_access_memory_kunit:
- bat-atsm-2: [PASS][5] -> [ABORT][6] ([Intel XE#9663]) +1 other test abort
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10/bat-atsm-2/igt@xe_live_ktest@xe_migrate@xe_migrate_access_memory_kunit.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/bat-atsm-2/igt@xe_live_ktest@xe_migrate@xe_migrate_access_memory_kunit.html
[Intel XE#9663]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9663
Build changes
-------------
* Linux: xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10 -> xe-pw-177030v2
IGT_9169: 9169
xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10: 18bb5742e834aeb869af8b7262ce7e16ad9e1b10
xe-pw-177030v2: 177030v2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/index.html
[-- Attachment #2: Type: text/html, Size: 3305 bytes --]
^ permalink raw reply [flat|nested] 8+ messages in thread
* ✗ Xe.CI.FULL: failure for drm/xe/ggtt: Cut GGTT initialization from 900 ms to 37 ms (rev2)
2026-10-28 4:50 [RFC PATCH] drm/xe/ggtt: Cut GGTT initialization from 900 ms to 37 ms Daniel Colascione
` (3 preceding siblings ...)
2026-10-28 16:11 ` ✗ Xe.CI.BAT: failure " Patchwork
@ 2026-10-29 2:06 ` Patchwork
2026-10-29 15:16 ` [RFC PATCH] drm/xe/ggtt: Cut GGTT initialization from 900 ms to 37 ms Matthew Brost
5 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2026-10-29 2:06 UTC (permalink / raw)
To: Daniel Colascione; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 19109 bytes --]
== Series Details ==
Series: drm/xe/ggtt: Cut GGTT initialization from 900 ms to 37 ms (rev2)
URL : https://patchwork.freedesktop.org/series/177030/
State : failure
== Summary ==
CI Bug Log - changes from xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10_FULL -> xe-pw-177030v2_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-177030v2_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-177030v2_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (3 -> 3)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-177030v2_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@runner@aborted:
- shard-lnl: NOTRUN -> ([FAIL][1], [FAIL][2], [FAIL][3], [FAIL][4], [FAIL][5], [FAIL][6], [FAIL][7], [FAIL][8], [FAIL][9], [FAIL][10], [FAIL][11], [FAIL][12], [FAIL][13], [FAIL][14], [FAIL][15], [FAIL][16], [FAIL][17], [FAIL][18], [FAIL][19], [FAIL][20], [FAIL][21], [FAIL][22], [FAIL][23], [FAIL][24], [FAIL][25])
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-1/igt@runner@aborted.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-7/igt@runner@aborted.html
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-7/igt@runner@aborted.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-7/igt@runner@aborted.html
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-7/igt@runner@aborted.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-5/igt@runner@aborted.html
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-5/igt@runner@aborted.html
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-5/igt@runner@aborted.html
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-5/igt@runner@aborted.html
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-8/igt@runner@aborted.html
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-8/igt@runner@aborted.html
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-8/igt@runner@aborted.html
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-8/igt@runner@aborted.html
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-4/igt@runner@aborted.html
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-4/igt@runner@aborted.html
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-4/igt@runner@aborted.html
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-2/igt@runner@aborted.html
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-2/igt@runner@aborted.html
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-2/igt@runner@aborted.html
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-2/igt@runner@aborted.html
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-3/igt@runner@aborted.html
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-3/igt@runner@aborted.html
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-1/igt@runner@aborted.html
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-1/igt@runner@aborted.html
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-1/igt@runner@aborted.html
* igt@xe_module_load@load:
- shard-lnl: ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50]) -> ([ABORT][51], [ABORT][52], [ABORT][53], [ABORT][54], [ABORT][55], [ABORT][56], [ABORT][57], [ABORT][58], [ABORT][59], [ABORT][60], [ABORT][61], [ABORT][62], [ABORT][63], [ABORT][64], [ABORT][65], [ABORT][66], [ABORT][67], [ABORT][68], [ABORT][69], [ABORT][70], [ABORT][71], [ABORT][72], [ABORT][73], [ABORT][74], [ABORT][75])
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10/shard-lnl-4/igt@xe_module_load@load.html
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10/shard-lnl-5/igt@xe_module_load@load.html
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10/shard-lnl-2/igt@xe_module_load@load.html
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10/shard-lnl-3/igt@xe_module_load@load.html
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10/shard-lnl-1/igt@xe_module_load@load.html
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10/shard-lnl-2/igt@xe_module_load@load.html
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10/shard-lnl-8/igt@xe_module_load@load.html
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10/shard-lnl-2/igt@xe_module_load@load.html
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10/shard-lnl-5/igt@xe_module_load@load.html
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10/shard-lnl-2/igt@xe_module_load@load.html
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10/shard-lnl-1/igt@xe_module_load@load.html
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10/shard-lnl-4/igt@xe_module_load@load.html
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10/shard-lnl-3/igt@xe_module_load@load.html
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10/shard-lnl-3/igt@xe_module_load@load.html
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10/shard-lnl-7/igt@xe_module_load@load.html
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10/shard-lnl-7/igt@xe_module_load@load.html
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10/shard-lnl-4/igt@xe_module_load@load.html
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10/shard-lnl-5/igt@xe_module_load@load.html
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10/shard-lnl-5/igt@xe_module_load@load.html
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10/shard-lnl-1/igt@xe_module_load@load.html
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10/shard-lnl-8/igt@xe_module_load@load.html
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10/shard-lnl-8/igt@xe_module_load@load.html
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10/shard-lnl-4/igt@xe_module_load@load.html
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10/shard-lnl-7/igt@xe_module_load@load.html
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10/shard-lnl-8/igt@xe_module_load@load.html
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-3/igt@xe_module_load@load.html
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-3/igt@xe_module_load@load.html
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-2/igt@xe_module_load@load.html
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-2/igt@xe_module_load@load.html
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-2/igt@xe_module_load@load.html
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-5/igt@xe_module_load@load.html
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-5/igt@xe_module_load@load.html
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-5/igt@xe_module_load@load.html
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-5/igt@xe_module_load@load.html
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-7/igt@xe_module_load@load.html
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-7/igt@xe_module_load@load.html
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-7/igt@xe_module_load@load.html
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-7/igt@xe_module_load@load.html
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-1/igt@xe_module_load@load.html
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-4/igt@xe_module_load@load.html
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-2/igt@xe_module_load@load.html
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-1/igt@xe_module_load@load.html
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-1/igt@xe_module_load@load.html
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-8/igt@xe_module_load@load.html
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-8/igt@xe_module_load@load.html
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-8/igt@xe_module_load@load.html
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-8/igt@xe_module_load@load.html
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-4/igt@xe_module_load@load.html
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-4/igt@xe_module_load@load.html
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-lnl-1/igt@xe_module_load@load.html
Known issues
------------
Here are the changes found in xe-pw-177030v2_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
- shard-bmg: NOTRUN -> [SKIP][76] ([Intel XE#2887])
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-bmg-3/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
* igt@kms_content_protection@atomic-dpms@pipe-a-dp-1:
- shard-bmg: NOTRUN -> [FAIL][77] ([Intel XE#3304] / [Intel XE#7374])
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-bmg-7/igt@kms_content_protection@atomic-dpms@pipe-a-dp-1.html
* igt@kms_content_protection@uevent@pipe-a-dp-2:
- shard-bmg: NOTRUN -> [FAIL][78] ([Intel XE#6707] / [Intel XE#7439])
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-bmg-4/igt@kms_content_protection@uevent@pipe-a-dp-2.html
* igt@kms_cursor_legacy@flip-vs-cursor-legacy:
- shard-bmg: [PASS][79] -> [FAIL][80] ([Intel XE#7809])
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10/shard-bmg-10/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-bmg-5/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
* igt@kms_dp_link_training@non-uhbr-mst:
- shard-bmg: NOTRUN -> [SKIP][81] ([Intel XE#9536])
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-bmg-3/igt@kms_dp_link_training@non-uhbr-mst.html
* igt@kms_flip@2x-plain-flip-fb-recreate@bc-dp2-hdmi-a3:
- shard-bmg: [PASS][82] -> [FAIL][83] ([Intel XE#5408] / [Intel XE#6266]) +3 other tests fail
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10/shard-bmg-5/igt@kms_flip@2x-plain-flip-fb-recreate@bc-dp2-hdmi-a3.html
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-bmg-8/igt@kms_flip@2x-plain-flip-fb-recreate@bc-dp2-hdmi-a3.html
* igt@kms_flip@wf_vblank-ts-check:
- shard-bmg: [PASS][84] -> [FAIL][85] ([Intel XE#3098]) +4 other tests fail
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10/shard-bmg-10/igt@kms_flip@wf_vblank-ts-check.html
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-bmg-5/igt@kms_flip@wf_vblank-ts-check.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling:
- shard-bmg: NOTRUN -> [SKIP][86] ([Intel XE#7178] / [Intel XE#7351])
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-bmg-3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling.html
* igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-primscrn-cur-indfb-draw-mmap-wc:
- shard-bmg: NOTRUN -> [SKIP][87] ([Intel XE#2311]) +3 other tests skip
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-wc:
- shard-bmg: NOTRUN -> [SKIP][88] ([Intel XE#2313]) +2 other tests skip
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-bmg-3/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-wc.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-rebind:
- shard-bmg: NOTRUN -> [SKIP][89] ([Intel XE#2322] / [Intel XE#7372])
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-bmg-3/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-rebind.html
* igt@xe_exec_fault_mode@twice-multi-queue:
- shard-bmg: NOTRUN -> [SKIP][90] ([Intel XE#8374])
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-bmg-3/igt@xe_exec_fault_mode@twice-multi-queue.html
* igt@xe_exec_multi_queue@many-execs-dyn-priority-smem:
- shard-bmg: NOTRUN -> [SKIP][91] ([Intel XE#8364]) +1 other test skip
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-bmg-3/igt@xe_exec_multi_queue@many-execs-dyn-priority-smem.html
* igt@xe_exec_reset@multi-queue-gt-reset:
- shard-bmg: NOTRUN -> [SKIP][92] ([Intel XE#8369])
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-bmg-3/igt@xe_exec_reset@multi-queue-gt-reset.html
* igt@xe_exec_threads@threads-multi-queue-userptr-invalidate:
- shard-bmg: NOTRUN -> [SKIP][93] ([Intel XE#8378])
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-bmg-3/igt@xe_exec_threads@threads-multi-queue-userptr-invalidate.html
#### Possible fixes ####
* igt@kms_bw@linear-tiling-1-displays-target-1920x1080p:
- shard-bmg: [SKIP][94] ([Intel XE#367]) -> [PASS][95]
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10/shard-bmg-2/igt@kms_bw@linear-tiling-1-displays-target-1920x1080p.html
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-bmg-7/igt@kms_bw@linear-tiling-1-displays-target-1920x1080p.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
- shard-bmg: [INCOMPLETE][96] ([Intel XE#7084] / [Intel XE#8150]) -> [PASS][97] +1 other test pass
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10/shard-bmg-1/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-bmg-3/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
* igt@xe_evict@evict-mixed-many-threads-small:
- shard-bmg: [INCOMPLETE][98] ([Intel XE#6321] / [Intel XE#8355]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10/shard-bmg-2/igt@xe_evict@evict-mixed-many-threads-small.html
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/shard-bmg-7/igt@xe_evict@evict-mixed-many-threads-small.html
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#3098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3098
[Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#5408]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5408
[Intel XE#6266]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6266
[Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
[Intel XE#6707]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6707
[Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084
[Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
[Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
[Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
[Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
[Intel XE#7439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7439
[Intel XE#7809]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7809
[Intel XE#8150]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8150
[Intel XE#8355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8355
[Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
[Intel XE#8369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8369
[Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
[Intel XE#8378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8378
[Intel XE#9536]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9536
Build changes
-------------
* Linux: xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10 -> xe-pw-177030v2
IGT_9169: 9169
xe-6020-18bb5742e834aeb869af8b7262ce7e16ad9e1b10: 18bb5742e834aeb869af8b7262ce7e16ad9e1b10
xe-pw-177030v2: 177030v2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-177030v2/index.html
[-- Attachment #2: Type: text/html, Size: 20206 bytes --]
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [RFC PATCH] drm/xe/ggtt: Cut GGTT initialization from 900 ms to 37 ms
2026-10-28 4:50 [RFC PATCH] drm/xe/ggtt: Cut GGTT initialization from 900 ms to 37 ms Daniel Colascione
` (4 preceding siblings ...)
2026-10-29 2:06 ` ✗ Xe.CI.FULL: " Patchwork
@ 2026-10-29 15:16 ` Matthew Brost
2026-10-29 15:31 ` Matthew Brost
5 siblings, 1 reply; 8+ messages in thread
From: Matthew Brost @ 2026-10-29 15:16 UTC (permalink / raw)
To: Daniel Colascione; +Cc: intel-xe, Thomas Hellstrom, Rodrigo Vivi, dri-devel
On Tue, Oct 27, 2026 at 09:50:31PM -0700, Daniel Colascione wrote:
Thanks for this - I have wondered why when I probe Xe it takes a
noticable amount of time - I suspect this is why.
> We initialize the GGTT GPU page tables on startup. On my LNL, doing
> this one PTE at a time through the BAR takes about 900 ms and involves
> a million small writes.
>
> Use the GPU's copy engine to fill the PTEs in batches. We build
> MI_UPDATE_GTT commands in normal memory, then send them to the GPU for
> execution. This way, we avoid the per-PTE MMIO write and do the PTE fill
> in 36.77 ms, ~24x faster.
>
> The new path is enabled by default. xe.ggtt_init_gpu=0 uses the old
> CPU-driven path.
>
> LNL-only because I can test only LNL. Might it work elsewhere?
>
It should work anywhere.
> Signed-off-by: Daniel Colascione <dancol@dancol.org>
> ---
> drivers/gpu/drm/xe/instructions/xe_mi_commands.h | 2 +
> drivers/gpu/drm/xe/xe_ggtt.c | 128 +++++++++++++++++++++--
> drivers/gpu/drm/xe/xe_ggtt.h | 1 +
> drivers/gpu/drm/xe/xe_gt.c | 3 +-
> drivers/gpu/drm/xe/xe_module.c | 5 +
> drivers/gpu/drm/xe/xe_module.h | 1 +
> 6 files changed, 130 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
> index 835ef75bbeb1..04bd4225adef 100644
> --- a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
> +++ b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
> @@ -62,6 +62,8 @@
> #define MI_LRI_FORCE_POSTED REG_BIT(12)
> #define MI_LRI_LEN(x) (((x) & 0xff) + 1)
>
> +#define MI_UPDATE_GTT __MI_INSTR(0x23)
> +
> #define MI_STORE_REGISTER_MEM (__MI_INSTR(0x24) | XE_INSTR_NUM_DW(4))
> #define MI_SRM_USE_GGTT REG_BIT(22)
> #define MI_SRM_ADD_CS_OFFSET REG_BIT(19)
> diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
> index 773777afc68a..3737d085ae68 100644
> --- a/drivers/gpu/drm/xe/xe_ggtt.c
> +++ b/drivers/gpu/drm/xe/xe_ggtt.c
> @@ -15,20 +15,25 @@
> #include <drm/intel/i915_drm.h>
> #include <generated/xe_wa_oob.h>
>
> +#include "instructions/xe_mi_commands.h"
> #include "regs/xe_gt_regs.h"
> #include "regs/xe_gtt_defs.h"
> #include "regs/xe_regs.h"
> #include "xe_assert.h"
> +#include "xe_bb.h"
> #include "xe_bo.h"
> +#include "xe_exec_queue.h"
> #include "xe_gt.h"
> #include "xe_gt_printk.h"
> #include "xe_gt_types.h"
> #include "xe_log.h"
> #include "xe_map.h"
> #include "xe_mmio.h"
> +#include "xe_module.h"
> #include "xe_pat.h"
> #include "xe_pm.h"
> #include "xe_res_cursor.h"
> +#include "xe_sched_job.h"
> #include "xe_sriov.h"
> #include "xe_tile_printk.h"
> #include "xe_tile_sriov_vf.h"
> @@ -384,9 +389,9 @@ static void dev_fini_ggtt(void *arg)
> * @ggtt: the &xe_ggtt to be initialized
> *
> * It allows to create new mappings usable by the GuC.
> - * Mappings are not usable by the HW engines, as it doesn't have scratch nor
> - * initial clear done to it yet. That will happen in the regular, non-early
> - * GGTT initialization.
> + * HW engines may only access explicitly mapped bootstrap buffers until the
> + * remaining holes have been cleared. Normally xe_ggtt_init() does this;
> + * the GPU clear finishes this work in xe_ggtt_init_late().
> *
> * Return: 0 on success or a negative error code on failure.
> */
> @@ -456,18 +461,119 @@ ALLOW_ERROR_INJECTION(xe_ggtt_init_early, ERRNO); /* See xe_pci_probe() */
> static void xe_ggtt_invalidate(struct xe_ggtt *ggtt);
> static void xe_ggtt_invalidate_engine(struct xe_ggtt *ggtt);
>
> -static void xe_ggtt_initial_clear(struct xe_ggtt *ggtt)
> +static bool ggtt_use_gpu(struct xe_device *xe)
> {
> + return xe_modparam.ggtt_init_gpu && xe->info.platform == XE_LUNARLAKE;
Per below (last reply) - let's just turn this everywhere in platform
config.
> +}
> +
> +/*
> + * MI_UPDATE_GTT takes at most 511 inline PTEs (ACM PRM, Vol. 2a,
> + * pp. 1096-1097). Limit batches to 512K to fit the kernel batch pool.
> + */
> +#define GGTT_INIT_PTES_PER_PACKET 511
> +#define GGTT_INIT_BATCH_DWORDS (128 * (2 + 2 * GGTT_INIT_PTES_PER_PACKET))
> +
> +static int ggtt_clear_gpu(struct xe_exec_queue *q, struct xe_bb *bb,
> + u64 pte, u64 start, u64 end)
s/ggtt_clear_gpu/xe_ggtt_clear_gpu
> +{
> + while (start < end) {
> + struct xe_sched_job *job;
> + int err;
> +
> + bb->len = 0;
> + while (start < end && bb->len < GGTT_INIT_BATCH_DWORDS) {
> + u32 count = min_t(u64, (end - start) >> XE_PTE_SHIFT,
> + GGTT_INIT_PTES_PER_PACKET);
> +
> + bb->cs[bb->len++] = MI_UPDATE_GTT | (2 * count);
> + bb->cs[bb->len++] = start;
> + memset64((u64 *)&bb->cs[bb->len], pte, count);
> + bb->len += 2 * count;
> + start += (u64)count << XE_PTE_SHIFT;
> + }
> +
> + job = xe_bb_create_job(q, bb);
> + if (IS_ERR(job))
> + return PTR_ERR(job);
> +
> + xe_sched_job_arm(job);
> + xe_sched_job_get(job);
> + xe_sched_job_push(job);
> +
> + dma_fence_wait(&job->drm.s_fence->finished, false);
You can pipeline this function.
i.e., generate fences in a loop and only wait on the last one.
This is fairly common pattern, xe_svm_copy is an example of function
with loop which issues a bunch of jobs and only waits on the very last
fence.
> + err = dma_fence_get_status(&job->drm.s_fence->finished);
> + xe_sched_job_put(job);
> + if (err < 0)
> + return err;
> + }
> +
> + return 0;
> +}
> +
> +static int xe_ggtt_initial_clear(struct xe_ggtt *ggtt, struct xe_hw_engine *hwe)
> +{
> + struct xe_device *xe = tile_to_xe(ggtt->tile);
> + struct xe_exec_queue *q = NULL;
> + struct xe_bb *bb = NULL;
> struct drm_mm_node *hole;
> - u64 start, end;
> + u16 pat_index = xe_cache_pat_idx(xe, XE_CACHE_WB);
> + u64 start, end, pte = 0;
> + int err = 0;
> +
> + if (hwe) {
> + q = xe_exec_queue_create(xe, NULL, BIT(hwe->logical_instance), 1,
> + hwe, EXEC_QUEUE_FLAG_KERNEL, 0);
Can we use migration queue (xe_migrate.c)? We'd probably need a bit of
layering rework to allow another layer like GGTT to safely use this
queue but that seems better to keep a single isolated kernel queue.
> + if (IS_ERR(q))
> + return PTR_ERR(q);
> +
> + bb = xe_bb_new(hwe->gt, GGTT_INIT_BATCH_DWORDS, false);
> + if (IS_ERR(bb)) {
> + err = PTR_ERR(bb);
> + goto put_queue;
> + }
> + }
>
> - /* Display may have allocated inside ggtt, so be careful with clearing here */
> + if (ggtt->scratch)
> + pte = xe_bo_addr(ggtt->scratch, 0, XE_PAGE_SIZE) |
> + ggtt->pt_ops->pte_encode_flags(ggtt->scratch, pat_index);
> +
> + /* Preserve boot mappings and exclude allocator changes until completion. */
> mutex_lock(&ggtt->lock);
CI and Sashiko correctly complain that 'ggtt->lock' is tainted with
reclaim and ggtt_clear_gpu will be a malloc for the GPU job.
I'm actually questioning if this taint is actually valid. afiak we never
shrink or evict anything GGTT mapped (i.e., that memory is always
pinned). So I think we can just drop the taint - I'd do this in a
standalone patch.
> - drm_mm_for_each_hole(hole, &ggtt->mm, start, end)
> - xe_ggtt_clear(ggtt, ggtt->start + start, end - start);
> + drm_mm_for_each_hole(hole, &ggtt->mm, start, end) {
> + if (q)
> + err = ggtt_clear_gpu(q, bb, pte, ggtt->start + start, ggtt->start + end);
> + else
> + xe_ggtt_clear(ggtt, ggtt->start + start, end - start);
> + if (err)
> + goto unlock;
> + }
>
> xe_ggtt_invalidate(ggtt);
> +unlock:
> mutex_unlock(&ggtt->lock);
> + xe_bb_free(bb, NULL);
> +put_queue:
> + if (q)
> + xe_exec_queue_put(q);
> + return err;
> +}
> +
> +/**
> + * xe_ggtt_init_late - Finish deferred GGTT initialization after GuC startup
> + * @ggtt: GGTT to initialize
> + *
> + * All default contexts must be recorded before waiting for a GPU clear with
> + * the GGTT mutex held, so reset recovery need not allocate context mappings.
> + *
> + * Return: 0 on success or a negative error code on failure.
> + */
> +int xe_ggtt_init_late(struct xe_ggtt *ggtt)
> +{
> + if (!ggtt_use_gpu(tile_to_xe(ggtt->tile)))
> + return 0;
> +
> + return xe_ggtt_initial_clear(ggtt, xe_gt_hw_engine(ggtt->tile->primary_gt,
> + XE_ENGINE_CLASS_COPY, 0, false));
> }
>
> static void ggtt_node_fini(struct xe_ggtt_node *node)
> @@ -536,6 +642,9 @@ void xe_ggtt_node_remove(struct xe_ggtt_node *node, bool invalidate)
> * xe_ggtt_init - Regular non-early GGTT initialization
> * @ggtt: the &xe_ggtt to be initialized
> *
> + * Allocate the scratch page if needed and clear unused entries, or defer
> + * the clear to xe_ggtt_init_late() when GPU initialization is enabled.
> + *
> * Return: 0 on success or a negative error code on failure.
> */
> int xe_ggtt_init(struct xe_ggtt *ggtt)
> @@ -572,7 +681,8 @@ int xe_ggtt_init(struct xe_ggtt *ggtt)
> xe_bo_size(ggtt->scratch));
> }
>
> - xe_ggtt_initial_clear(ggtt);
> + if (!ggtt_use_gpu(xe))
> + xe_ggtt_initial_clear(ggtt, NULL);
>
> return devm_add_action_or_reset(xe->drm.dev, ggtt_fini, ggtt);
> err:
> diff --git a/drivers/gpu/drm/xe/xe_ggtt.h b/drivers/gpu/drm/xe/xe_ggtt.h
> index c864cc975a69..cae8600d7142 100644
> --- a/drivers/gpu/drm/xe/xe_ggtt.h
> +++ b/drivers/gpu/drm/xe/xe_ggtt.h
> @@ -17,6 +17,7 @@ struct xe_ggtt *xe_ggtt_alloc(struct xe_tile *tile);
> int xe_ggtt_init_early(struct xe_ggtt *ggtt);
> int xe_ggtt_init_kunit(struct xe_ggtt *ggtt, u32 reserved, u32 size);
> int xe_ggtt_init(struct xe_ggtt *ggtt);
> +int xe_ggtt_init_late(struct xe_ggtt *ggtt);
>
> void xe_ggtt_shift_nodes(struct xe_ggtt *ggtt, u64 new_base);
> u64 xe_ggtt_start(struct xe_ggtt *ggtt);
> diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
> index 45fb074812a2..d1c14a02de66 100644
> --- a/drivers/gpu/drm/xe/xe_gt.c
> +++ b/drivers/gpu/drm/xe/xe_gt.c
> @@ -686,7 +686,8 @@ static int gt_init_with_all_forcewake(struct xe_gt *gt)
> if (err)
> return err;
>
> - return 0;
> + return xe_gt_is_main_type(gt) ?
> + xe_ggtt_init_late(gt_to_tile(gt)->mem.ggtt) : 0;
> }
>
> static void xe_gt_fini(void *arg)
> diff --git a/drivers/gpu/drm/xe/xe_module.c b/drivers/gpu/drm/xe/xe_module.c
> index 897724cb5cfb..44cc0107cf53 100644
> --- a/drivers/gpu/drm/xe/xe_module.c
> +++ b/drivers/gpu/drm/xe/xe_module.c
> @@ -22,6 +22,7 @@
> #include "xe_sched_job.h"
>
> struct xe_modparam xe_modparam = {
> + .ggtt_init_gpu = true,
I'd make this platform param in xe_pci.c and turn it on for every
platform which supports the required GPU instructions (likely every Xe
supported platform). We can let this soak in for a couple months in our
CI before getting into a kernel release to ensure everything is
functional and then perhaps rip out the non-GPU clear code.
Matt
> .probe_display = XE_DEFAULT_PROBE_DISPLAY,
> .guc_log_level = XE_DEFAULT_GUC_LOG_LEVEL,
> .force_probe = XE_DEFAULT_FORCE_PROBE,
> @@ -34,6 +35,10 @@ struct xe_modparam xe_modparam = {
> /* the rest are 0 by default */
> };
>
> +module_param_named(ggtt_init_gpu, xe_modparam.ggtt_init_gpu, bool, 0444);
> +MODULE_PARM_DESC(ggtt_init_gpu,
> + "GPU GGTT initialization on Lunar Lake (default: true)");
> +
> module_param_named(svm_notifier_size, xe_modparam.svm_notifier_size, uint, 0600);
> MODULE_PARM_DESC(svm_notifier_size, "Set the svm notifier size in MiB, must be power of 2 "
> "[default=" __stringify(XE_DEFAULT_SVM_NOTIFIER_SIZE) "]");
> diff --git a/drivers/gpu/drm/xe/xe_module.h b/drivers/gpu/drm/xe/xe_module.h
> index 6272d9e41207..8aa91822c35c 100644
> --- a/drivers/gpu/drm/xe/xe_module.h
> +++ b/drivers/gpu/drm/xe/xe_module.h
> @@ -12,6 +12,7 @@ struct work_struct;
>
> /* Module modprobe variables */
> struct xe_modparam {
> + bool ggtt_init_gpu;
> bool probe_display;
> int force_vram_bar_size;
> int guc_log_level;
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [RFC PATCH] drm/xe/ggtt: Cut GGTT initialization from 900 ms to 37 ms
2026-10-29 15:16 ` [RFC PATCH] drm/xe/ggtt: Cut GGTT initialization from 900 ms to 37 ms Matthew Brost
@ 2026-10-29 15:31 ` Matthew Brost
0 siblings, 0 replies; 8+ messages in thread
From: Matthew Brost @ 2026-10-29 15:31 UTC (permalink / raw)
To: Daniel Colascione; +Cc: intel-xe, Thomas Hellstrom, Rodrigo Vivi, dri-devel
On Thu, Oct 29, 2026 at 08:16:44AM -0700, Matthew Brost wrote:
Sorry double reply, just had another thought...
> On Tue, Oct 27, 2026 at 09:50:31PM -0700, Daniel Colascione wrote:
>
> Thanks for this - I have wondered why when I probe Xe it takes a
> noticable amount of time - I suspect this is why.
>
> > We initialize the GGTT GPU page tables on startup. On my LNL, doing
> > this one PTE at a time through the BAR takes about 900 ms and involves
> > a million small writes.
> >
> > Use the GPU's copy engine to fill the PTEs in batches. We build
> > MI_UPDATE_GTT commands in normal memory, then send them to the GPU for
> > execution. This way, we avoid the per-PTE MMIO write and do the PTE fill
> > in 36.77 ms, ~24x faster.
> >
> > The new path is enabled by default. xe.ggtt_init_gpu=0 uses the old
> > CPU-driven path.
> >
> > LNL-only because I can test only LNL. Might it work elsewhere?
> >
>
> It should work anywhere.
>
> > Signed-off-by: Daniel Colascione <dancol@dancol.org>
> > ---
> > drivers/gpu/drm/xe/instructions/xe_mi_commands.h | 2 +
> > drivers/gpu/drm/xe/xe_ggtt.c | 128 +++++++++++++++++++++--
> > drivers/gpu/drm/xe/xe_ggtt.h | 1 +
> > drivers/gpu/drm/xe/xe_gt.c | 3 +-
> > drivers/gpu/drm/xe/xe_module.c | 5 +
> > drivers/gpu/drm/xe/xe_module.h | 1 +
> > 6 files changed, 130 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
> > index 835ef75bbeb1..04bd4225adef 100644
> > --- a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
> > +++ b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
> > @@ -62,6 +62,8 @@
> > #define MI_LRI_FORCE_POSTED REG_BIT(12)
> > #define MI_LRI_LEN(x) (((x) & 0xff) + 1)
> >
> > +#define MI_UPDATE_GTT __MI_INSTR(0x23)
> > +
> > #define MI_STORE_REGISTER_MEM (__MI_INSTR(0x24) | XE_INSTR_NUM_DW(4))
> > #define MI_SRM_USE_GGTT REG_BIT(22)
> > #define MI_SRM_ADD_CS_OFFSET REG_BIT(19)
> > diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
> > index 773777afc68a..3737d085ae68 100644
> > --- a/drivers/gpu/drm/xe/xe_ggtt.c
> > +++ b/drivers/gpu/drm/xe/xe_ggtt.c
> > @@ -15,20 +15,25 @@
> > #include <drm/intel/i915_drm.h>
> > #include <generated/xe_wa_oob.h>
> >
> > +#include "instructions/xe_mi_commands.h"
> > #include "regs/xe_gt_regs.h"
> > #include "regs/xe_gtt_defs.h"
> > #include "regs/xe_regs.h"
> > #include "xe_assert.h"
> > +#include "xe_bb.h"
> > #include "xe_bo.h"
> > +#include "xe_exec_queue.h"
> > #include "xe_gt.h"
> > #include "xe_gt_printk.h"
> > #include "xe_gt_types.h"
> > #include "xe_log.h"
> > #include "xe_map.h"
> > #include "xe_mmio.h"
> > +#include "xe_module.h"
> > #include "xe_pat.h"
> > #include "xe_pm.h"
> > #include "xe_res_cursor.h"
> > +#include "xe_sched_job.h"
> > #include "xe_sriov.h"
> > #include "xe_tile_printk.h"
> > #include "xe_tile_sriov_vf.h"
> > @@ -384,9 +389,9 @@ static void dev_fini_ggtt(void *arg)
> > * @ggtt: the &xe_ggtt to be initialized
> > *
> > * It allows to create new mappings usable by the GuC.
> > - * Mappings are not usable by the HW engines, as it doesn't have scratch nor
> > - * initial clear done to it yet. That will happen in the regular, non-early
> > - * GGTT initialization.
> > + * HW engines may only access explicitly mapped bootstrap buffers until the
> > + * remaining holes have been cleared. Normally xe_ggtt_init() does this;
> > + * the GPU clear finishes this work in xe_ggtt_init_late().
> > *
> > * Return: 0 on success or a negative error code on failure.
> > */
> > @@ -456,18 +461,119 @@ ALLOW_ERROR_INJECTION(xe_ggtt_init_early, ERRNO); /* See xe_pci_probe() */
> > static void xe_ggtt_invalidate(struct xe_ggtt *ggtt);
> > static void xe_ggtt_invalidate_engine(struct xe_ggtt *ggtt);
> >
> > -static void xe_ggtt_initial_clear(struct xe_ggtt *ggtt)
> > +static bool ggtt_use_gpu(struct xe_device *xe)
> > {
> > + return xe_modparam.ggtt_init_gpu && xe->info.platform == XE_LUNARLAKE;
>
> Per below (last reply) - let's just turn this everywhere in platform
> config.
>
> > +}
> > +
> > +/*
> > + * MI_UPDATE_GTT takes at most 511 inline PTEs (ACM PRM, Vol. 2a,
> > + * pp. 1096-1097). Limit batches to 512K to fit the kernel batch pool.
> > + */
> > +#define GGTT_INIT_PTES_PER_PACKET 511
> > +#define GGTT_INIT_BATCH_DWORDS (128 * (2 + 2 * GGTT_INIT_PTES_PER_PACKET))
> > +
> > +static int ggtt_clear_gpu(struct xe_exec_queue *q, struct xe_bb *bb,
> > + u64 pte, u64 start, u64 end)
>
> s/ggtt_clear_gpu/xe_ggtt_clear_gpu
>
> > +{
> > + while (start < end) {
> > + struct xe_sched_job *job;
> > + int err;
> > +
> > + bb->len = 0;
> > + while (start < end && bb->len < GGTT_INIT_BATCH_DWORDS) {
> > + u32 count = min_t(u64, (end - start) >> XE_PTE_SHIFT,
> > + GGTT_INIT_PTES_PER_PACKET);
> > +
> > + bb->cs[bb->len++] = MI_UPDATE_GTT | (2 * count);
> > + bb->cs[bb->len++] = start;
> > + memset64((u64 *)&bb->cs[bb->len], pte, count);
> > + bb->len += 2 * count;
> > + start += (u64)count << XE_PTE_SHIFT;
> > + }
> > +
> > + job = xe_bb_create_job(q, bb);
> > + if (IS_ERR(job))
> > + return PTR_ERR(job);
> > +
> > + xe_sched_job_arm(job);
> > + xe_sched_job_get(job);
> > + xe_sched_job_push(job);
> > +
> > + dma_fence_wait(&job->drm.s_fence->finished, false);
>
> You can pipeline this function.
>
> i.e., generate fences in a loop and only wait on the last one.
>
> This is fairly common pattern, xe_svm_copy is an example of function
> with loop which issues a bunch of jobs and only waits on the very last
> fence.
>
> > + err = dma_fence_get_status(&job->drm.s_fence->finished);
> > + xe_sched_job_put(job);
> > + if (err < 0)
> > + return err;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int xe_ggtt_initial_clear(struct xe_ggtt *ggtt, struct xe_hw_engine *hwe)
> > +{
> > + struct xe_device *xe = tile_to_xe(ggtt->tile);
> > + struct xe_exec_queue *q = NULL;
> > + struct xe_bb *bb = NULL;
> > struct drm_mm_node *hole;
> > - u64 start, end;
> > + u16 pat_index = xe_cache_pat_idx(xe, XE_CACHE_WB);
> > + u64 start, end, pte = 0;
> > + int err = 0;
> > +
> > + if (hwe) {
> > + q = xe_exec_queue_create(xe, NULL, BIT(hwe->logical_instance), 1,
> > + hwe, EXEC_QUEUE_FLAG_KERNEL, 0);
>
> Can we use migration queue (xe_migrate.c)? We'd probably need a bit of
> layering rework to allow another layer like GGTT to safely use this
> queue but that seems better to keep a single isolated kernel queue.
>
> > + if (IS_ERR(q))
> > + return PTR_ERR(q);
> > +
> > + bb = xe_bb_new(hwe->gt, GGTT_INIT_BATCH_DWORDS, false);
> > + if (IS_ERR(bb)) {
> > + err = PTR_ERR(bb);
> > + goto put_queue;
> > + }
> > + }
> >
> > - /* Display may have allocated inside ggtt, so be careful with clearing here */
> > + if (ggtt->scratch)
> > + pte = xe_bo_addr(ggtt->scratch, 0, XE_PAGE_SIZE) |
> > + ggtt->pt_ops->pte_encode_flags(ggtt->scratch, pat_index);
> > +
> > + /* Preserve boot mappings and exclude allocator changes until completion. */
> > mutex_lock(&ggtt->lock);
>
> CI and Sashiko correctly complain that 'ggtt->lock' is tainted with
> reclaim and ggtt_clear_gpu will be a malloc for the GPU job.
>
> I'm actually questioning if this taint is actually valid. afiak we never
> shrink or evict anything GGTT mapped (i.e., that memory is always
> pinned). So I think we can just drop the taint - I'd do this in a
> standalone patch.
>
> > - drm_mm_for_each_hole(hole, &ggtt->mm, start, end)
> > - xe_ggtt_clear(ggtt, ggtt->start + start, end - start);
> > + drm_mm_for_each_hole(hole, &ggtt->mm, start, end) {
> > + if (q)
> > + err = ggtt_clear_gpu(q, bb, pte, ggtt->start + start, ggtt->start + end);
> > + else
> > + xe_ggtt_clear(ggtt, ggtt->start + start, end - start);
> > + if (err)
> > + goto unlock;
> > + }
> >
> > xe_ggtt_invalidate(ggtt);
> > +unlock:
> > mutex_unlock(&ggtt->lock);
> > + xe_bb_free(bb, NULL);
> > +put_queue:
> > + if (q)
> > + xe_exec_queue_put(q);
> > + return err;
> > +}
> > +
> > +/**
> > + * xe_ggtt_init_late - Finish deferred GGTT initialization after GuC startup
> > + * @ggtt: GGTT to initialize
> > + *
> > + * All default contexts must be recorded before waiting for a GPU clear with
> > + * the GGTT mutex held, so reset recovery need not allocate context mappings.
> > + *
> > + * Return: 0 on success or a negative error code on failure.
> > + */
> > +int xe_ggtt_init_late(struct xe_ggtt *ggtt)
> > +{
> > + if (!ggtt_use_gpu(tile_to_xe(ggtt->tile)))
> > + return 0;
> > +
> > + return xe_ggtt_initial_clear(ggtt, xe_gt_hw_engine(ggtt->tile->primary_gt,
> > + XE_ENGINE_CLASS_COPY, 0, false));
> > }
> >
> > static void ggtt_node_fini(struct xe_ggtt_node *node)
> > @@ -536,6 +642,9 @@ void xe_ggtt_node_remove(struct xe_ggtt_node *node, bool invalidate)
> > * xe_ggtt_init - Regular non-early GGTT initialization
> > * @ggtt: the &xe_ggtt to be initialized
> > *
> > + * Allocate the scratch page if needed and clear unused entries, or defer
> > + * the clear to xe_ggtt_init_late() when GPU initialization is enabled.
> > + *
> > * Return: 0 on success or a negative error code on failure.
> > */
> > int xe_ggtt_init(struct xe_ggtt *ggtt)
> > @@ -572,7 +681,8 @@ int xe_ggtt_init(struct xe_ggtt *ggtt)
> > xe_bo_size(ggtt->scratch));
> > }
> >
> > - xe_ggtt_initial_clear(ggtt);
> > + if (!ggtt_use_gpu(xe))
> > + xe_ggtt_initial_clear(ggtt, NULL);
Hmm, so this defers GGTT clears to after we use GGTT memory for queues /
jobs.
The fact this works points to GGTT scratch most likely not actually
being needed but that is pretty hard to reason 100% correctly.
I wonder if a better solution is completely drop the GGTT clear and BO
which sets XE_BO_FLAG_GGTT just allocates guard page at the end (again
with a config to enable this which is on by default until we can reason
this isn't needed).
A lot to take in here. Let us know if you want to continue driving this,
or I can try to find an engineer at Intel to own it. A reduction from
900 ms to 37 ms is a compelling result, and this clearly needs to be
reworked.
Matt
> >
> > return devm_add_action_or_reset(xe->drm.dev, ggtt_fini, ggtt);
> > err:
> > diff --git a/drivers/gpu/drm/xe/xe_ggtt.h b/drivers/gpu/drm/xe/xe_ggtt.h
> > index c864cc975a69..cae8600d7142 100644
> > --- a/drivers/gpu/drm/xe/xe_ggtt.h
> > +++ b/drivers/gpu/drm/xe/xe_ggtt.h
> > @@ -17,6 +17,7 @@ struct xe_ggtt *xe_ggtt_alloc(struct xe_tile *tile);
> > int xe_ggtt_init_early(struct xe_ggtt *ggtt);
> > int xe_ggtt_init_kunit(struct xe_ggtt *ggtt, u32 reserved, u32 size);
> > int xe_ggtt_init(struct xe_ggtt *ggtt);
> > +int xe_ggtt_init_late(struct xe_ggtt *ggtt);
> >
> > void xe_ggtt_shift_nodes(struct xe_ggtt *ggtt, u64 new_base);
> > u64 xe_ggtt_start(struct xe_ggtt *ggtt);
> > diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
> > index 45fb074812a2..d1c14a02de66 100644
> > --- a/drivers/gpu/drm/xe/xe_gt.c
> > +++ b/drivers/gpu/drm/xe/xe_gt.c
> > @@ -686,7 +686,8 @@ static int gt_init_with_all_forcewake(struct xe_gt *gt)
> > if (err)
> > return err;
> >
> > - return 0;
> > + return xe_gt_is_main_type(gt) ?
> > + xe_ggtt_init_late(gt_to_tile(gt)->mem.ggtt) : 0;
> > }
> >
> > static void xe_gt_fini(void *arg)
> > diff --git a/drivers/gpu/drm/xe/xe_module.c b/drivers/gpu/drm/xe/xe_module.c
> > index 897724cb5cfb..44cc0107cf53 100644
> > --- a/drivers/gpu/drm/xe/xe_module.c
> > +++ b/drivers/gpu/drm/xe/xe_module.c
> > @@ -22,6 +22,7 @@
> > #include "xe_sched_job.h"
> >
> > struct xe_modparam xe_modparam = {
> > + .ggtt_init_gpu = true,
>
> I'd make this platform param in xe_pci.c and turn it on for every
> platform which supports the required GPU instructions (likely every Xe
> supported platform). We can let this soak in for a couple months in our
> CI before getting into a kernel release to ensure everything is
> functional and then perhaps rip out the non-GPU clear code.
>
> Matt
>
> > .probe_display = XE_DEFAULT_PROBE_DISPLAY,
> > .guc_log_level = XE_DEFAULT_GUC_LOG_LEVEL,
> > .force_probe = XE_DEFAULT_FORCE_PROBE,
> > @@ -34,6 +35,10 @@ struct xe_modparam xe_modparam = {
> > /* the rest are 0 by default */
> > };
> >
> > +module_param_named(ggtt_init_gpu, xe_modparam.ggtt_init_gpu, bool, 0444);
> > +MODULE_PARM_DESC(ggtt_init_gpu,
> > + "GPU GGTT initialization on Lunar Lake (default: true)");
> > +
> > module_param_named(svm_notifier_size, xe_modparam.svm_notifier_size, uint, 0600);
> > MODULE_PARM_DESC(svm_notifier_size, "Set the svm notifier size in MiB, must be power of 2 "
> > "[default=" __stringify(XE_DEFAULT_SVM_NOTIFIER_SIZE) "]");
> > diff --git a/drivers/gpu/drm/xe/xe_module.h b/drivers/gpu/drm/xe/xe_module.h
> > index 6272d9e41207..8aa91822c35c 100644
> > --- a/drivers/gpu/drm/xe/xe_module.h
> > +++ b/drivers/gpu/drm/xe/xe_module.h
> > @@ -12,6 +12,7 @@ struct work_struct;
> >
> > /* Module modprobe variables */
> > struct xe_modparam {
> > + bool ggtt_init_gpu;
> > bool probe_display;
> > int force_vram_bar_size;
> > int guc_log_level;
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2026-10-29 15:32 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-10-28 4:50 [RFC PATCH] drm/xe/ggtt: Cut GGTT initialization from 900 ms to 37 ms Daniel Colascione
2026-10-28 13:09 ` ✗ LGCI.VerificationFailed: failure for " Patchwork
2026-10-28 13:23 ` [RFC PATCH] " sashiko-bot
2026-10-28 15:37 ` ✓ CI.KUnit: success for drm/xe/ggtt: Cut GGTT initialization from 900 ms to 37 ms (rev2) Patchwork
2026-10-28 16:11 ` ✗ Xe.CI.BAT: failure " Patchwork
2026-10-29 2:06 ` ✗ Xe.CI.FULL: " Patchwork
2026-10-29 15:16 ` [RFC PATCH] drm/xe/ggtt: Cut GGTT initialization from 900 ms to 37 ms Matthew Brost
2026-10-29 15:31 ` Matthew Brost
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