From: Lorenzo Pieralisi <lpieralisi@kernel.org>
To: Sascha Bischoff <sascha.bischoff@arm.com>
Cc: Marc Zyngier <maz@kernel.org>, Thomas Gleixner <tglx@kernel.org>,
Radu Rendec <radu@rendec.net>,
Timothy Hayes <timothy.hayes@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Jonathan Cameron <jic23@kernel.org>,
"Rafael J. Wysocki" <rafael.j.wysocki@intel.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 01/10] irqchip/gic-v5: Reject SPIs not backed by an IRS
Date: Mon, 2 Nov 2026 14:50:30 +0100 [thread overview]
Message-ID: <auiVJuDPZr-ietKa@red-moon> (raw)
In-Reply-To: <20261102-host_gicv5_fixes-v1-1-743b61626fc5@arm.com>
On Mon, Nov 02, 2026 at 01:32:54PM +0000, Sascha Bischoff wrote:
> It is possible to build a multi-IRS GICv5 system where there are gaps
> in the global SPI range that are not backed by any IRS. In the current
> incarnation, this results in dereferencing a null pointer.
>
> Reject cases where the firmware attempts to use those SPIs during IRQ
> allocation by catching the case where there is no chip_data associated
> with the irq (meaning that there is no IRS to back it). Spit out a
> warning about broken firmware when this is encountered as it shouldn't
> be using non-existent SPIs in the first place.
>
> Fixes: 5cb1b6dab2def ("irqchip/gic-v5: Add GICv5 IRS/SPI support")
> Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
> ---
> drivers/irqchip/irq-gic-v5.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
Acked-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
> diff --git a/drivers/irqchip/irq-gic-v5.c b/drivers/irqchip/irq-gic-v5.c
> index 8c0303af71e7d..f3cce2bd28cc3 100644
> --- a/drivers/irqchip/irq-gic-v5.c
> +++ b/drivers/irqchip/irq-gic-v5.c
> @@ -727,6 +727,15 @@ static int gicv5_irq_spi_domain_alloc(struct irq_domain *domain, unsigned int vi
>
> irqd = irq_desc_get_irq_data(irq_to_desc(virq));
> chip_data = gicv5_irs_lookup_by_spi_id(hwirq);
> + /*
> + * The global SPI range may contain IDs not covered by any IRS, i.e., it
> + * may have gaps, in which case there is no IRS to back the SPI. Catch
> + * broken firmware trying to use any of those SPIs.
> + */
> + if (!chip_data) {
> + pr_warn("Firmware bug! Unimplemented SPI (0x%lx)!\n", hwirq);
> + return -EINVAL;
> + }
>
> irq_domain_set_info(domain, virq, hwirq, &gicv5_spi_irq_chip, chip_data,
> handle_fasteoi_irq, NULL, NULL);
>
> --
> 2.34.1
>
next prev parent reply other threads:[~2026-11-02 13:50 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-02 13:32 [PATCH 00/10] irqchip/gic-v5: Fix misc IRS and ITS host driver issues Sascha Bischoff
2026-11-02 13:32 ` [PATCH 01/10] irqchip/gic-v5: Reject SPIs not backed by an IRS Sascha Bischoff
2026-11-02 13:50 ` Lorenzo Pieralisi [this message]
2026-11-02 13:32 ` [PATCH 02/10] irqchip/gic-v5: Only set IRS DPS when 1ofN routing is supported Sascha Bischoff
2026-11-02 14:00 ` Lorenzo Pieralisi
2026-11-02 13:32 ` [PATCH 03/10] irqchip/gic-v5: Serialise IRS synchronisation requests Sascha Bischoff
2026-11-03 9:12 ` Lorenzo Pieralisi
2026-11-04 17:05 ` Sascha Bischoff
2026-11-02 13:32 ` [PATCH 04/10] irqchip/gic-v5: Serialise ITS invalidation commands Sascha Bischoff
2026-11-02 15:56 ` Lorenzo Pieralisi
2026-11-04 17:35 ` Sascha Bischoff
2026-11-02 13:32 ` [PATCH 05/10] irqchip/gic-v5: Use linear DT and ITT when L2 covers all IDs Sascha Bischoff
2026-11-03 14:58 ` Lorenzo Pieralisi
2026-11-02 13:32 ` [PATCH 06/10] irqchip/gic-v5: Honour ACPI ITS noncoherent flag Sascha Bischoff
2026-11-02 14:13 ` Lorenzo Pieralisi
2026-11-02 13:33 ` [PATCH 07/10] irqchip/gic-v5: Use firmware node name in ITS warning Sascha Bischoff
2026-11-02 14:21 ` Lorenzo Pieralisi
2026-11-02 13:33 ` [PATCH 08/10] irqchip/gic-v5: Invalidate ITS device cache before freeing ITT Sascha Bischoff
2026-11-02 15:22 ` Lorenzo Pieralisi
2026-11-02 13:33 ` [PATCH 09/10] irqchip/gic-v5: Clean the allocated linear device table size Sascha Bischoff
2026-11-02 14:46 ` Lorenzo Pieralisi
2026-11-04 17:21 ` Sascha Bischoff
2026-11-02 13:33 ` [PATCH 10/10] irqchip/gic-v5: Release ITS MMIO region on DT probe failure Sascha Bischoff
2026-11-02 14:54 ` Lorenzo Pieralisi
2026-11-04 17:37 ` Sascha Bischoff
2026-11-03 14:59 ` [PATCH 00/10] irqchip/gic-v5: Fix misc IRS and ITS host driver issues Lorenzo Pieralisi
2026-11-04 17:40 ` Sascha Bischoff
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=auiVJuDPZr-ietKa@red-moon \
--to=lpieralisi@kernel.org \
--cc=catalin.marinas@arm.com \
--cc=jic23@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=maz@kernel.org \
--cc=radu@rendec.net \
--cc=rafael.j.wysocki@intel.com \
--cc=sascha.bischoff@arm.com \
--cc=tglx@kernel.org \
--cc=timothy.hayes@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.