From: Chen Yu <yu.c.chen@intel.com>
To: Tony Luck <tony.luck@intel.com>
Cc: Fenghua Yu <fenghuay@nvidia.com>,
Reinette Chatre <reinette.chatre@intel.com>,
Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>,
Peter Newman <peternewman@google.com>,
James Morse <james.morse@arm.com>,
Babu Moger <babu.moger@amd.com>,
"Drew Fustini" <dfustini@baylibre.com>,
Dave Martin <Dave.Martin@arm.com>, <x86@kernel.org>,
<linux-kernel@vger.kernel.org>, <patches@lists.linux.dev>
Subject: Re: [RFC PATCH 6/8] arm,x86,fs/resctrl: Prepare for asymmetric caches
Date: Tue, 3 Nov 2026 23:31:14 +0800 [thread overview]
Message-ID: <aun+Qt5iTECdwogN@chenyu-dev> (raw)
In-Reply-To: <20261026215718.16810-7-tony.luck@intel.com>
On Mon, Oct 26, 2026 at 02:57:16PM -0700, Tony Luck wrote:
> Each struct resctrl_ctrl carries a struct resctrl_ctrl_bitmap that describes
> properties (cbm_len, min_cbm_bits, shareable_bits, flags) shared by every
> control domain using that control. This assumes all domains of a control are
> symmetric. Future asymmetric systems may have control domains with differing
> bitmap properties, in particular a @cbm_len that varies by cache instance.
>
> Add a field to the rdt_ctrl_domain structure to store per-domain cache
> bitmap lengths.
>
> Update code that reads cbm_len to use the per-domain copy instead of the
> resctrl_ctrl copy, so that domain-specific values will be picked up when
> asymmetric domains are enumerated.
>
> +static void rdt_sync_ctrl_bitmap(struct rdt_resource *r, struct rdt_ctrl_domain *d)
> +{
> + struct resctrl_ctrl *ctrl;
> +
> + for_each_resource_ctrl(ctrl, r) {
maybe we can let rdt_sync_ctrl_bitmap() receives the resctrl_ctrl from
domain_add_cpu_ctrl() then we don't need to iterate the controllers under
resource?
rdt_sync_ctrl_bitmap(r, d, ctrl);
thanks,
Chenyu
> + if (ctrl->type != RESCTRL_CTRL_BITMAP)
> + continue;
> + d->cbm_len = ctrl->bitmap.cbm_len;
> + break;
> + }
> +}
next prev parent reply other threads:[~2026-11-03 15:42 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-26 21:57 [RFC PATCH 0/8] arm,x86,fs/resctrl: Support asymmetric L2 cache allocation Tony Luck
2026-10-26 21:57 ` [RFC PATCH 1/8] fs/resctrl: Change UI of "max" file (merge back into earlier patches) Tony Luck
2026-10-26 21:57 ` [RFC PATCH 2/8] x86/resctrl: Add L2CAT quirk for Intel Panther Lake Tony Luck
2026-10-26 21:57 ` [RFC PATCH 3/8] x86/cpuid: Add and use defines for Intel RDT enumeration leaves Tony Luck
2026-10-26 21:57 ` [RFC PATCH 4/8] x86/resctrl: Add X86_FEATURE bits for asymmetric L2 Tony Luck
2026-10-26 21:57 ` [RFC PATCH 5/8] x86/resctrl: Refactor rdt_get_cache_alloc_cfg() Tony Luck
2026-10-26 21:57 ` [RFC PATCH 6/8] arm,x86,fs/resctrl: Prepare for asymmetric caches Tony Luck
2026-11-03 15:31 ` Chen Yu [this message]
2026-11-03 18:23 ` Luck, Tony
2026-10-26 21:57 ` [RFC PATCH 7/8] x86/resctrl: Check for and enable asymmetric L2 cache allocation Tony Luck
2026-10-26 21:57 ` [RFC PATCH 8/8] fs/resctrl: Suppress creation of cbm_mask info file on asymmetric systems Tony Luck
2026-10-26 22:30 ` [RFC PATCH 0/8] arm,x86,fs/resctrl: Support asymmetric L2 cache allocation Reinette Chatre
2026-10-27 17:41 ` Luck, Tony
2026-10-27 18:30 ` Reinette Chatre
2026-11-03 16:31 ` Chen Yu
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