From: Frank Li <Frank.li@oss.nxp.com>
To: Jelly Jia <Jelly.Jia@cixtech.com>
Cc: vkoul@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, robin.murphy@arm.com, sboyd@kernel.org,
bmasney+clk@redhat.com, jbrunet+clk@baylibre.com,
devicetree@vger.kernel.org, Frank.Li@kernel.org,
cix-kernel-upstream@cixtech.com, dmaengine@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
joakim.zhang@cixtech.com
Subject: Re: [PATCH v2 4/5] dmaengine: arm-dma350: Honour dma-channel-mask
Date: Wed, 4 Nov 2026 13:44:18 -0600 [thread overview]
Message-ID: <auuLEgmZFGJ0Ol0g@SMW015318> (raw)
In-Reply-To: <20261104124437.296753-5-Jelly.Jia@cixtech.com>
On Wed, Nov 04, 2026 at 08:44:36PM +0800, Jelly Jia wrote:
> DMA-350 channels may be reserved for firmware or another processor.
> Read the optional dma-channel-mask property and register only the channels
> whose bits are set. If the property is absent, preserve the existing
> behaviour and expose every hardware channel.
>
> Skip masked channels before accessing their channel registers or
> initializing their interrupts and virt-dma state. This avoids clearing
> or configuring channels reserved for firmware or another processor.
>
> Signed-off-by: Jelly Jia <Jelly.Jia@cixtech.com>
> ---
> drivers/dma/arm-dma350.c | 20 +++++++++++++++++++-
> 1 file changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/dma/arm-dma350.c b/drivers/dma/arm-dma350.c
> index 2f22f8a0ab47..b24e569a1dd8 100644
> --- a/drivers/dma/arm-dma350.c
> +++ b/drivers/dma/arm-dma350.c
> @@ -1253,9 +1253,10 @@ static int d350_probe(struct platform_device *pdev)
> struct clk *clk;
> struct d350 *dmac;
> void __iomem *base;
> + u32 chan_mask = U32_MAX;
> u32 reg;
> int ret, nchan, dw, aw, r, p;
> - bool coherent, memset;
> + bool coherent, has_chan_mask, memset;
>
> clk = devm_clk_get_optional_enabled(dev, NULL);
> if (IS_ERR(clk))
> @@ -1328,6 +1329,19 @@ static int d350_probe(struct platform_device *pdev)
> dmac->dma.device_caps = d350_caps;
> INIT_LIST_HEAD(&dmac->dma.channels);
>
> + /*
> + * dma-channel-mask is optional. Firmware-reserved channels stay
> + * clear; if the property is absent, Linux may use every channel.
> + */
> + has_chan_mask = device_property_present(dev, "dma-channel-mask");
> + if (has_chan_mask) {
> + ret = device_property_read_u32(dev, "dma-channel-mask",
> + &chan_mask);
> + if (ret)
> + return dev_err_probe(dev, ret,
> + "failed to read dma-channel-mask\n");
> + }
> +
> reg = readl_relaxed(base + DMANSECCTRL + NSEC_CTRL);
> writel_relaxed(reg | INTREN_ANYCHINTR_EN,
> base + DMANSECCTRL + NSEC_CTRL);
> @@ -1337,6 +1351,10 @@ static int d350_probe(struct platform_device *pdev)
> for (int i = 0; i < nchan; i++) {
> struct d350_chan *dch = &dmac->channels[i];
>
> + if (has_chan_mask &&
> + (i >= 32 || !(chan_mask & BIT(i))))
> + continue;
> +
max nchan is 8 (in your cover letter), why need check i >= 8 here?
Frank
> dch->base = base + DMACH(i);
> writel_relaxed(CH_CMD_CLEAR, dch->base + CH_CMD);
>
> --
> 2.54.0
>
next prev parent reply other threads:[~2026-11-04 19:44 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-04 12:44 [PATCH v2 0/5] soc: cix: Add the Sky1 AUDSS DMA-350 interrupt path Jelly Jia
2026-11-04 12:44 ` [PATCH v2 1/5] dt-bindings: soc: cix: Describe the Sky1 AUDSS DMA IRQ controller Jelly Jia
2026-11-04 12:44 ` [PATCH v2 2/5] clk: cix: Handle Sky1 AUDSS DMA interrupt gates as an irqchip Jelly Jia
2026-11-04 12:44 ` [PATCH v2 3/5] dt-bindings: dma: arm,dma-350: Document dma-channel-mask Jelly Jia
2026-11-04 12:44 ` [PATCH v2 4/5] dmaengine: arm-dma350: Honour dma-channel-mask Jelly Jia
2026-11-04 19:44 ` Frank Li [this message]
2026-11-05 8:41 ` Jelly Jia
2026-11-04 12:44 ` [PATCH v2 5/5] arm64: dts: cix: Add the Sky1 AUDSS DMA-350 integration Jelly Jia
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