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From: Jelly Jia <Jelly.Jia@cixtech.com>
To: Frank Li <Frank.li@oss.nxp.com>
Cc: vkoul@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
	conor+dt@kernel.org, robin.murphy@arm.com, sboyd@kernel.org,
	bmasney+clk@redhat.com, jbrunet+clk@baylibre.com,
	devicetree@vger.kernel.org, Frank.Li@kernel.org,
	cix-kernel-upstream@cixtech.com, dmaengine@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
	joakim.zhang@cixtech.com
Subject: Re: [PATCH v2 4/5] dmaengine: arm-dma350: Honour dma-channel-mask
Date: Thu, 5 Nov 2026 16:41:50 +0800	[thread overview]
Message-ID: <auxBTkn7Z+Ssr05B@ubuntu> (raw)
In-Reply-To: <auuLEgmZFGJ0Ol0g@SMW015318>

Hi Frank,

> max nchan is 8 (in your cover letter), why need check i >= 8 here?

The i >= 32 check was intended to guard the single-u32 mask and avoid
out-of-range shifts on 32-bit builds. However, DMA-350 supports at most
eight channels, so the check is unnecessary. I've removed it locally
and will include the change in the next revision.

Best regards,
Jelly

  reply	other threads:[~2026-11-05  8:41 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-04 12:44 [PATCH v2 0/5] soc: cix: Add the Sky1 AUDSS DMA-350 interrupt path Jelly Jia
2026-11-04 12:44 ` [PATCH v2 1/5] dt-bindings: soc: cix: Describe the Sky1 AUDSS DMA IRQ controller Jelly Jia
2026-11-04 12:44 ` [PATCH v2 2/5] clk: cix: Handle Sky1 AUDSS DMA interrupt gates as an irqchip Jelly Jia
2026-11-04 12:44 ` [PATCH v2 3/5] dt-bindings: dma: arm,dma-350: Document dma-channel-mask Jelly Jia
2026-11-04 12:44 ` [PATCH v2 4/5] dmaengine: arm-dma350: Honour dma-channel-mask Jelly Jia
2026-11-04 19:44   ` Frank Li
2026-11-05  8:41     ` Jelly Jia [this message]
2026-11-04 12:44 ` [PATCH v2 5/5] arm64: dts: cix: Add the Sky1 AUDSS DMA-350 integration Jelly Jia

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