[PATCH v5 0/7] arm64: dts: renesas: Enable ISP and IVC on RZ/V2H EVK

[PATCH v5 0/7] arm64: dts: renesas: Enable ISP and IVC on RZ/V2H EVK

[Linus Walleij]

Describe the optional ISP DMA line-tick and IVC frame-start/frame-stop
interrupts. Add the RZ/V2H(P) IVC and Arm Mali-C55 ISP nodes, connect their
video endpoints, and enable both blocks on the RZ/V2H EVK.

Two additional RFC patches replace bulk clock and reset operations in
the Mali-C55 driver with explicit sequences using named handles. They
reproduce the driver call orders from the reporters' working DT swap
while keeping the clock and reset assignments unchanged.

The Device Tree does *not* guarantee any sequencing of resources,
so these sequences must be handled in code.

Clocks are enabled hclk, aclk, vclk and disabled in reverse order.
Resets are deasserted vresetn, aresetn, hresetn and asserted in reverse
order. These are driver-only experiments: the CPG power domain can
enable clocks in DT order before the callback, and IVC may already hold
shared resources active. The physical transition order is not guaranteed.
These RFC patches have not been tested on hardware.

After these patches, and enabling the right Linux drivers, we get
this in the console:
mali-c55 16080000.isp: Detected Mali-C55 ISP 9000043.31032022.0

This was done in order to enable booting mainline with mainline
device trees.

The patches were authored with the assistance of an LLM.

Signed-off-by: Linus Walleij <linusw@kernel.org>
---
Changes in v5:
- Add two RFC driver patches for explicit clock and reset sequencing.
- Match the call order from the reported DT swap using named handles.
- Link to v4: https://patch.msgid.link/20261012-mali-c55-renesas-dts-v4-0-c410e280bf2d@kernel.org

Changes in v4:
- Provide interrupt names in both bindings, their examples and SoC nodes.
- Use Renesas RZ/V2H interrupt numbers in the binding examples.
- Link to v3: https://patch.msgid.link/20260928-mali-c55-renesas-dts-v3-0-2cf7eb746ebb@kernel.org

Changes in v3:
- Correct the ISP video and register clock/reset mappings by swapping
  vclk/hclk and vresetn/hresetn.
- Add an optional ISP power-domain binding and attach the RZ/V2H ISP
  to the CPG power domain.
- Link to v2: https://patch.msgid.link/20260925-mali-c55-renesas-dts-v2-0-69f728a474a2@kernel.org

Changes in v2:
- Add separate IVC and ISP binding patches describing the optional IVC
  frame-start/frame-stop completion and ISP DMA line-tick IRQs.
  Show all six IRQs in the examples using consecutive mock numbers.
- Add the IVC frame-start/stop and ISP DMA line-tick interrupt lines
  using the confirmed SPI assignments, addressing Geert's IRQ review.
- Correct the IVC and ISP register sizes to 64 KiB and 512 KiB,
  respectively, as requested by Geert. GPV_VIDEO0 is a separate bus
  interconnect region.
- Compact the clock and reset properties and remove blank lines between
  properties, following Geert's review.
- Link to v1: https://patch.msgid.link/20260922-mali-c55-renesas-dts-v1-0-cd63cdb51033@kernel.org

---
Daniel Scally (2):
      arm64: dts: renesas: r9a09g057: Add IVC and ISP nodes
      arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Add ISP and IVC nodes

Linus Walleij (5):
      dt-bindings: media: renesas,r9a09g057-ivc: Describe additional interrupts
      dt-bindings: media: arm,mali-c55: Describe DMA line-tick interrupts
      dt-bindings: media: arm,mali-c55: Add power domain
      [RFC] media: mali-c55: Sequence clocks explicitly
      [RFC] media: mali-c55: Sequence resets explicitly

 .../devicetree/bindings/media/arm,mali-c55.yaml    |  27 +++-
 .../bindings/media/renesas,r9a09g057-ivc.yaml      |  22 +++-
 arch/arm64/boot/dts/renesas/r9a09g057.dtsi         |  47 +++++++
 .../boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts    |   8 ++
 .../media/platform/arm/mali-c55/mali-c55-common.h  |  11 +-
 .../media/platform/arm/mali-c55/mali-c55-core.c    | 136 +++++++++++++++------
 6 files changed, 205 insertions(+), 46 deletions(-)
---
base-commit: cee9395acd8043be0644b25c34bfa86623f2b935
change-id: 20260922-mali-c55-renesas-dts-74d4727f59e5

Best regards,
--  
Linus Walleij <linusw@kernel.org>

[PATCH v5 1/7] dt-bindings: media: renesas,r9a09g057-ivc: Describe additional interrupts

[Linus Walleij]

The RZ/V2H IVC provides input frame-start and frame-stop completion
interrupts alongside its input frame-end interrupt.

Describe these optional interrupts and their signal names from Table 3.1
of the RZ/V2H(P) hardware manual's ISP additional document. Require frame
end first for compatibility with drivers using index-based IRQ lookup.
Keep interrupt-names optional and require only the first interrupt to
preserve support for existing device trees. Extend the example to show
all three interrupts with their names and RZ/V2H interrupt numbers.

Assisted-by: LLM
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
---
 .../bindings/media/renesas,r9a09g057-ivc.yaml      | 22 ++++++++++++++++++++--
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/renesas,r9a09g057-ivc.yaml b/Documentation/devicetree/bindings/media/renesas,r9a09g057-ivc.yaml
index c09cbd8c9e35..75ecb47422b2 100644
--- a/Documentation/devicetree/bindings/media/renesas,r9a09g057-ivc.yaml
+++ b/Documentation/devicetree/bindings/media/renesas,r9a09g057-ivc.yaml
@@ -21,7 +21,21 @@ properties:
     maxItems: 1
 
   interrupts:
-    maxItems: 1
+    description:
+      The image input frame-end interrupt must be specified first to remain
+      compatible with drivers that retrieve it by index.
+    minItems: 1
+    items:
+      - description: Image input frame-end interrupt
+      - description: Image input frame-start interrupt
+      - description: Frame-stop processing completion interrupt
+
+  interrupt-names:
+    minItems: 1
+    items:
+      - const: isp_vvalid_ifp
+      - const: isp_vvalid_irp
+      - const: isp_int_fstop
 
   clocks:
     items:
@@ -92,7 +106,11 @@ examples:
                <&cpg 0xd3>;
       reset-names = "reg", "axi", "isp";
 
-      interrupts = <GIC_SPI 861 IRQ_TYPE_EDGE_RISING>;
+      /* RZ/V2H interrupt numbers. */
+      interrupts = <GIC_SPI 861 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 860 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 864 IRQ_TYPE_LEVEL_HIGH>;
+      interrupt-names = "isp_vvalid_ifp", "isp_vvalid_irp", "isp_int_fstop";
 
       port {
         ivc_out: endpoint {

-- 
2.56.0

[PATCH v5 2/7] dt-bindings: media: arm,mali-c55: Describe DMA line-tick interrupts

[Linus Walleij]

Mali-C55 exposes separate full-resolution and UV DMA writer line-tick
interrupts in addition to its combined core interrupt.

Describe these optional interrupts from Tables 6-14 and 6-24 of the
Mali-C55 Configuration and Integration Manual. Use combined_interrupt
for the combined core interrupt and the signal names for the line-tick
interrupts.

Require the core interrupt first for compatibility with drivers using
index-based IRQ lookup. Keep interrupt-names optional and require only
the first interrupt to preserve support for existing device trees.
Extend the example to show all three interrupts with their names and
RZ/V2H interrupt numbers.

Assisted-by: LLM
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
---
 .../devicetree/bindings/media/arm,mali-c55.yaml    | 23 ++++++++++++++++++++--
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/arm,mali-c55.yaml b/Documentation/devicetree/bindings/media/arm,mali-c55.yaml
index fc4fcd19922a..d04105cd1ecc 100644
--- a/Documentation/devicetree/bindings/media/arm,mali-c55.yaml
+++ b/Documentation/devicetree/bindings/media/arm,mali-c55.yaml
@@ -18,7 +18,21 @@ properties:
     maxItems: 1
 
   interrupts:
-    maxItems: 1
+    description:
+      The combined ISP core interrupt must be specified first to remain
+      compatible with drivers that retrieve it by index.
+    minItems: 1
+    items:
+      - description: Combined ISP core interrupt
+      - description: Full-resolution DMA writer line-tick interrupt
+      - description: Full-resolution UV DMA writer line-tick interrupt
+
+  interrupt-names:
+    minItems: 1
+    items:
+      - const: combined_interrupt
+      - const: fr_dma_writer_linetick_out
+      - const: fr_uv_dma_writer_linetick_out
 
   clocks:
     items:
@@ -75,7 +89,12 @@ examples:
       clock-names = "vclk", "aclk", "hclk";
       resets = <&resets 0>, <&resets 1>, <&resets 2>;
       reset-names = "vresetn", "aresetn", "hresetn";
-      interrupts = <GIC_SPI 861 IRQ_TYPE_EDGE_RISING>;
+      /* RZ/V2H interrupt numbers. */
+      interrupts = <GIC_SPI 859 IRQ_TYPE_LEVEL_HIGH>,
+                   <GIC_SPI 865 IRQ_TYPE_EDGE_RISING>,
+                   <GIC_SPI 866 IRQ_TYPE_EDGE_RISING>;
+      interrupt-names = "combined_interrupt", "fr_dma_writer_linetick_out",
+                        "fr_uv_dma_writer_linetick_out";
 
       port {
         isp_in: endpoint {

-- 
2.56.0

[PATCH v5 3/7] dt-bindings: media: arm,mali-c55: Add power domain

[Linus Walleij]

Some Mali-C55 integrations place the ISP in a power domain. In
particular, RZ/V2H uses the CPG domain to manage its module clocks
through runtime PM.

Allow a single power domain and describe it in the example. Keep the
property optional for integrations that do not expose a power domain.

Assisted-by: LLM
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Daniel Scally <dan.scally@ideasonboard.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
---
 Documentation/devicetree/bindings/media/arm,mali-c55.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/media/arm,mali-c55.yaml b/Documentation/devicetree/bindings/media/arm,mali-c55.yaml
index d04105cd1ecc..23b53faec73d 100644
--- a/Documentation/devicetree/bindings/media/arm,mali-c55.yaml
+++ b/Documentation/devicetree/bindings/media/arm,mali-c55.yaml
@@ -46,6 +46,9 @@ properties:
       - const: aclk
       - const: hclk
 
+  power-domains:
+    maxItems: 1
+
   resets:
     items:
       - description: vclk domain reset
@@ -87,6 +90,7 @@ examples:
       reg = <0x400000 0x200000>;
       clocks = <&clk 0>, <&clk 1>, <&clk 2>;
       clock-names = "vclk", "aclk", "hclk";
+      power-domains = <&power>;
       resets = <&resets 0>, <&resets 1>, <&resets 2>;
       reset-names = "vresetn", "aresetn", "hresetn";
       /* RZ/V2H interrupt numbers. */

-- 
2.56.0

[PATCH v5 4/7] arm64: dts: renesas: r9a09g057: Add IVC and ISP nodes

[Linus Walleij]

From: Daniel Scally <dan.scally@ideasonboard.com>

Add the Input Video Control Block and Arm Mali-C55 ISP to the device
tree file for the RZ/V2H(P) SoC.

[Rebase onto v7.3-rc1, place the nodes in address order, add the missing
 interrupts in binding order and name them. - Linus Walleij]

Assisted-by: LLM
Signed-off-by: Daniel Scally <dan.scally@ideasonboard.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
---
 arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 47 ++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index 639693d464a7..228155fa3c76 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -1839,6 +1839,53 @@ queue3 {
 			};
 		};
 
+		ivc: isp-input@16040000 {
+			compatible = "renesas,r9a09g057-ivc";
+			reg = <0 0x16040000 0 0x10000>;
+			clocks = <&cpg CPG_MOD 0xe3>, <&cpg CPG_MOD 0xe4>,
+				 <&cpg CPG_MOD 0xe5>;
+			clock-names = "reg", "axi", "isp";
+			interrupts = <GIC_SPI 861 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 860 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 864 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "isp_vvalid_ifp", "isp_vvalid_irp",
+					  "isp_int_fstop";
+			power-domains = <&cpg>;
+			resets = <&cpg 0xd4>, <&cpg 0xd1>, <&cpg 0xd3>;
+			reset-names = "reg", "axi", "isp";
+			status = "disabled";
+
+			port {
+				ivc_out: endpoint {
+					remote-endpoint = <&isp_in>;
+				};
+			};
+		};
+
+		isp: isp@16080000 {
+			compatible = "arm,mali-c55";
+			reg = <0 0x16080000 0 0x80000>;
+			clocks = <&cpg CPG_MOD 0xe5>, <&cpg CPG_MOD 0xe4>,
+				 <&cpg CPG_MOD 0xe2>;
+			clock-names = "vclk", "aclk", "hclk";
+			interrupts = <GIC_SPI 859 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 865 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 866 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "combined_interrupt",
+					  "fr_dma_writer_linetick_out",
+					  "fr_uv_dma_writer_linetick_out";
+			power-domains = <&cpg>;
+			resets = <&cpg 0xd3>, <&cpg 0xd1>, <&cpg 0xd2>;
+			reset-names = "vresetn", "aresetn", "hresetn";
+			status = "disabled";
+
+			port {
+				isp_in: endpoint {
+					remote-endpoint = <&ivc_out>;
+				};
+			};
+		};
+
 		dsi: dsi@16430000 {
 			compatible = "renesas,r9a09g057-mipi-dsi";
 			reg = <0 0x16430000 0 0x20000>;

-- 
2.56.0

[PATCH v5 5/7] arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Add ISP and IVC nodes

[Linus Walleij]

From: Daniel Scally <dan.scally@ideasonboard.com>

Add nodes to devicetree enabling the ISP and IVC that are found on
the RZ/V2H(P) SoC.

[Rebase onto v7.3-rc1 and sort the board overrides by label.
 - Linus Walleij]

Assisted-by: LLM
Signed-off-by: Daniel Scally <dan.scally@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linusw@kernel.org>
---
 arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
index 637fc92dcc26..74b75be599ae 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
@@ -305,6 +305,14 @@ versa3: clock-generator@69 {
 	};
 };
 
+&isp {
+	status = "okay";
+};
+
+&ivc {
+	status = "okay";
+};
+
 &mdio0 {
 	phy0: ethernet-phy@0 {
 		compatible = "ethernet-phy-id0022.1640";

-- 
2.56.0

[PATCH RFC v5 6/7] media: mali-c55: Sequence clocks explicitly

[Linus Walleij]

Reporters avoid a register-access hang on RZ/V2H by swapping the first
and third clock and reset identifiers in the ISP node. Test the clock
ordering from that configuration without changing the DT assignments.

Acquire hclk, aclk and vclk individually by name. Enable them in that
order and disable them in reverse order. With the current RZ/V2H DT,
this requests clocks 0xe2, 0xe4 and 0xe5, matching the reported working
configuration. Unwind successful enables in reverse order on failure.

This RFC changes the driver's sequence only. The CPG power domain can
enable clocks in DT order before the runtime-resume callback, and shared
users may already hold clocks enabled. It does not guarantee the same
order of physical clock transitions as the DT swap.

The report changed clocks and resets together, so clock ordering alone
has not been shown to fix the hang. Target hardware testing is needed.

Signed-off-by: Linus Walleij <linusw@kernel.org>
---
 .../media/platform/arm/mali-c55/mali-c55-common.h  |  5 +-
 .../media/platform/arm/mali-c55/mali-c55-core.c    | 59 +++++++++++++++-------
 2 files changed, 44 insertions(+), 20 deletions(-)

diff --git a/drivers/media/platform/arm/mali-c55/mali-c55-common.h b/drivers/media/platform/arm/mali-c55/mali-c55-common.h
index 13a3e9dc4243..b1ac50d6b30e 100644
--- a/drivers/media/platform/arm/mali-c55/mali-c55-common.h
+++ b/drivers/media/platform/arm/mali-c55/mali-c55-common.h
@@ -38,7 +38,6 @@
 
 #define MALI_C55_DEFAULT_MEDIA_BUS_FMT	MEDIA_BUS_FMT_RGB121212_1X36
 
-#define MALI_C55_NUM_CLKS		3
 #define MALI_C55_NUM_RESETS		3
 
 struct device;
@@ -237,7 +236,9 @@ struct mali_c55_context {
 struct mali_c55 {
 	struct device *dev;
 	void __iomem *base;
-	struct clk_bulk_data clks[MALI_C55_NUM_CLKS];
+	struct clk *hclk;
+	struct clk *aclk;
+	struct clk *vclk;
 	struct reset_control_bulk_data resets[MALI_C55_NUM_RESETS];
 	int irqnum;
 
diff --git a/drivers/media/platform/arm/mali-c55/mali-c55-core.c b/drivers/media/platform/arm/mali-c55/mali-c55-core.c
index f28e9f4354ac..0caef871cad4 100644
--- a/drivers/media/platform/arm/mali-c55/mali-c55-core.c
+++ b/drivers/media/platform/arm/mali-c55/mali-c55-core.c
@@ -64,12 +64,6 @@ static const unsigned int config_space_addrs[] = {
 	[MALI_C55_CONFIG_PONG] = 0x22b2c,
 };
 
-static const char * const mali_c55_clk_names[MALI_C55_NUM_CLKS] = {
-	"vclk",
-	"aclk",
-	"hclk",
-};
-
 static const char * const mali_c55_reset_names[MALI_C55_NUM_RESETS] = {
 	"vresetn",
 	"aresetn",
@@ -668,7 +662,9 @@ static int mali_c55_init_context(struct mali_c55 *mali_c55,
 static void __mali_c55_power_off(struct mali_c55 *mali_c55)
 {
 	reset_control_bulk_assert(ARRAY_SIZE(mali_c55->resets), mali_c55->resets);
-	clk_bulk_disable_unprepare(ARRAY_SIZE(mali_c55->clks), mali_c55->clks);
+	clk_disable_unprepare(mali_c55->vclk);
+	clk_disable_unprepare(mali_c55->aclk);
+	clk_disable_unprepare(mali_c55->hclk);
 }
 
 static int __maybe_unused mali_c55_runtime_suspend(struct device *dev)
@@ -687,20 +683,30 @@ static int __mali_c55_power_on(struct mali_c55 *mali_c55)
 	int ret;
 	u32 val;
 
-	ret = clk_bulk_prepare_enable(ARRAY_SIZE(mali_c55->clks),
-				      mali_c55->clks);
+	/* Enable the register interface, AXI and video clocks in that order. */
+	ret = clk_prepare_enable(mali_c55->hclk);
 	if (ret) {
-		dev_err(mali_c55->dev, "failed to enable clocks\n");
+		dev_err(mali_c55->dev, "failed to enable hclk\n");
 		return ret;
 	}
 
+	ret = clk_prepare_enable(mali_c55->aclk);
+	if (ret) {
+		dev_err(mali_c55->dev, "failed to enable aclk\n");
+		goto err_disable_hclk;
+	}
+
+	ret = clk_prepare_enable(mali_c55->vclk);
+	if (ret) {
+		dev_err(mali_c55->dev, "failed to enable vclk\n");
+		goto err_disable_aclk;
+	}
+
 	ret = reset_control_bulk_deassert(ARRAY_SIZE(mali_c55->resets),
 					  mali_c55->resets);
 	if (ret) {
 		dev_err(mali_c55->dev, "failed to deassert resets\n");
-		clk_bulk_disable_unprepare(ARRAY_SIZE(mali_c55->clks),
-					   mali_c55->clks);
-		return ret;
+		goto err_disable_vclk;
 	}
 
 	/* Use "software only" context management. */
@@ -734,6 +740,15 @@ static int __mali_c55_power_on(struct mali_c55 *mali_c55)
 			   val, !val, 10 * USEC_PER_MSEC, 250 * USEC_PER_MSEC);
 
 	return 0;
+
+err_disable_vclk:
+	clk_disable_unprepare(mali_c55->vclk);
+err_disable_aclk:
+	clk_disable_unprepare(mali_c55->aclk);
+err_disable_hclk:
+	clk_disable_unprepare(mali_c55->hclk);
+
+	return ret;
 }
 
 static int __maybe_unused mali_c55_runtime_resume(struct device *dev)
@@ -788,12 +803,20 @@ static int mali_c55_probe(struct platform_device *pdev)
 		return dev_err_probe(dev, PTR_ERR(mali_c55->base),
 				     "failed to map IO memory\n");
 
-	for (unsigned int i = 0; i < ARRAY_SIZE(mali_c55_clk_names); i++)
-		mali_c55->clks[i].id = mali_c55_clk_names[i];
+	mali_c55->hclk = devm_clk_get(dev, "hclk");
+	if (IS_ERR(mali_c55->hclk))
+		return dev_err_probe(dev, PTR_ERR(mali_c55->hclk),
+				     "failed to acquire hclk\n");
 
-	ret = devm_clk_bulk_get(dev, ARRAY_SIZE(mali_c55->clks), mali_c55->clks);
-	if (ret)
-		return dev_err_probe(dev, ret, "failed to acquire clocks\n");
+	mali_c55->aclk = devm_clk_get(dev, "aclk");
+	if (IS_ERR(mali_c55->aclk))
+		return dev_err_probe(dev, PTR_ERR(mali_c55->aclk),
+				     "failed to acquire aclk\n");
+
+	mali_c55->vclk = devm_clk_get(dev, "vclk");
+	if (IS_ERR(mali_c55->vclk))
+		return dev_err_probe(dev, PTR_ERR(mali_c55->vclk),
+				     "failed to acquire vclk\n");
 
 	for (unsigned int i = 0; i < ARRAY_SIZE(mali_c55_reset_names); i++)
 		mali_c55->resets[i].id = mali_c55_reset_names[i];

-- 
2.56.0

[PATCH RFC v5 7/7] media: mali-c55: Sequence resets explicitly

[Linus Walleij]

Reporters avoid a register-access hang on RZ/V2H by swapping the first
and third clock and reset identifiers in the ISP node. Test the reset
ordering from that configuration without changing the DT assignments.

Acquire vresetn, aresetn and hresetn individually by name, retaining their
optional shared semantics. Deassert them in that order and assert them
in reverse order. With the current RZ/V2H DT, this deasserts 0xd3, 0xd1
and 0xd2 and asserts 0xd2, 0xd1 and 0xd3. These are the orders produced
by the bulk helpers with the reported working DT swap, since bulk
reset deassertion traverses its array backwards.

Preserve the bulk helpers' error rollback. A shared reset increments its
deassert count before invoking the provider, so a failed deassertion
must also be balanced when unwinding.

This RFC tests the driver's request order, not simultaneous hardware
reset transitions. The IVC can already hold shared resets deasserted.
The report changed clocks and resets together, so this ordering still
needs target hardware testing.

Signed-off-by: Linus Walleij <linusw@kernel.org>
---
 .../media/platform/arm/mali-c55/mali-c55-common.h  |  6 +-
 .../media/platform/arm/mali-c55/mali-c55-core.c    | 75 ++++++++++++++++------
 2 files changed, 60 insertions(+), 21 deletions(-)

diff --git a/drivers/media/platform/arm/mali-c55/mali-c55-common.h b/drivers/media/platform/arm/mali-c55/mali-c55-common.h
index b1ac50d6b30e..f2cd4d4ef472 100644
--- a/drivers/media/platform/arm/mali-c55/mali-c55-common.h
+++ b/drivers/media/platform/arm/mali-c55/mali-c55-common.h
@@ -38,8 +38,6 @@
 
 #define MALI_C55_DEFAULT_MEDIA_BUS_FMT	MEDIA_BUS_FMT_RGB121212_1X36
 
-#define MALI_C55_NUM_RESETS		3
-
 struct device;
 struct mali_c55;
 struct mali_c55_cap_dev;
@@ -239,7 +237,9 @@ struct mali_c55 {
 	struct clk *hclk;
 	struct clk *aclk;
 	struct clk *vclk;
-	struct reset_control_bulk_data resets[MALI_C55_NUM_RESETS];
+	struct reset_control *vresetn;
+	struct reset_control *aresetn;
+	struct reset_control *hresetn;
 	int irqnum;
 
 	u16 capabilities;
diff --git a/drivers/media/platform/arm/mali-c55/mali-c55-core.c b/drivers/media/platform/arm/mali-c55/mali-c55-core.c
index 0caef871cad4..47e26d85784e 100644
--- a/drivers/media/platform/arm/mali-c55/mali-c55-core.c
+++ b/drivers/media/platform/arm/mali-c55/mali-c55-core.c
@@ -64,12 +64,6 @@ static const unsigned int config_space_addrs[] = {
 	[MALI_C55_CONFIG_PONG] = 0x22b2c,
 };
 
-static const char * const mali_c55_reset_names[MALI_C55_NUM_RESETS] = {
-	"vresetn",
-	"aresetn",
-	"hresetn",
-};
-
 /*
  * System IO
  *
@@ -661,7 +655,27 @@ static int mali_c55_init_context(struct mali_c55 *mali_c55,
 
 static void __mali_c55_power_off(struct mali_c55 *mali_c55)
 {
-	reset_control_bulk_assert(ARRAY_SIZE(mali_c55->resets), mali_c55->resets);
+	int ret;
+
+	ret = reset_control_assert(mali_c55->hresetn);
+	if (ret)
+		goto disable_clocks;
+
+	ret = reset_control_assert(mali_c55->aresetn);
+	if (ret)
+		goto err_deassert_hresetn;
+
+	ret = reset_control_assert(mali_c55->vresetn);
+	if (ret)
+		goto err_deassert_aresetn;
+
+	goto disable_clocks;
+
+err_deassert_aresetn:
+	reset_control_deassert(mali_c55->aresetn);
+err_deassert_hresetn:
+	reset_control_deassert(mali_c55->hresetn);
+disable_clocks:
 	clk_disable_unprepare(mali_c55->vclk);
 	clk_disable_unprepare(mali_c55->aclk);
 	clk_disable_unprepare(mali_c55->hclk);
@@ -702,11 +716,23 @@ static int __mali_c55_power_on(struct mali_c55 *mali_c55)
 		goto err_disable_aclk;
 	}
 
-	ret = reset_control_bulk_deassert(ARRAY_SIZE(mali_c55->resets),
-					  mali_c55->resets);
+	/* Release video, AXI and register interface resets in that order. */
+	ret = reset_control_deassert(mali_c55->vresetn);
 	if (ret) {
-		dev_err(mali_c55->dev, "failed to deassert resets\n");
-		goto err_disable_vclk;
+		dev_err(mali_c55->dev, "failed to deassert vresetn\n");
+		goto err_assert_vresetn;
+	}
+
+	ret = reset_control_deassert(mali_c55->aresetn);
+	if (ret) {
+		dev_err(mali_c55->dev, "failed to deassert aresetn\n");
+		goto err_assert_aresetn;
+	}
+
+	ret = reset_control_deassert(mali_c55->hresetn);
+	if (ret) {
+		dev_err(mali_c55->dev, "failed to deassert hresetn\n");
+		goto err_assert_hresetn;
 	}
 
 	/* Use "software only" context management. */
@@ -741,7 +767,13 @@ static int __mali_c55_power_on(struct mali_c55 *mali_c55)
 
 	return 0;
 
-err_disable_vclk:
+	/* A shared reset takes a reference before calling its provider. */
+err_assert_hresetn:
+	reset_control_assert(mali_c55->hresetn);
+err_assert_aresetn:
+	reset_control_assert(mali_c55->aresetn);
+err_assert_vresetn:
+	reset_control_assert(mali_c55->vresetn);
 	clk_disable_unprepare(mali_c55->vclk);
 err_disable_aclk:
 	clk_disable_unprepare(mali_c55->aclk);
@@ -818,13 +850,20 @@ static int mali_c55_probe(struct platform_device *pdev)
 		return dev_err_probe(dev, PTR_ERR(mali_c55->vclk),
 				     "failed to acquire vclk\n");
 
-	for (unsigned int i = 0; i < ARRAY_SIZE(mali_c55_reset_names); i++)
-		mali_c55->resets[i].id = mali_c55_reset_names[i];
+	mali_c55->vresetn = devm_reset_control_get_optional_shared(dev, "vresetn");
+	if (IS_ERR(mali_c55->vresetn))
+		return dev_err_probe(dev, PTR_ERR(mali_c55->vresetn),
+				     "failed to acquire vresetn\n");
 
-	ret = devm_reset_control_bulk_get_optional_shared(dev,
-			ARRAY_SIZE(mali_c55_reset_names), mali_c55->resets);
-	if (ret)
-		return dev_err_probe(dev, ret, "failed to acquire resets\n");
+	mali_c55->aresetn = devm_reset_control_get_optional_shared(dev, "aresetn");
+	if (IS_ERR(mali_c55->aresetn))
+		return dev_err_probe(dev, PTR_ERR(mali_c55->aresetn),
+				     "failed to acquire aresetn\n");
+
+	mali_c55->hresetn = devm_reset_control_get_optional_shared(dev, "hresetn");
+	if (IS_ERR(mali_c55->hresetn))
+		return dev_err_probe(dev, PTR_ERR(mali_c55->hresetn),
+				     "failed to acquire hresetn\n");
 
 	of_reserved_mem_device_init(dev);
 	vb2_dma_contig_set_max_seg_size(dev, UINT_MAX);

-- 
2.56.0

Re: [PATCH RFC v5 6/7] media: mali-c55: Sequence clocks explicitly

[Lad, Prabhakar]

Hi Linus,

Thank you for the patch.

On Tue, Oct 27, 2026 at 4:15 PM Linus Walleij <linusw@kernel.org> wrote:
>
> Reporters avoid a register-access hang on RZ/V2H by swapping the first
> and third clock and reset identifiers in the ISP node. Test the clock
> ordering from that configuration without changing the DT assignments.
>
> Acquire hclk, aclk and vclk individually by name. Enable them in that
> order and disable them in reverse order. With the current RZ/V2H DT,
> this requests clocks 0xe2, 0xe4 and 0xe5, matching the reported working
> configuration. Unwind successful enables in reverse order on failure.
>
> This RFC changes the driver's sequence only. The CPG power domain can
> enable clocks in DT order before the runtime-resume callback, and shared
> users may already hold clocks enabled. It does not guarantee the same
> order of physical clock transitions as the DT swap.
>
> The report changed clocks and resets together, so clock ordering alone
> has not been shown to fix the hang. Target hardware testing is needed.
>
> Signed-off-by: Linus Walleij <linusw@kernel.org>
> ---
>  .../media/platform/arm/mali-c55/mali-c55-common.h  |  5 +-
>  .../media/platform/arm/mali-c55/mali-c55-core.c    | 59 +++++++++++++++-------
>  2 files changed, 44 insertions(+), 20 deletions(-)
>
I think we can drop this patch as we are not seeing any issues with
clock ordereing see response on 7/7

Cheers,
Prabhakar

> diff --git a/drivers/media/platform/arm/mali-c55/mali-c55-common.h b/drivers/media/platform/arm/mali-c55/mali-c55-common.h
> index 13a3e9dc4243..b1ac50d6b30e 100644
> --- a/drivers/media/platform/arm/mali-c55/mali-c55-common.h
> +++ b/drivers/media/platform/arm/mali-c55/mali-c55-common.h
> @@ -38,7 +38,6 @@
>
>  #define MALI_C55_DEFAULT_MEDIA_BUS_FMT MEDIA_BUS_FMT_RGB121212_1X36
>
> -#define MALI_C55_NUM_CLKS              3
>  #define MALI_C55_NUM_RESETS            3
>
>  struct device;
> @@ -237,7 +236,9 @@ struct mali_c55_context {
>  struct mali_c55 {
>         struct device *dev;
>         void __iomem *base;
> -       struct clk_bulk_data clks[MALI_C55_NUM_CLKS];
> +       struct clk *hclk;
> +       struct clk *aclk;
> +       struct clk *vclk;
>         struct reset_control_bulk_data resets[MALI_C55_NUM_RESETS];
>         int irqnum;
>
> diff --git a/drivers/media/platform/arm/mali-c55/mali-c55-core.c b/drivers/media/platform/arm/mali-c55/mali-c55-core.c
> index f28e9f4354ac..0caef871cad4 100644
> --- a/drivers/media/platform/arm/mali-c55/mali-c55-core.c
> +++ b/drivers/media/platform/arm/mali-c55/mali-c55-core.c
> @@ -64,12 +64,6 @@ static const unsigned int config_space_addrs[] = {
>         [MALI_C55_CONFIG_PONG] = 0x22b2c,
>  };
>
> -static const char * const mali_c55_clk_names[MALI_C55_NUM_CLKS] = {
> -       "vclk",
> -       "aclk",
> -       "hclk",
> -};
> -
>  static const char * const mali_c55_reset_names[MALI_C55_NUM_RESETS] = {
>         "vresetn",
>         "aresetn",
> @@ -668,7 +662,9 @@ static int mali_c55_init_context(struct mali_c55 *mali_c55,
>  static void __mali_c55_power_off(struct mali_c55 *mali_c55)
>  {
>         reset_control_bulk_assert(ARRAY_SIZE(mali_c55->resets), mali_c55->resets);
> -       clk_bulk_disable_unprepare(ARRAY_SIZE(mali_c55->clks), mali_c55->clks);
> +       clk_disable_unprepare(mali_c55->vclk);
> +       clk_disable_unprepare(mali_c55->aclk);
> +       clk_disable_unprepare(mali_c55->hclk);
>  }
>
>  static int __maybe_unused mali_c55_runtime_suspend(struct device *dev)
> @@ -687,20 +683,30 @@ static int __mali_c55_power_on(struct mali_c55 *mali_c55)
>         int ret;
>         u32 val;
>
> -       ret = clk_bulk_prepare_enable(ARRAY_SIZE(mali_c55->clks),
> -                                     mali_c55->clks);
> +       /* Enable the register interface, AXI and video clocks in that order. */
> +       ret = clk_prepare_enable(mali_c55->hclk);
>         if (ret) {
> -               dev_err(mali_c55->dev, "failed to enable clocks\n");
> +               dev_err(mali_c55->dev, "failed to enable hclk\n");
>                 return ret;
>         }
>
> +       ret = clk_prepare_enable(mali_c55->aclk);
> +       if (ret) {
> +               dev_err(mali_c55->dev, "failed to enable aclk\n");
> +               goto err_disable_hclk;
> +       }
> +
> +       ret = clk_prepare_enable(mali_c55->vclk);
> +       if (ret) {
> +               dev_err(mali_c55->dev, "failed to enable vclk\n");
> +               goto err_disable_aclk;
> +       }
> +
>         ret = reset_control_bulk_deassert(ARRAY_SIZE(mali_c55->resets),
>                                           mali_c55->resets);
>         if (ret) {
>                 dev_err(mali_c55->dev, "failed to deassert resets\n");
> -               clk_bulk_disable_unprepare(ARRAY_SIZE(mali_c55->clks),
> -                                          mali_c55->clks);
> -               return ret;
> +               goto err_disable_vclk;
>         }
>
>         /* Use "software only" context management. */
> @@ -734,6 +740,15 @@ static int __mali_c55_power_on(struct mali_c55 *mali_c55)
>                            val, !val, 10 * USEC_PER_MSEC, 250 * USEC_PER_MSEC);
>
>         return 0;
> +
> +err_disable_vclk:
> +       clk_disable_unprepare(mali_c55->vclk);
> +err_disable_aclk:
> +       clk_disable_unprepare(mali_c55->aclk);
> +err_disable_hclk:
> +       clk_disable_unprepare(mali_c55->hclk);
> +
> +       return ret;
>  }
>
>  static int __maybe_unused mali_c55_runtime_resume(struct device *dev)
> @@ -788,12 +803,20 @@ static int mali_c55_probe(struct platform_device *pdev)
>                 return dev_err_probe(dev, PTR_ERR(mali_c55->base),
>                                      "failed to map IO memory\n");
>
> -       for (unsigned int i = 0; i < ARRAY_SIZE(mali_c55_clk_names); i++)
> -               mali_c55->clks[i].id = mali_c55_clk_names[i];
> +       mali_c55->hclk = devm_clk_get(dev, "hclk");
> +       if (IS_ERR(mali_c55->hclk))
> +               return dev_err_probe(dev, PTR_ERR(mali_c55->hclk),
> +                                    "failed to acquire hclk\n");
>
> -       ret = devm_clk_bulk_get(dev, ARRAY_SIZE(mali_c55->clks), mali_c55->clks);
> -       if (ret)
> -               return dev_err_probe(dev, ret, "failed to acquire clocks\n");
> +       mali_c55->aclk = devm_clk_get(dev, "aclk");
> +       if (IS_ERR(mali_c55->aclk))
> +               return dev_err_probe(dev, PTR_ERR(mali_c55->aclk),
> +                                    "failed to acquire aclk\n");
> +
> +       mali_c55->vclk = devm_clk_get(dev, "vclk");
> +       if (IS_ERR(mali_c55->vclk))
> +               return dev_err_probe(dev, PTR_ERR(mali_c55->vclk),
> +                                    "failed to acquire vclk\n");
>
>         for (unsigned int i = 0; i < ARRAY_SIZE(mali_c55_reset_names); i++)
>                 mali_c55->resets[i].id = mali_c55_reset_names[i];
>
> --
> 2.56.0
>
>

Re: [PATCH RFC v5 7/7] media: mali-c55: Sequence resets explicitly

[Lad, Prabhakar]

Hi Linus,

Thank you for the patch.

On Tue, Oct 27, 2026 at 4:25 PM Linus Walleij <linusw@kernel.org> wrote:
>
> Reporters avoid a register-access hang on RZ/V2H by swapping the first
> and third clock and reset identifiers in the ISP node. Test the reset
> ordering from that configuration without changing the DT assignments.
>
> Acquire vresetn, aresetn and hresetn individually by name, retaining their
> optional shared semantics. Deassert them in that order and assert them
> in reverse order. With the current RZ/V2H DT, this deasserts 0xd3, 0xd1
> and 0xd2 and asserts 0xd2, 0xd1 and 0xd3. These are the orders produced
> by the bulk helpers with the reported working DT swap, since bulk
> reset deassertion traverses its array backwards.
>
> Preserve the bulk helpers' error rollback. A shared reset increments its
> deassert count before invoking the provider, so a failed deassertion
> must also be balanced when unwinding.
>
> This RFC tests the driver's request order, not simultaneous hardware
> reset transitions. The IVC can already hold shared resets deasserted.
> The report changed clocks and resets together, so this ordering still
> needs target hardware testing.
>
> Signed-off-by: Linus Walleij <linusw@kernel.org>
> ---
>  .../media/platform/arm/mali-c55/mali-c55-common.h  |  6 +-
>  .../media/platform/arm/mali-c55/mali-c55-core.c    | 75 ++++++++++++++++------
>  2 files changed, 60 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/media/platform/arm/mali-c55/mali-c55-common.h b/drivers/media/platform/arm/mali-c55/mali-c55-common.h
> index b1ac50d6b30e..f2cd4d4ef472 100644
> --- a/drivers/media/platform/arm/mali-c55/mali-c55-common.h
> +++ b/drivers/media/platform/arm/mali-c55/mali-c55-common.h
> @@ -38,8 +38,6 @@
>
>  #define MALI_C55_DEFAULT_MEDIA_BUS_FMT MEDIA_BUS_FMT_RGB121212_1X36
>
> -#define MALI_C55_NUM_RESETS            3
> -
>  struct device;
>  struct mali_c55;
>  struct mali_c55_cap_dev;
> @@ -239,7 +237,9 @@ struct mali_c55 {
>         struct clk *hclk;
>         struct clk *aclk;
>         struct clk *vclk;
> -       struct reset_control_bulk_data resets[MALI_C55_NUM_RESETS];
> +       struct reset_control *vresetn;
> +       struct reset_control *aresetn;
> +       struct reset_control *hresetn;
>         int irqnum;
>
>         u16 capabilities;
> diff --git a/drivers/media/platform/arm/mali-c55/mali-c55-core.c b/drivers/media/platform/arm/mali-c55/mali-c55-core.c
> index 0caef871cad4..47e26d85784e 100644
> --- a/drivers/media/platform/arm/mali-c55/mali-c55-core.c
> +++ b/drivers/media/platform/arm/mali-c55/mali-c55-core.c
> @@ -64,12 +64,6 @@ static const unsigned int config_space_addrs[] = {
>         [MALI_C55_CONFIG_PONG] = 0x22b2c,
>  };
>
> -static const char * const mali_c55_reset_names[MALI_C55_NUM_RESETS] = {
> -       "vresetn",
> -       "aresetn",
> -       "hresetn",
> -};
> -
I tested on the RZ/V2H EVK with the clocks and DT left untouched,
changing only the reset order.

The hang comes from the reset assert order in __mali_c55_power_off().
Asserting vresetn (the ISP core reset per the RZ/V2H manual) before
hresetn/aresetn wedges the ISP. The next power-on then stalls on its
first register access. The deassert order doesn't matter.

Asserting h->a->v (deasserting v->a->h) passes repeated runtime-PM
cycles and also works with the IVC enabled. So 7/7 gives the right
reset sequence, 6/7 isn't needed for this, and the existing DT mapping
(0xd3 = vresetn = ISP core reset) is correct.

A smaller alternative keeps the bulk API and only reorders the names:

+/*
+ * The reset bulk API asserts the resets in array order and deasserts them in
+ * reverse order. The video core reset (vresetn) must be asserted last, after
+ * the register (hresetn) and AXI (aresetn) interface resets. Otherwise the
+ * ISP can be left in a state where the first register access after the next
+ * power-on stalls the bus.
+ */
 static const char * const mali_c55_reset_names[MALI_C55_NUM_RESETS] = {
-       "vresetn",
-       "aresetn",
        "hresetn",
+       "aresetn",
+       "vresetn",
 };

Cheers,
Prabhakar

>  /*
>   * System IO
>   *
> @@ -661,7 +655,27 @@ static int mali_c55_init_context(struct mali_c55 *mali_c55,
>
>  static void __mali_c55_power_off(struct mali_c55 *mali_c55)
>  {
> -       reset_control_bulk_assert(ARRAY_SIZE(mali_c55->resets), mali_c55->resets);
> +       int ret;
> +
> +       ret = reset_control_assert(mali_c55->hresetn);
> +       if (ret)
> +               goto disable_clocks;
> +
> +       ret = reset_control_assert(mali_c55->aresetn);
> +       if (ret)
> +               goto err_deassert_hresetn;
> +
> +       ret = reset_control_assert(mali_c55->vresetn);
> +       if (ret)
> +               goto err_deassert_aresetn;
> +
> +       goto disable_clocks;
> +
> +err_deassert_aresetn:
> +       reset_control_deassert(mali_c55->aresetn);
> +err_deassert_hresetn:
> +       reset_control_deassert(mali_c55->hresetn);
> +disable_clocks:
>         clk_disable_unprepare(mali_c55->vclk);
>         clk_disable_unprepare(mali_c55->aclk);
>         clk_disable_unprepare(mali_c55->hclk);
> @@ -702,11 +716,23 @@ static int __mali_c55_power_on(struct mali_c55 *mali_c55)
>                 goto err_disable_aclk;
>         }
>
> -       ret = reset_control_bulk_deassert(ARRAY_SIZE(mali_c55->resets),
> -                                         mali_c55->resets);
> +       /* Release video, AXI and register interface resets in that order. */
> +       ret = reset_control_deassert(mali_c55->vresetn);
>         if (ret) {
> -               dev_err(mali_c55->dev, "failed to deassert resets\n");
> -               goto err_disable_vclk;
> +               dev_err(mali_c55->dev, "failed to deassert vresetn\n");
> +               goto err_assert_vresetn;
> +       }
> +
> +       ret = reset_control_deassert(mali_c55->aresetn);
> +       if (ret) {
> +               dev_err(mali_c55->dev, "failed to deassert aresetn\n");
> +               goto err_assert_aresetn;
> +       }
> +
> +       ret = reset_control_deassert(mali_c55->hresetn);
> +       if (ret) {
> +               dev_err(mali_c55->dev, "failed to deassert hresetn\n");
> +               goto err_assert_hresetn;
>         }
>
>         /* Use "software only" context management. */
> @@ -741,7 +767,13 @@ static int __mali_c55_power_on(struct mali_c55 *mali_c55)
>
>         return 0;
>
> -err_disable_vclk:
> +       /* A shared reset takes a reference before calling its provider. */
> +err_assert_hresetn:
> +       reset_control_assert(mali_c55->hresetn);
> +err_assert_aresetn:
> +       reset_control_assert(mali_c55->aresetn);
> +err_assert_vresetn:
> +       reset_control_assert(mali_c55->vresetn);
>         clk_disable_unprepare(mali_c55->vclk);
>  err_disable_aclk:
>         clk_disable_unprepare(mali_c55->aclk);
> @@ -818,13 +850,20 @@ static int mali_c55_probe(struct platform_device *pdev)
>                 return dev_err_probe(dev, PTR_ERR(mali_c55->vclk),
>                                      "failed to acquire vclk\n");
>
> -       for (unsigned int i = 0; i < ARRAY_SIZE(mali_c55_reset_names); i++)
> -               mali_c55->resets[i].id = mali_c55_reset_names[i];
> +       mali_c55->vresetn = devm_reset_control_get_optional_shared(dev, "vresetn");
> +       if (IS_ERR(mali_c55->vresetn))
> +               return dev_err_probe(dev, PTR_ERR(mali_c55->vresetn),
> +                                    "failed to acquire vresetn\n");
>
> -       ret = devm_reset_control_bulk_get_optional_shared(dev,
> -                       ARRAY_SIZE(mali_c55_reset_names), mali_c55->resets);
> -       if (ret)
> -               return dev_err_probe(dev, ret, "failed to acquire resets\n");
> +       mali_c55->aresetn = devm_reset_control_get_optional_shared(dev, "aresetn");
> +       if (IS_ERR(mali_c55->aresetn))
> +               return dev_err_probe(dev, PTR_ERR(mali_c55->aresetn),
> +                                    "failed to acquire aresetn\n");
> +
> +       mali_c55->hresetn = devm_reset_control_get_optional_shared(dev, "hresetn");
> +       if (IS_ERR(mali_c55->hresetn))
> +               return dev_err_probe(dev, PTR_ERR(mali_c55->hresetn),
> +                                    "failed to acquire hresetn\n");
>
>         of_reserved_mem_device_init(dev);
>         vb2_dma_contig_set_max_seg_size(dev, UINT_MAX);
>
> --
> 2.56.0
>
>

Re: [PATCH v5 0/7] arm64: dts: renesas: Enable ISP and IVC on RZ/V2H EVK

[Barnabás Pőcze]

Hi

2026. 10. 27. 17:11 keltezéssel, Linus Walleij írta:
> Describe the optional ISP DMA line-tick and IVC frame-start/frame-stop
> interrupts. Add the RZ/V2H(P) IVC and Arm Mali-C55 ISP nodes, connect their
> video endpoints, and enable both blocks on the RZ/V2H EVK.
> 
> Two additional RFC patches replace bulk clock and reset operations in
> the Mali-C55 driver with explicit sequences using named handles. They
> reproduce the driver call orders from the reporters' working DT swap
> while keeping the clock and reset assignments unchanged.
> 
> The Device Tree does *not* guarantee any sequencing of resources,
> so these sequences must be handled in code.
> 
> Clocks are enabled hclk, aclk, vclk and disabled in reverse order.
> Resets are deasserted vresetn, aresetn, hresetn and asserted in reverse
> order. These are driver-only experiments: the CPG power domain can
> enable clocks in DT order before the callback, and IVC may already hold
> shared resources active. The physical transition order is not guaranteed.
> These RFC patches have not been tested on hardware.
> 
> After these patches, and enabling the right Linux drivers, we get
> this in the console:
> mali-c55 16080000.isp: Detected Mali-C55 ISP 9000043.31032022.0
> 
> This was done in order to enable booting mainline with mainline
> device trees.
> 
> The patches were authored with the assistance of an LLM.
> 
> Signed-off-by: Linus Walleij <linusw@kernel.org>
> ---
> Changes in v5:
> - Add two RFC driver patches for explicit clock and reset sequencing.

I also had the same problem as reported in https://lore.kernel.org/all/asz8oEtow_lrUU7K@zed/.
So with the first 5 changes, the device will lock up when trying to stream:

   [  124.093148] watchdog: CPU0: Watchdog detected hard LOCKUP on cpu 1

but with all 7, it appears to function. And I have also tested without patch 6
(clock ordering), and things appear to function as well.

My understanding of the problem is as follows: previously I have used a device tree
that specified

   resets = <&cpg 0xd2>, <&cpg 0xd1>, <&cpg 0xd3>;
   reset-names = "vresetn", "aresetn", "hresetn";

while the order in the driver is:

   vresetn
   aresetn
   hresetn

and given that the bulk reset api asserts in order and deasserts in reverse order,
this would be

   assert: 0xd2 -> 0xd1 -> 0xd3
   deassert: 0xd3 -> 0xd1 -> 0xd2

whereas this patch series has the order

   resets = <&cpg 0xd3>, <&cpg 0xd1>, <&cpg 0xd2>;
   reset-names = "vresetn", "aresetn", "hresetn";

so the ordering is as follows

   assert: 0xd3 -> 0xd1 -> 0xd2
   deassert: 0xd2 -> 0xd1 -> 0xd3

meaning that the order is effectively reversed compared to the working configuration.

However, by sequencing them in the driver, the ordering is:

   assert: hresetn -> aresetn -> vresetn
           0xd2    -> 0xd1    -> 0xd3
   deassert: vresetn -> aresetn -> hresetn
             0xd3    -> 0xd1    -> 0xd2

which restores the working order.

Given that `reset_control_bulk_{de,}assert()` very clearly document the order
of operations. I would also be in favor of simply reordering `mali_c55_reset_names`,
as suggested in https://lore.kernel.org/linux-media/CA+V-a8vEub2y2gvXp8jkjVHOGuj1Eqkbq75t8Nezz95iidtL3Q@mail.gmail.com/#t


Regards,
Barnabás Pőcze

> - Match the call order from the reported DT swap using named handles.
> - Link to v4: https://patch.msgid.link/20261012-mali-c55-renesas-dts-v4-0-c410e280bf2d@kernel.org
> 
> Changes in v4:
> - Provide interrupt names in both bindings, their examples and SoC nodes.
> - Use Renesas RZ/V2H interrupt numbers in the binding examples.
> - Link to v3: https://patch.msgid.link/20260928-mali-c55-renesas-dts-v3-0-2cf7eb746ebb@kernel.org
> 
> Changes in v3:
> - Correct the ISP video and register clock/reset mappings by swapping
>    vclk/hclk and vresetn/hresetn.
> - Add an optional ISP power-domain binding and attach the RZ/V2H ISP
>    to the CPG power domain.
> - Link to v2: https://patch.msgid.link/20260925-mali-c55-renesas-dts-v2-0-69f728a474a2@kernel.org
> 
> Changes in v2:
> - Add separate IVC and ISP binding patches describing the optional IVC
>    frame-start/frame-stop completion and ISP DMA line-tick IRQs.
>    Show all six IRQs in the examples using consecutive mock numbers.
> - Add the IVC frame-start/stop and ISP DMA line-tick interrupt lines
>    using the confirmed SPI assignments, addressing Geert's IRQ review.
> - Correct the IVC and ISP register sizes to 64 KiB and 512 KiB,
>    respectively, as requested by Geert. GPV_VIDEO0 is a separate bus
>    interconnect region.
> - Compact the clock and reset properties and remove blank lines between
>    properties, following Geert's review.
> - Link to v1: https://patch.msgid.link/20260922-mali-c55-renesas-dts-v1-0-cd63cdb51033@kernel.org
> 
> ---
> Daniel Scally (2):
>        arm64: dts: renesas: r9a09g057: Add IVC and ISP nodes
>        arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Add ISP and IVC nodes
> 
> Linus Walleij (5):
>        dt-bindings: media: renesas,r9a09g057-ivc: Describe additional interrupts
>        dt-bindings: media: arm,mali-c55: Describe DMA line-tick interrupts
>        dt-bindings: media: arm,mali-c55: Add power domain
>        [RFC] media: mali-c55: Sequence clocks explicitly
>        [RFC] media: mali-c55: Sequence resets explicitly
> 
>   .../devicetree/bindings/media/arm,mali-c55.yaml    |  27 +++-
>   .../bindings/media/renesas,r9a09g057-ivc.yaml      |  22 +++-
>   arch/arm64/boot/dts/renesas/r9a09g057.dtsi         |  47 +++++++
>   .../boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts    |   8 ++
>   .../media/platform/arm/mali-c55/mali-c55-common.h  |  11 +-
>   .../media/platform/arm/mali-c55/mali-c55-core.c    | 136 +++++++++++++++------
>   6 files changed, 205 insertions(+), 46 deletions(-)
> ---
> base-commit: cee9395acd8043be0644b25c34bfa86623f2b935
> change-id: 20260922-mali-c55-renesas-dts-74d4727f59e5
> 
> Best regards,
> --
> Linus Walleij <linusw@kernel.org>

Re: [PATCH RFC v5 7/7] media: mali-c55: Sequence resets explicitly

[Linus Walleij]

Hi Prabhakar,

thanks a lot for your help!

On Tue, Nov 3, 2026 at 2:47 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:

> I tested on the RZ/V2H EVK with the clocks and DT left untouched,
> changing only the reset order.
>
> The hang comes from the reset assert order in __mali_c55_power_off().
> Asserting vresetn (the ISP core reset per the RZ/V2H manual) before
> hresetn/aresetn wedges the ISP. The next power-on then stalls on its
> first register access. The deassert order doesn't matter.

OK I will drop the clock patch and keep this one.

> Asserting h->a->v (deasserting v->a->h) passes repeated runtime-PM
> cycles and also works with the IVC enabled. So 7/7 gives the right
> reset sequence, 6/7 isn't needed for this, and the existing DT mapping
> (0xd3 = vresetn = ISP core reset) is correct.

So this is a Tested-by for this patch?

> A smaller alternative keeps the bulk API and only reorders the names:

I guess that works, but I'm not sure the reset bulk API in the
kernel guarantees any order, so we better keep this patch as-is if
it works so we explicitly show users that this is critical.

Yours,
Linus Walleij

Re: [PATCH RFC v5 7/7] media: mali-c55: Sequence resets explicitly

[Jacopo Mondi]

Hi Linus

On Thu, Nov 05, 2026 at 09:58:09AM +0100, Linus Walleij wrote:
> Hi Prabhakar,
>
> thanks a lot for your help!
>
> On Tue, Nov 3, 2026 at 2:47 PM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
>
> > I tested on the RZ/V2H EVK with the clocks and DT left untouched,
> > changing only the reset order.
> >
> > The hang comes from the reset assert order in __mali_c55_power_off().
> > Asserting vresetn (the ISP core reset per the RZ/V2H manual) before
> > hresetn/aresetn wedges the ISP. The next power-on then stalls on its
> > first register access. The deassert order doesn't matter.
>
> OK I will drop the clock patch and keep this one.
>
> > Asserting h->a->v (deasserting v->a->h) passes repeated runtime-PM
> > cycles and also works with the IVC enabled. So 7/7 gives the right
> > reset sequence, 6/7 isn't needed for this, and the existing DT mapping
> > (0xd3 = vresetn = ISP core reset) is correct.
>
> So this is a Tested-by for this patch?
>
> > A smaller alternative keeps the bulk API and only reorders the names:
>
> I guess that works, but I'm not sure the reset bulk API in the
> kernel guarantees any order, so we better keep this patch as-is if

I was under the same impression as I have memories of quite some
conversations around this and I recall a workqueue was used to
schedule bulk reset operations.

Now that I re-looked at the implementation of
reset_control_bulk_deassert() and its history I don't see any trace of
it and the documentation says

 * Deassert the reset lines for all provided reset controls, in reverse order.

Was I hallucinating when I first suggested no ordering was guaranteed ?


> it works so we explicitly show users that this is critical.
>
> Yours,
> Linus Walleij

Re: [PATCH RFC v5 7/7] media: mali-c55: Sequence resets explicitly

[Linus Walleij]

On Thu, Nov 5, 2026 at 11:10 AM Jacopo Mondi
<jacopo.mondi@ideasonboard.com> wrote:
> On Thu, Nov 05, 2026 at 09:58:09AM +0100, Linus Walleij wrote:
> > Hi Prabhakar,
> >
> > thanks a lot for your help!
> >
> > On Tue, Nov 3, 2026 at 2:47 PM Lad, Prabhakar
> > <prabhakar.csengg@gmail.com> wrote:
> >
> > > I tested on the RZ/V2H EVK with the clocks and DT left untouched,
> > > changing only the reset order.
> > >
> > > The hang comes from the reset assert order in __mali_c55_power_off().
> > > Asserting vresetn (the ISP core reset per the RZ/V2H manual) before
> > > hresetn/aresetn wedges the ISP. The next power-on then stalls on its
> > > first register access. The deassert order doesn't matter.
> >
> > OK I will drop the clock patch and keep this one.
> >
> > > Asserting h->a->v (deasserting v->a->h) passes repeated runtime-PM
> > > cycles and also works with the IVC enabled. So 7/7 gives the right
> > > reset sequence, 6/7 isn't needed for this, and the existing DT mapping
> > > (0xd3 = vresetn = ISP core reset) is correct.
> >
> > So this is a Tested-by for this patch?
> >
> > > A smaller alternative keeps the bulk API and only reorders the names:
> >
> > I guess that works, but I'm not sure the reset bulk API in the
> > kernel guarantees any order, so we better keep this patch as-is if
>
> I was under the same impression as I have memories of quite some
> conversations around this and I recall a workqueue was used to
> schedule bulk reset operations.
>
> Now that I re-looked at the implementation of
> reset_control_bulk_deassert() and its history I don't see any trace of
> it and the documentation says
>
>  * Deassert the reset lines for all provided reset controls, in reverse order.
>
> Was I hallucinating when I first suggested no ordering was guaranteed ?

No idea... Lad showed me it is guaranteed so I sent a considerably
less intrusive patch now, check it out!

Yours,
Linus Walleij