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From: Sebastian Reichel <sebastian.reichel@collabora.com>
To: aiyengar1990@gmail.com
Cc: Will Deacon <will@kernel.org>,
	Robin Murphy <robin.murphy@arm.com>,
	 "Joerg Roedel (AMD)" <joro@8bytes.org>,
	Rob Herring <robh@kernel.org>,
	 Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	 Heiko Stuebner <heiko@sntech.de>,
	Niklas Cassel <cassel@kernel.org>,
	 linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev,
	devicetree@vger.kernel.org,  linux-kernel@vger.kernel.org,
	linux-rockchip@lists.infradead.org
Subject: Re: [PATCH 2/5] dt-bindings: iommu: arm,smmu-v3: allow clocks
Date: Tue, 10 Nov 2026 15:55:09 +0100	[thread overview]
Message-ID: <avMv7fQuNJZpE_zr@venus> (raw)
In-Reply-To: <20261110-smmu-v3-pcie-pd-v1-2-628819ca44b9@gmail.com>

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Hi,

On Tue, Nov 10, 2026 at 07:11:49AM +0000, Arun Iyengar via B4 Relay wrote:
> From: Arun Iyengar <aiyengar1990@gmail.com>
> 
> Some SoCs feed the SMMUv3 from a clock that the OS controls. On the
> Rockchip RK3588 the MMU-600 for PCIe runs from ACLK_MMU_PCIE, whose only
> other consumers are the PCIe controllers. When no PCIe controller is
> enabled, the clock framework gates it as unused, and the SMMU can no
> longer be accessed.
> 
> Allow up to four clocks, so that such a clock can be described and held
> by the SMMU driver.
> 
> Signed-off-by: Arun Iyengar <aiyengar1990@gmail.com>
> ---

This does not explain why a maximum of four clocks is allowed.

Greetings,

-- Sebastian

>  Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> index c8f22dfdb1db..f8a74730667c 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> @@ -63,6 +63,13 @@ properties:
>  
>    msi-parent: true
>  
> +  clocks:
> +    minItems: 1
> +    maxItems: 4
> +    description:
> +      Clocks needed to access the SMMU registers and to keep its translation
> +      units running, if they are not managed by firmware.
> +
>    power-domains:
>      maxItems: 1
>  
> 
> -- 
> 2.55.0
> 
> 
> 

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WARNING: multiple messages have this Message-ID (diff)
From: Sebastian Reichel <sebastian.reichel@collabora.com>
To: aiyengar1990@gmail.com
Cc: Will Deacon <will@kernel.org>,
	Robin Murphy <robin.murphy@arm.com>,
	 "Joerg Roedel (AMD)" <joro@8bytes.org>,
	Rob Herring <robh@kernel.org>,
	 Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	 Heiko Stuebner <heiko@sntech.de>,
	Niklas Cassel <cassel@kernel.org>,
	 linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev,
	devicetree@vger.kernel.org,  linux-kernel@vger.kernel.org,
	linux-rockchip@lists.infradead.org
Subject: Re: [PATCH 2/5] dt-bindings: iommu: arm,smmu-v3: allow clocks
Date: Tue, 10 Nov 2026 15:55:09 +0100	[thread overview]
Message-ID: <avMv7fQuNJZpE_zr@venus> (raw)
In-Reply-To: <20261110-smmu-v3-pcie-pd-v1-2-628819ca44b9@gmail.com>


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Hi,

On Tue, Nov 10, 2026 at 07:11:49AM +0000, Arun Iyengar via B4 Relay wrote:
> From: Arun Iyengar <aiyengar1990@gmail.com>
> 
> Some SoCs feed the SMMUv3 from a clock that the OS controls. On the
> Rockchip RK3588 the MMU-600 for PCIe runs from ACLK_MMU_PCIE, whose only
> other consumers are the PCIe controllers. When no PCIe controller is
> enabled, the clock framework gates it as unused, and the SMMU can no
> longer be accessed.
> 
> Allow up to four clocks, so that such a clock can be described and held
> by the SMMU driver.
> 
> Signed-off-by: Arun Iyengar <aiyengar1990@gmail.com>
> ---

This does not explain why a maximum of four clocks is allowed.

Greetings,

-- Sebastian

>  Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> index c8f22dfdb1db..f8a74730667c 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
> @@ -63,6 +63,13 @@ properties:
>  
>    msi-parent: true
>  
> +  clocks:
> +    minItems: 1
> +    maxItems: 4
> +    description:
> +      Clocks needed to access the SMMU registers and to keep its translation
> +      units running, if they are not managed by firmware.
> +
>    power-domains:
>      maxItems: 1
>  
> 
> -- 
> 2.55.0
> 
> 
> 

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  parent reply	other threads:[~2026-11-10 14:55 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-10  7:11 [PATCH 0/5] iommu/arm-smmu-v3: power domain and clock of the RK3588 PCIe SMMU Arun Iyengar
2026-11-10  7:11 ` Arun Iyengar via B4 Relay
2026-11-10  7:11 ` Arun Iyengar via B4 Relay
2026-11-10  7:11 ` [PATCH 1/5] dt-bindings: iommu: arm,smmu-v3: allow a power domain Arun Iyengar
2026-11-10  7:11   ` Arun Iyengar via B4 Relay
2026-11-10  7:11   ` Arun Iyengar via B4 Relay
2026-11-10 14:51   ` Sebastian Reichel
2026-11-10 14:51     ` Sebastian Reichel
2026-11-10  7:11 ` [PATCH 2/5] dt-bindings: iommu: arm,smmu-v3: allow clocks Arun Iyengar
2026-11-10  7:11   ` Arun Iyengar via B4 Relay
2026-11-10  7:11   ` Arun Iyengar via B4 Relay
2026-11-10  7:23   ` sashiko-bot
2026-11-10 14:55   ` Sebastian Reichel [this message]
2026-11-10 14:55     ` Sebastian Reichel
2026-11-10  7:11 ` [PATCH 3/5] iommu/arm-smmu-v3: enable optional clocks Arun Iyengar
2026-11-10  7:11   ` Arun Iyengar via B4 Relay
2026-11-10  7:11   ` Arun Iyengar via B4 Relay
2026-11-10  7:26   ` sashiko-bot
2026-11-10 14:53   ` Sebastian Reichel
2026-11-10 14:53     ` Sebastian Reichel
2026-11-10  7:11 ` [PATCH 4/5] arm64: dts: rockchip: add the PCIe power domain to the RK3588 PCIe SMMU Arun Iyengar
2026-11-10  7:11   ` Arun Iyengar via B4 Relay
2026-11-10  7:11   ` Arun Iyengar via B4 Relay
2026-11-10 15:00   ` Sebastian Reichel
2026-11-10 15:00     ` Sebastian Reichel
2026-11-11  6:53   ` Shawn Lin
2026-11-11  6:53     ` Shawn Lin
2026-11-10  7:11 ` [PATCH 5/5] arm64: dts: rockchip: add the clock of " Arun Iyengar
2026-11-10  7:11   ` Arun Iyengar via B4 Relay
2026-11-10  7:11   ` Arun Iyengar via B4 Relay
2026-11-10 15:07   ` Sebastian Reichel
2026-11-10 15:07     ` Sebastian Reichel
2026-11-10  8:40 ` [PATCH 0/5] iommu/arm-smmu-v3: power domain and " Shawn Lin
2026-11-10  8:40   ` Shawn Lin
2026-11-10  8:49   ` Heiko Stübner
2026-11-10  8:49     ` Heiko Stübner
2026-11-11  8:02     ` Shawn Lin
2026-11-11  8:02       ` Shawn Lin
2026-11-11  9:53       ` Heiko Stübner
2026-11-11  9:53         ` Heiko Stübner
2026-11-12  3:50         ` Sebastian Reichel
2026-11-12  3:50           ` Sebastian Reichel
2026-11-10 15:13 ` Sebastian Reichel
2026-11-10 15:13   ` Sebastian Reichel

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