From: Jim MacArthur <jim.macarthur@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH for-11.2 2/4] hw/intc/arm_gicv5: Free memory in finalize
Date: Tue, 10 Nov 2026 16:34:51 +0000 [thread overview]
Message-ID: <avNHq9ukmSPmqPXW@linaro.org> (raw)
In-Reply-To: <20261103172616.2400758-3-peter.maydell@linaro.org>
On Tue, Nov 03, 2026 at 05:26:14PM +0000, Peter Maydell wrote:
> The GICv5 allocates memory and creates hashtables during realize and
> as part of its operation. Free those resources in finalize.
>
> Since the GICv5 is created at QEMU startup and remains in existence
> for the lifetime of the process, this isn't an in-practice leak,
> only a theoretical one.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> hw/intc/arm_gicv5.c | 11 +++++++++++
> hw/intc/arm_gicv5_common.c | 3 +++
> 2 files changed, 14 insertions(+)
>
> diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c
> index d0a8574916b..fd6456cd8aa 100644
> --- a/hw/intc/arm_gicv5.c
> +++ b/hw/intc/arm_gicv5.c
> @@ -1970,6 +1970,17 @@ static void gicv5_init(Object *obj)
>
> static void gicv5_finalize(Object *obj)
> {
> + GICv5 *s = ARM_GICV5(obj);
> +
> + for (int i = 0; i < NUM_GICV5_DOMAINS; i++) {
> + GHashTable *ht = s->phys_lpi_config[i].lpi_cache;
> +
> + if (ht) {
> + g_hash_table_destroy(ht);
> + }
> +
> + g_free(s->hppi[i]);
> + }
> }
>
> static void gicv5_class_init(ObjectClass *oc, const void *data)
> diff --git a/hw/intc/arm_gicv5_common.c b/hw/intc/arm_gicv5_common.c
> index 2920b11cc39..cfadfee4f05 100644
> --- a/hw/intc/arm_gicv5_common.c
> +++ b/hw/intc/arm_gicv5_common.c
> @@ -112,6 +112,9 @@ static void gicv5_common_init(Object *obj)
>
> static void gicv5_common_finalize(Object *obj)
> {
> + GICv5Common *cs = ARM_GICV5_COMMON(obj);
> +
> + g_free(cs->spi);
> }
>
Reviewed-by: Jim MacArthur <jim.macarthur@linaro.org>
next prev parent reply other threads:[~2026-11-10 16:35 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-03 17:26 [PATCH for-11.2 0/4] hw/intc/arm_gicv5: Misc minor fixes Peter Maydell
2026-11-03 17:26 ` [PATCH for-11.2 1/4] hw/intc/arm_gicv5: Use cached IRS_IST_BASER.VALID state Peter Maydell
2026-11-10 16:23 ` Jim MacArthur
2026-11-03 17:26 ` [PATCH for-11.2 2/4] hw/intc/arm_gicv5: Free memory in finalize Peter Maydell
2026-11-10 16:34 ` Jim MacArthur [this message]
2026-11-03 17:26 ` [PATCH for-11.2 3/4] target/arm: Only allow GICv5 on CPUs without AArch32 at EL1..3 Peter Maydell
2026-11-04 12:12 ` Philippe Mathieu-Daudé
2026-11-03 17:26 ` [PATCH for-11.2 4/4] hw/intc/arm_gicv5: Use correct type for value in lpi_cache_get_hppi() Peter Maydell
2026-11-03 17:49 ` Peter Maydell
2026-11-04 11:24 ` Philippe Mathieu-Daudé
2026-11-04 11:46 ` Peter Maydell
2026-11-04 11:59 ` Philippe Mathieu-Daudé
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