From: Jim MacArthur <jim.macarthur@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: Re: [PATCH for-11.2 1/4] hw/intc/arm_gicv5: Use cached IRS_IST_BASER.VALID state
Date: Tue, 10 Nov 2026 16:23:25 +0000 [thread overview]
Message-ID: <avNE_fHfwLISriHr@linaro.org> (raw)
In-Reply-To: <20261103172616.2400758-2-peter.maydell@linaro.org>
On Tue, Nov 03, 2026 at 05:26:13PM +0000, Peter Maydell wrote:
> When the guest writes to IRS_IST_BASER we effectively cache the value
> of the VALID bit in the GICv5ISTConfig valid field entry. In a few
> places we check whether the IST is valid by doing a bit extract on
> the register value; switch those to look at cfg->structure instead.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> hw/intc/arm_gicv5.c | 7 +++----
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c
> index 5d0a50ab6aa..d0a8574916b 100644
> --- a/hw/intc/arm_gicv5.c
> +++ b/hw/intc/arm_gicv5.c
> @@ -1222,8 +1222,7 @@ static void irs_map_l2_istr_write(GICv5 *s, GICv5Domain domain, uint64_t value)
> uint64_t l1_iste;
> MemTxResult res;
>
> - if (!FIELD_EX64(cs->irs_ist_baser[domain], IRS_IST_BASER, VALID) ||
> - !cfg->structure) {
> + if (!cfg->valid || !cfg->structure) {
> /* WI if no IST set up or it is not 2-level */
> return;
> }
> @@ -1293,7 +1292,7 @@ static void irs_ist_baser_write(GICv5 *s, GICv5Domain domain, uint64_t value)
> {
> GICv5Common *cs = ARM_GICV5_COMMON(s);
>
> - if (FIELD_EX64(cs->irs_ist_baser[domain], IRS_IST_BASER, VALID)) {
> + if (s->phys_lpi_config[domain].valid) {
> /* If VALID is set, ADDR is RO and we can only update VALID */
> bool valid = FIELD_EX64(value, IRS_IST_BASER, VALID);
> if (valid) {
> @@ -1604,7 +1603,7 @@ static bool config_writel(GICv5 *s, GICv5Domain domain, hwaddr offset,
> deposit64(cs->irs_ist_baser[domain], 32, 32, data));
> return true;
> case A_IRS_IST_CFGR:
> - if (FIELD_EX64(cs->irs_ist_baser[domain], IRS_IST_BASER, VALID)) {
> + if (s->phys_lpi_config[domain].valid) {
> qemu_log_mask(LOG_GUEST_ERROR,
> "guest tried to write IRS_IST_CFGR for %s config frame "
> "while IST_BASER.VALID set\n", domain_name[domain]);
That makes sense.
Reviewed-by: Jim MacArthur <jim.macarthur@linaro.org>
next prev parent reply other threads:[~2026-11-10 16:23 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-03 17:26 [PATCH for-11.2 0/4] hw/intc/arm_gicv5: Misc minor fixes Peter Maydell
2026-11-03 17:26 ` [PATCH for-11.2 1/4] hw/intc/arm_gicv5: Use cached IRS_IST_BASER.VALID state Peter Maydell
2026-11-10 16:23 ` Jim MacArthur [this message]
2026-11-03 17:26 ` [PATCH for-11.2 2/4] hw/intc/arm_gicv5: Free memory in finalize Peter Maydell
2026-11-10 16:34 ` Jim MacArthur
2026-11-03 17:26 ` [PATCH for-11.2 3/4] target/arm: Only allow GICv5 on CPUs without AArch32 at EL1..3 Peter Maydell
2026-11-04 12:12 ` Philippe Mathieu-Daudé
2026-11-03 17:26 ` [PATCH for-11.2 4/4] hw/intc/arm_gicv5: Use correct type for value in lpi_cache_get_hppi() Peter Maydell
2026-11-03 17:49 ` Peter Maydell
2026-11-04 11:24 ` Philippe Mathieu-Daudé
2026-11-04 11:46 ` Peter Maydell
2026-11-04 11:59 ` Philippe Mathieu-Daudé
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