* [PATCH v6 0/2] Extend CPER records with RAS info queue data
@ 2026-11-06 18:59 Badal Nilawar
2026-11-06 18:59 ` [PATCH v6 1/2] drm/xe/xe_ras: Add support to retrieve " Badal Nilawar
` (4 more replies)
0 siblings, 5 replies; 8+ messages in thread
From: Badal Nilawar @ 2026-11-06 18:59 UTC (permalink / raw)
To: intel-xe
Cc: anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio, raag.jadav,
riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
himal.prasad.ghimiray, arvind.yadav, syed.abdul.muqthyar.ahmed,
nitin.r.gote, matthew.d.roper
This series continues the RAS info queue support from
https://patchwork.freedesktop.org/series/169692/#rev5
Badal Nilawar (2):
drm/xe/xe_ras: Add support to retrieve info queue data
drm/xe/cper: Prepare Intel CPER info records
drivers/gpu/drm/xe/xe_cper.c | 287 +++++++++++++++++-
drivers/gpu/drm/xe/xe_cper_types.h | 59 +++-
drivers/gpu/drm/xe/xe_ras.c | 140 +++++++++
drivers/gpu/drm/xe/xe_ras.h | 4 +-
drivers/gpu/drm/xe/xe_ras_types.h | 117 ++++++-
drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h | 2 +
6 files changed, 591 insertions(+), 18 deletions(-)
--
2.56.0
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v6 1/2] drm/xe/xe_ras: Add support to retrieve info queue data
2026-11-06 18:59 [PATCH v6 0/2] Extend CPER records with RAS info queue data Badal Nilawar
@ 2026-11-06 18:59 ` Badal Nilawar
2026-11-10 10:53 ` Raag Jadav
2026-11-06 18:59 ` [PATCH v6 2/2] drm/xe/cper: Prepare Intel CPER info records Badal Nilawar
` (3 subsequent siblings)
4 siblings, 1 reply; 8+ messages in thread
From: Badal Nilawar @ 2026-11-06 18:59 UTC (permalink / raw)
To: intel-xe
Cc: anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio, raag.jadav,
riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
himal.prasad.ghimiray, arvind.yadav, syed.abdul.muqthyar.ahmed,
nitin.r.gote, matthew.d.roper
Retrieve the RAS info queue data, in multiple chunks, and assemble it into
a flat buffer.
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
v6:
- Replace destination buffer checks with xe_assert() (Raag)
- Extract get_first_chunk() and get_remaining_chunks() helpers (Raag)
---
drivers/gpu/drm/xe/xe_ras.c | 140 ++++++++++++++++++
drivers/gpu/drm/xe/xe_ras.h | 4 +-
drivers/gpu/drm/xe/xe_ras_types.h | 91 +++++++++++-
drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h | 2 +
4 files changed, 234 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index 2c01c183d02b..7f218ab2bd1b 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -1106,6 +1106,146 @@ int xe_ras_set_threshold(struct xe_device *xe, u8 severity, u8 component, u32 th
return 0;
}
+static int get_info_queue(struct xe_device *xe,
+ struct xe_ras_get_info_queue_request *request,
+ struct xe_ras_get_info_queue_response *response)
+{
+ struct xe_sysctrl_mailbox_command command = {0};
+ const struct xe_ras_info_queue_header *hdr;
+ size_t rlen;
+ int ret;
+
+ xe_sysctrl_create_command(&command, XE_SYSCTRL_GROUP_GFSP, XE_SYSCTRL_CMD_GET_INFO_QUEUE,
+ request, sizeof(*request), response, sizeof(*response));
+
+ ret = xe_sysctrl_send_command(&xe->sc, &command, &rlen);
+ if (ret) {
+ xe_err(xe, "sysctrl: failed to get info queue %d\n", ret);
+ return ret;
+ }
+
+ if (rlen != sizeof(*response)) {
+ xe_err(xe, "sysctrl: unexpected get info queue response length %zu (expected %zu)\n",
+ rlen, sizeof(*response));
+ return -EIO;
+ }
+
+ ret = ras_status_to_errno(response->status);
+ if (ret) {
+ xe_err(xe, "sysctrl: get info queue command failed with status %#x\n",
+ response->status);
+ return ret;
+ }
+
+ hdr = &response->queue_response.header;
+ xe_dbg(xe, "[RAS] info queue: total_size=%u chunk_offset=%u chunk_size=%u flags=0x%x num_headers=%u\n",
+ hdr->total_size, hdr->chunk_offset, hdr->chunk_size,
+ hdr->flags, hdr->num_headers);
+
+ return 0;
+}
+
+static bool chunk_is_valid(const struct xe_ras_info_queue_header *hdr,
+ u32 expected_offset, u32 dest_size)
+{
+ u32 end;
+
+ return hdr->chunk_offset == expected_offset &&
+ hdr->chunk_size && hdr->chunk_size <= XE_RAS_INFO_QUEUE_MAX_CHUNK_SIZE &&
+ !check_add_overflow(hdr->chunk_offset, hdr->chunk_size, &end) &&
+ end <= XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE && end <= dest_size;
+}
+
+static u32 get_first_chunk(struct xe_device *xe,
+ const struct xe_ras_get_counter_response *response,
+ u8 *dest_buf, u32 dest_size, u32 *flags)
+{
+ const struct xe_ras_info_queue_header *hdr = &response->first.header;
+
+ if (!chunk_is_valid(hdr, 0, dest_size)) {
+ xe_warn(xe, "[RAS]: invalid first info queue chunk (offset=%u size=%u, expected offset=%u)\n",
+ hdr->chunk_offset, hdr->chunk_size, 0);
+ return 0;
+ }
+
+ memcpy(dest_buf, response->first.data, hdr->chunk_size);
+ *flags = hdr->flags;
+
+ return hdr->chunk_size;
+}
+
+static u32 get_remaining_chunks(struct xe_device *xe,
+ const struct xe_ras_get_counter_response *response,
+ u8 *dest_buf, u32 dest_size, u32 offset, u32 flags)
+{
+ int ret;
+
+ while ((flags & XE_RAS_INFO_QUEUE_FLAG_MORE_DATA) && offset < dest_size) {
+ struct xe_ras_get_info_queue_request request = {};
+ struct xe_ras_get_info_queue_response queue_response = {};
+ struct xe_ras_info_queue_header *hdr;
+
+ request.queue_request.offset = offset;
+ request.queue_request.size = min(XE_RAS_INFO_QUEUE_MAX_CHUNK_SIZE,
+ dest_size - offset);
+ request.queue_request.session_id = response->counter;
+
+ ret = get_info_queue(xe, &request, &queue_response);
+ if (ret) {
+ xe_err(xe, "[RAS]: info queue drain aborted: fetch at offset=%u, ret = %d\n",
+ offset, ret);
+ return offset;
+ }
+
+ hdr = &queue_response.queue_response.header;
+
+ if (!chunk_is_valid(hdr, offset, dest_size)) {
+ xe_warn(xe, "[RAS]: invalid info queue chunk (offset=%u size=%u, expected offset=%u)\n",
+ hdr->chunk_offset, hdr->chunk_size, offset);
+ return offset;
+ }
+
+ memcpy(dest_buf + offset, queue_response.queue_response.data, hdr->chunk_size);
+ offset += hdr->chunk_size;
+ flags = hdr->flags;
+ }
+
+ return min(offset, response->first.header.total_size);
+}
+
+/**
+ * xe_ras_drain_info_queue() - Drain the full RAS info queue into a flat buffer
+ * @xe: xe device
+ * @response: counter response carrying the first embedded chunk
+ * @dest_buf: destination buffer supplied by the caller
+ * @dest_size: size of @dest_buf in bytes; also caps the total amount of data
+ * assembled from the info queue
+ *
+ * Copies the first chunk already embedded in @response, then loops
+ * issuing GET_INFO_QUEUE to fetch any remaining chunks until the queue
+ * signals no more data or a transport/bounds error is encountered. On
+ * transport or bounds errors the function stops and returns whatever has
+ * been assembled so far.
+ *
+ * Returns: Number of valid bytes written into @dest_buf.
+ */
+u32 xe_ras_drain_info_queue(struct xe_device *xe,
+ const struct xe_ras_get_counter_response *response,
+ u8 *dest_buf, u32 dest_size)
+{
+ u32 flags, offset;
+
+ xe_assert(xe, response->has_info_queue);
+ xe_assert(xe, dest_buf);
+ xe_assert(xe, dest_size);
+
+ offset = get_first_chunk(xe, response, dest_buf, dest_size, &flags);
+ if (!offset)
+ return 0;
+
+ return get_remaining_chunks(xe, response, dest_buf, dest_size, offset, flags);
+}
+
static ssize_t gpu_health_show(struct device *dev, struct device_attribute *attr, char *buf)
{
struct xe_ras_get_health_response response = {0};
diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h
index c44fa172011f..5bdac147098f 100644
--- a/drivers/gpu/drm/xe/xe_ras.h
+++ b/drivers/gpu/drm/xe/xe_ras.h
@@ -25,5 +25,7 @@ bool xe_ras_get_disable_vram_page_offline(struct xe_device *xe);
u32 xe_ras_get_max_pages(struct xe_device *xe);
int xe_ras_get_counter_response(struct xe_device *xe, const struct xe_ras_error_class *counter,
struct xe_ras_get_counter_response *response);
-
+u32 xe_ras_drain_info_queue(struct xe_device *xe,
+ const struct xe_ras_get_counter_response *response,
+ u8 *dest_buf, u32 dest_size);
#endif
diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
index a86f9d2b8c92..67d57182aac9 100644
--- a/drivers/gpu/drm/xe/xe_ras_types.h
+++ b/drivers/gpu/drm/xe/xe_ras_types.h
@@ -19,6 +19,10 @@
#define XE_RAS_MEMORY_POISON BIT(2)
#define XE_RAS_MEMORY_DATA_PARITY BIT(5)
+#define XE_RAS_INFO_QUEUE_MAX_CHUNK_SIZE 200
+#define XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE 5120
+#define XE_RAS_INFO_QUEUE_FLAG_MORE_DATA 0x02
+
/**
* enum xe_ras_page_action - Page offline actions for page offline request
*
@@ -110,6 +114,83 @@ struct xe_ras_threshold_crossed {
struct xe_ras_error_class counters[XE_RAS_NUM_COUNTERS];
} __packed;
+/**
+ * struct xe_ras_info_queue_header - Metadata for large info queue data transfers
+ *
+ * Provides chunk metadata for commands that support extended info queue
+ * functionality. Used when the total data exceeds a single mailbox response.
+ */
+struct xe_ras_info_queue_header {
+ /** @total_size: Total size of the complete info queue data in bytes */
+ u32 total_size;
+ /** @chunk_offset: Offset of this chunk within the total data in bytes */
+ u32 chunk_offset;
+ /** @chunk_size: Size of the data in this chunk in bytes */
+ u32 chunk_size;
+ /** @reserved0: Reserved for future use */
+ u32 reserved0;
+ /** @flags: Info queue control flags (XE_RAS_INFO_QUEUE_FLAG_*) */
+ u32 flags:8;
+ /** @reserved1: Reserved for future use */
+ u32 reserved1:4;
+ /** @num_headers: Number of detailed counter headers at start of the data */
+ u32 num_headers:5;
+ /** @reserved2: Reserved for future use */
+ u32 reserved2:15;
+ /** @reserved3: Reserved for future use */
+ u32 reserved3;
+} __packed;
+
+/**
+ * struct xe_ras_info_queue_data_request - Request for a specific chunk of info queue data
+ *
+ * Allows the driver to request continuation of large info queue transfers
+ * by specifying an offset and size within the full data set.
+ */
+struct xe_ras_info_queue_data_request {
+ /** @offset: Byte offset of the requested data chunk */
+ u32 offset;
+ /** @size: Maximum size of the requested chunk in bytes */
+ u32 size;
+ /** @session_id: Session ID to correlate multi-chunk transfers */
+ struct xe_ras_error_class session_id;
+ /** @reserved: Reserved for future use */
+ u32 reserved;
+} __packed;
+
+/**
+ * struct xe_ras_info_queue_data_response - Generic response for commands with info queues
+ *
+ * Standard response format for any command that returns an info queue
+ * payload. May be embedded in a command-specific response structure.
+ */
+struct xe_ras_info_queue_data_response {
+ /** @header: Info queue metadata for this chunk */
+ struct xe_ras_info_queue_header header;
+ /** @data: Info queue data for this chunk */
+ u8 data[XE_RAS_INFO_QUEUE_MAX_CHUNK_SIZE];
+} __packed;
+
+/**
+ * struct xe_ras_get_info_queue_request - Request for XE_SYSCTRL_CMD_GET_INFO_QUEUE
+ */
+struct xe_ras_get_info_queue_request {
+ /** @queue_request: Info queue request parameters */
+ struct xe_ras_info_queue_data_request queue_request;
+ /** @reserved: Reserved for future use */
+ u32 reserved[16];
+} __packed;
+
+/**
+ * struct xe_ras_get_info_queue_response - Response for XE_SYSCTRL_CMD_GET_INFO_QUEUE
+ */
+struct xe_ras_get_info_queue_response {
+ /** @status: Status of the retrieval operation */
+ u32 status;
+ /** @queue_response: Info queue data chunk */
+ struct xe_ras_info_queue_data_response queue_response;
+} __packed;
+
/**
* struct xe_ras_get_counter_request - Request structure for get counter
*/
@@ -132,8 +213,14 @@ struct xe_ras_get_counter_response {
u64 timestamp;
/** @threshold: Threshold value for the counter */
u32 threshold;
- /** @reserved: Reserved */
- u32 reserved[57];
+ /** @reserved: Reserved for future use */
+ u32 reserved:9;
+ /** @has_info_queue: Set if info queue is available */
+ u32 has_info_queue:1;
+ /** @reserved1: Reserved for future use */
+ u32 reserved1:22;
+ /** @first: First info queue chunk, if @has_info_queue is set */
+ struct xe_ras_info_queue_data_response first;
} __packed;
/**
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
index cdacceebca06..50b1d9abaf1f 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
+++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
@@ -37,6 +37,7 @@ enum xe_sysctrl_group {
* @XE_SYSCTRL_CMD_GET_OFFLINE_QUEUE: Retrieve list of offlined queued pages from firmware
* @XE_SYSCTRL_CMD_GET_HEALTH: Retrieve gpu health
* @XE_SYSCTRL_CMD_SET_HEALTH: Set gpu health
+ * @XE_SYSCTRL_CMD_GET_INFO_QUEUE: Retrieve a chunk of info queue data
*/
enum xe_sysctrl_gfsp_cmd {
XE_SYSCTRL_CMD_GET_SOC_ERROR = 0x01,
@@ -50,6 +51,7 @@ enum xe_sysctrl_gfsp_cmd {
XE_SYSCTRL_CMD_GET_OFFLINE_QUEUE = 0x0A,
XE_SYSCTRL_CMD_GET_HEALTH = 0x0B,
XE_SYSCTRL_CMD_SET_HEALTH = 0x0C,
+ XE_SYSCTRL_CMD_GET_INFO_QUEUE = 0x0D,
};
/**
--
2.56.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v6 2/2] drm/xe/cper: Prepare Intel CPER info records
2026-11-06 18:59 [PATCH v6 0/2] Extend CPER records with RAS info queue data Badal Nilawar
2026-11-06 18:59 ` [PATCH v6 1/2] drm/xe/xe_ras: Add support to retrieve " Badal Nilawar
@ 2026-11-06 18:59 ` Badal Nilawar
2026-11-11 10:36 ` Raag Jadav
2026-11-06 19:08 ` ✓ CI.KUnit: success for Extend CPER records with RAS info queue data Patchwork
` (2 subsequent siblings)
4 siblings, 1 reply; 8+ messages in thread
From: Badal Nilawar @ 2026-11-06 18:59 UTC (permalink / raw)
To: intel-xe
Cc: anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio, raag.jadav,
riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
himal.prasad.ghimiray, arvind.yadav, syed.abdul.muqthyar.ahmed,
nitin.r.gote, matthew.d.roper
The RAS info queue contains error logs for detail counters, or dynamic
counter headers followed by error logs for aggregate counters.
Build CPER info records from the queue data, converting each error log
into an CPER event. For aggregate counters, group logs by their dynamic
counter header and build one info record per header.
Emit a CPER record for each generated info record.
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
v6:
- Reintroduce event_ prefixes
- %s/einfo/info/
- Split cper_prepare_einfo() into queue-fetch and info-array construction helpers (Raag)
- Rename the dynamic counter header's count field to error_count (Raag)
---
drivers/gpu/drm/xe/xe_cper.c | 287 +++++++++++++++++++++++++++--
drivers/gpu/drm/xe/xe_cper_types.h | 59 +++++-
drivers/gpu/drm/xe/xe_ras_types.h | 26 +++
3 files changed, 357 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
index bb90030bcd2d..9e2d4240200e 100644
--- a/drivers/gpu/drm/xe/xe_cper.c
+++ b/drivers/gpu/drm/xe/xe_cper.c
@@ -89,7 +89,7 @@ static u64 cper_timestamp_now(void)
static void cper_init_intel_hdr(struct xe_device *xe, const struct xe_ras_error_class *counter,
u64 first_timestamp, u32 sig_id, u32 error_count,
- struct xe_cper_intel_hdr *ihdr)
+ u32 info_size, struct xe_cper_intel_hdr *ihdr)
{
ihdr->counter = *counter;
ihdr->validation_bits |= XE_CPER_VALID_LOCATION;
@@ -106,6 +106,7 @@ static void cper_init_intel_hdr(struct xe_device *xe, const struct xe_ras_error_
}
ihdr->error_count = error_count;
+ ihdr->info_log_size = info_size;
strscpy(ihdr->pci_bdf, pci_name(to_pci_dev(xe->drm.dev)), sizeof(ihdr->pci_bdf));
ihdr->validation_bits |= XE_CPER_VALID_PCI_BDF;
@@ -147,11 +148,11 @@ static void cper_init_record_hdr(struct xe_device *xe, u8 severity,
static void cper_init_section_desc(struct xe_device *xe, u8 severity,
struct cper_section_descriptor *sdesc,
- u32 einfo_len)
+ u32 info_len)
{
sdesc->section_offset = sizeof(struct cper_record_header) +
sizeof(struct cper_section_descriptor);
- sdesc->section_length = sizeof(struct xe_cper_intel_hdr) + einfo_len;
+ sdesc->section_length = sizeof(struct xe_cper_intel_hdr) + info_len;
sdesc->revision = CPER_SEC_REV;
sdesc->validation_bits = 0;
sdesc->section_type = INTEL_CPER_SECTION_ACCEL_GENERIC;
@@ -166,14 +167,14 @@ static void cper_init_section_desc(struct xe_device *xe, u8 severity,
static void cper_record_emit(struct xe_device *xe, u8 severity,
const guid_t *notification_type,
const struct xe_cper_intel_hdr *ihdr,
- const void *einfo, u32 einfo_len)
+ const void *info, u32 info_len)
{
struct cper_section_descriptor *sdesc;
struct xe_cper_nonstd_record *rec;
struct cper_record_header *rhdr;
u32 total_len;
- total_len = sizeof(struct xe_cper_nonstd_record) + einfo_len;
+ total_len = sizeof(struct xe_cper_nonstd_record) + info_len;
rec = kzalloc(total_len, GFP_KERNEL);
if (!rec)
return;
@@ -185,14 +186,14 @@ static void cper_record_emit(struct xe_device *xe, u8 severity,
cper_init_record_hdr(xe, severity, notification_type, rhdr, total_len);
/* Assemble the section descriptor (UEFI Appendix N.2.2) */
- cper_init_section_desc(xe, severity, sdesc, einfo_len);
+ cper_init_section_desc(xe, severity, sdesc, info_len);
/* Copy the Intel-specific section header */
rec->intel_hdr = *ihdr;
/* Append optional variable-length error info */
- if (einfo && einfo_len)
- memcpy((u8 *)rec + sizeof(*rec), einfo, einfo_len);
+ if (info && info_len)
+ memcpy((u8 *)rec + sizeof(*rec), info, info_len);
trace_xe_error_cper(xe, &rhdr->platform_id, &sdesc->fru_id, severity,
&rec->intel_hdr, total_len, (u8 *)rec);
@@ -200,6 +201,237 @@ static void cper_record_emit(struct xe_device *xe, u8 severity,
kfree(rec);
}
+static struct xe_cper_intel_info *
+build_info(const struct xe_ras_error_log *logs, u32 num_logs,
+ const struct xe_ras_error_class *counter, u32 error_count)
+{
+ struct xe_cper_intel_event *entry;
+ struct xe_cper_intel_info *info;
+ u32 queue_size, i;
+
+ queue_size = num_logs * XE_CPER_RAS_LOG_ENTRY_SIZE;
+ info = kzalloc_flex(*info, event_queue, queue_size);
+ if (!info)
+ return NULL;
+
+ info->error_count = error_count;
+ info->event_queue_size = queue_size;
+ info->event_queue_count = num_logs;
+ info->counter = *counter;
+
+ entry = (struct xe_cper_intel_event *)info->event_queue;
+ for (i = 0; i < num_logs; i++) {
+ entry->size = sizeof_field(struct xe_ras_error_log, details);
+ entry->timestamp = logs[i].timestamp;
+ memcpy(entry->metadata, logs[i].details, sizeof(logs[i].details));
+ entry = (void *)entry + XE_CPER_RAS_LOG_ENTRY_SIZE;
+ }
+
+ return info;
+}
+
+static void free_info_arr(struct xe_cper_info_entry *info_arr, u32 num_entries)
+{
+ u32 i;
+
+ for (i = 0; i < num_entries; i++)
+ kfree(info_arr[i].info);
+ kfree(info_arr);
+}
+
+static bool fill_info_entry(struct xe_cper_info_entry *entry,
+ const struct xe_ras_error_class *counter, u32 error_count,
+ const struct xe_ras_error_log *logs, u32 num_logs)
+{
+ entry->info = build_info(logs, num_logs, counter, error_count);
+ if (!entry->info)
+ return false;
+
+ entry->info_size = struct_size(entry->info, event_queue,
+ entry->info->event_queue_size);
+ /* The first log is the first occurrence of the error */
+ entry->timestamp = logs[0].timestamp;
+ entry->hdr.counter = *counter;
+ entry->hdr.error_count = error_count;
+ return true;
+}
+
+static u32 build_detail_info(const struct xe_ras_error_class *counter,
+ u32 error_count,
+ const struct xe_ras_error_log *logs, u32 num_logs,
+ struct xe_cper_info_entry *info_arr)
+{
+ /* All logs belong to the queried class; the error count may exceed the logs kept */
+ if (!num_logs)
+ return 0;
+
+ num_logs = min_t(u32, num_logs, XE_RAS_NUM_COUNTERS);
+
+ return fill_info_entry(&info_arr[0], counter, error_count, logs, num_logs) ? 1 : 0;
+}
+
+static u32 build_aggregate_info(struct xe_device *xe,
+ const struct xe_ras_info_queue_dynamic_counter_hdr *hdrs,
+ u32 num_hdrs, const struct xe_ras_error_log *logs,
+ u32 avail_logs, struct xe_cper_info_entry *info_arr)
+{
+ u32 log_offset = 0, num_entries = 0, i;
+
+ for (i = 0; i < num_hdrs; i++) {
+ u32 num_logs = min_t(u32, hdrs[i].error_count, XE_RAS_NUM_COUNTERS);
+
+ if (num_logs > avail_logs - log_offset) {
+ xe_warn(xe, "CPER: header[%u] claims %u logs but only %u remain\n",
+ i, num_logs, avail_logs - log_offset);
+ break;
+ }
+
+ if (!num_logs)
+ continue;
+
+ if (!fill_info_entry(&info_arr[num_entries], &hdrs[i].counter,
+ hdrs[i].error_count, &logs[log_offset], num_logs))
+ break;
+
+ log_offset += num_logs;
+ num_entries++;
+ }
+
+ return num_entries;
+}
+
+static u8 *cper_get_info_queue_buffer(struct xe_device *xe,
+ const struct xe_ras_get_counter_response *counter_resp,
+ u32 *raw_total)
+{
+ const struct xe_ras_info_queue_header *first_qhdr = &counter_resp->first.header;
+ u32 buf_size;
+ u8 *raw_buf;
+
+ if (!first_qhdr->total_size) {
+ xe_warn(xe, "CPER: info queue reports zero total size\n");
+ return NULL;
+ }
+
+ if (first_qhdr->total_size > XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE)
+ xe_warn(xe, "CPER: info queue size %u exceeds max %u, truncating\n",
+ first_qhdr->total_size, XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE);
+
+ buf_size = min(first_qhdr->total_size, XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE);
+ raw_buf = kzalloc_objs(*raw_buf, buf_size);
+ if (!raw_buf)
+ return NULL;
+
+ *raw_total = xe_ras_drain_info_queue(xe, counter_resp, raw_buf, buf_size);
+ if (!*raw_total) {
+ kfree(raw_buf);
+ return NULL;
+ }
+
+ return raw_buf;
+}
+
+static struct xe_cper_info_entry *
+cper_build_info_arr(struct xe_device *xe,
+ const struct xe_ras_get_counter_response *counter_resp,
+ const struct xe_ras_error_class *counter,
+ const u8 *raw_buf, u32 raw_total, u32 *num_entries)
+{
+ const struct xe_ras_error_log *logs;
+ struct xe_cper_info_entry *info_arr;
+ u32 num_headers, headers_size, avail_logs;
+
+ num_headers = counter_resp->first.header.num_headers;
+ headers_size = num_headers * sizeof(struct xe_ras_info_queue_dynamic_counter_hdr);
+ if (headers_size > raw_total) {
+ xe_warn(xe, "CPER: aggregate headers size (%u) exceeds raw total (%u)\n",
+ headers_size, raw_total);
+ return NULL;
+ }
+
+ logs = (const struct xe_ras_error_log *)(raw_buf + headers_size);
+ avail_logs = (raw_total - headers_size) / sizeof(*logs);
+
+ info_arr = kzalloc_objs(*info_arr, num_headers ?: 1);
+ if (!info_arr)
+ return NULL;
+
+ if (num_headers)
+ *num_entries = build_aggregate_info(xe, (const void *)raw_buf,
+ num_headers, logs, avail_logs,
+ info_arr);
+ else
+ *num_entries = build_detail_info(counter, counter_resp->value,
+ logs, avail_logs, info_arr);
+
+ if (!*num_entries) {
+ kfree(info_arr);
+ return NULL;
+ }
+
+ return info_arr;
+}
+
+/**
+ * cper_prepare_info() - Build the CPER error info records from RAS info queue data
+ * @xe: xe device instance
+ * @counter_resp: counter response containing the first embedded chunk
+ * @counter: RAS error class used for info record of details counter
+ * @num_entries: output number of entries in the returned array
+ *
+ * Assembles the complete raw info queue data from the first chunk already
+ * embedded in @counter_resp and any additional chunks fetched via
+ * GET_INFO_QUEUE. Two use cases are supported based on num_headers in
+ * the info queue header:
+ *
+ * Detail error counter (num_headers == 0)::
+ *
+ * [xe_ras_error_log * N]
+ *
+ * Returns one xe_cper_info_entry covering up to XE_RAS_NUM_COUNTERS logs.
+ *
+ * Aggregate error counter (num_headers > 0)::
+ *
+ * [xe_ras_info_queue_dynamic_counter_hdr * num_headers]
+ * [xe_ras_error_log * N]
+ *
+ * Returns one xe_cper_info_entry per header. Each header's @counter
+ * identifies its error class, and @error_count gives its error count. Up to
+ * XE_RAS_NUM_COUNTERS xe_ras_error_log entries are associated with each
+ * header. The header's counter populates the entry's info->counter.
+ *
+ * Returns: allocated xe_cper_info_entry array on success (caller must free it
+ * with free_info_arr()), NULL if no info queue is available or no
+ * error info could be built. @num_entries is set to the number of
+ * entries in the array, or zero when returning NULL.
+ */
+static struct xe_cper_info_entry *
+cper_prepare_info(struct xe_device *xe,
+ const struct xe_ras_get_counter_response *counter_resp,
+ const struct xe_ras_error_class *counter, u32 *num_entries)
+{
+ struct xe_cper_info_entry *info_arr = NULL;
+ u32 raw_total;
+ u8 *raw_buf = NULL;
+
+ *num_entries = 0;
+ if (!counter_resp->has_info_queue)
+ return NULL;
+
+ raw_buf = cper_get_info_queue_buffer(xe, counter_resp, &raw_total);
+ if (!raw_buf)
+ goto out;
+
+ info_arr = cper_build_info_arr(xe, counter_resp, counter, raw_buf,
+ raw_total, num_entries);
+out:
+ kfree(raw_buf);
+ if (!info_arr)
+ xe_warn(xe, "CPER: failed to build error info from info queue, emitting record without it\n");
+
+ return info_arr;
+}
+
/**
* xe_cper_emit_counter() - Emit CPER records for an already fetched error counter
* @xe: The &xe_device
@@ -208,19 +440,48 @@ static void cper_record_emit(struct xe_device *xe, u8 severity,
* @counter: RAS error class
* @response: Counter response returned by firmware for @counter
*
- * Build and emit a CPER record from @response.
+ * Build and emit CPER records from @response, including any info queue data.
+ * Must be called from a sleepable context with a runtime PM reference held.
*/
void xe_cper_emit_counter(struct xe_device *xe, int cper_sev, enum xe_sigid sigid,
const struct xe_ras_error_class *counter,
const struct xe_ras_get_counter_response *response)
{
- struct xe_cper_intel_hdr ihdr = {};
+ struct xe_cper_info_entry *info_arr = NULL, *entries;
+ struct xe_cper_info_entry single = {};
+ u32 num_entries = 0, count, i;
xe_assert(xe, is_hw_sigid(sigid));
- cper_init_intel_hdr(xe, counter, response->timestamp,
- sigid, response->value, &ihdr);
- cper_record_emit(xe, cper_sev, &INTEL_CPER_NOTIFY_GPU_ERROR, &ihdr, NULL, 0);
+ /* Draining the info queue sends sysctrl commands */
+ might_sleep();
+ xe_device_assert_mem_access(xe);
+
+ /* Without info queue data, emit a single record from the counter itself */
+ single.hdr.counter = *counter;
+ single.hdr.error_count = response->value;
+ single.timestamp = response->timestamp;
+ entries = &single;
+ count = 1;
+
+ info_arr = cper_prepare_info(xe, response, counter, &num_entries);
+ if (info_arr) {
+ entries = info_arr;
+ count = num_entries;
+ }
+
+ for (i = 0; i < count; i++) {
+ struct xe_cper_intel_hdr ihdr = {};
+
+ cper_init_intel_hdr(xe, &entries[i].hdr.counter, entries[i].timestamp,
+ sigid, entries[i].hdr.error_count,
+ entries[i].info_size, &ihdr);
+
+ cper_record_emit(xe, cper_sev, &INTEL_CPER_NOTIFY_GPU_ERROR, &ihdr,
+ entries[i].info, entries[i].info_size);
+ }
+
+ free_info_arr(info_arr, num_entries);
}
static void cper_emit_hw_err(struct xe_device *xe, int cper_sev, enum xe_sigid sigid,
diff --git a/drivers/gpu/drm/xe/xe_cper_types.h b/drivers/gpu/drm/xe/xe_cper_types.h
index 68e30df0440e..2502a73bd3f9 100644
--- a/drivers/gpu/drm/xe/xe_cper_types.h
+++ b/drivers/gpu/drm/xe/xe_cper_types.h
@@ -12,6 +12,11 @@
#include "xe_ras_types.h"
+/* Entries built from RAS error logs carry fixed-size details */
+#define XE_CPER_RAS_LOG_ENTRY_SIZE \
+ (offsetof(struct xe_cper_intel_event, metadata) + \
+ sizeof_field(struct xe_ras_error_log, details))
+
/*
* Validation bits definition for validation_bits in struct
* xe_cper_intel_hdr. When set, corresponding fields in header
@@ -67,14 +72,50 @@ struct xe_cper_intel_hdr {
/** @drv_version: Driver source version string (THIS_MODULE->srcversion) */
char drv_version[25];
/** @reserved: Reserved for future use, must be zero */
- u8 reserved[261];
+ u8 reserved[258];
+ /** @info_log_size: Size of xe_cper_intel_info */
+ u16 info_log_size;
+ /** @reserved1: Reserved for future use, must be zero */
+ u8 reserved1;
+} __packed;
+
+/**
+ * struct xe_cper_intel_info - Variable-length Intel-specific CPER error information
+ *
+ * Contains the counter and event queue, and is appended after
+ * &xe_cper_intel_hdr when detailed error information is available.
+ */
+struct xe_cper_intel_info {
+ /** @counter: Error class (severity, component, location, cause) */
+ struct xe_ras_error_class counter;
+ /** @error_count: Total number of errors recorded */
+ u32 error_count;
+ /** @event_queue_size: Total size of @event_queue in bytes */
+ u32 event_queue_size;
+ /** @event_queue_count: Number of events in @event_queue */
+ u32 event_queue_count;
+ /** @event_queue: Packed array of xe_cper_intel_event records */
+ u8 event_queue[];
+} __packed;
+
+/**
+ * struct xe_cper_intel_event - Single error event in the CPER event queue
+ */
+struct xe_cper_intel_event {
+ /** @size: Byte size of the @metadata payload */
+ u32 size;
+ /** @timestamp: &xe_ras_error_log::timestamp */
+ u64 timestamp;
+ /** @metadata: &xe_ras_error_log::details */
+ u8 metadata[];
} __packed;
/**
* struct xe_cper_nonstd_record - Intel GPU CPER record
*
* Contains the standard CPER record header, section descriptor, and the
- * Intel error section header.
+ * Intel section header. A &xe_cper_intel_info payload may be
+ * appended dynamically.
*/
struct xe_cper_nonstd_record {
/** @record_hdr: Standard CPER record header (UEFI Appendix N.2.1) */
@@ -99,6 +140,20 @@ struct xe_device_guid_entry {
guid_t guid;
};
+/**
+ * struct xe_cper_info_entry - One CPER info payload and its source counter
+ */
+struct xe_cper_info_entry {
+ /** @hdr: Error class and error count used for the CPER section header */
+ struct xe_ras_info_queue_dynamic_counter_hdr hdr;
+ /** @info: Allocated info payload, NULL if none */
+ struct xe_cper_intel_info *info;
+ /** @info_size: Byte size of @info including the event queue */
+ u32 info_size;
+ /** @timestamp: Timestamp of the first occurrence of this error class */
+ u64 timestamp;
+};
+
/**
* struct xe_cper - Xe CPER state
*/
diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
index 67d57182aac9..cec6f8427973 100644
--- a/drivers/gpu/drm/xe/xe_ras_types.h
+++ b/drivers/gpu/drm/xe/xe_ras_types.h
@@ -12,6 +12,7 @@
#define XE_RAS_NUM_COUNTERS 16
#define XE_RAS_NUM_ERROR_ARR 3
#define XE_RAS_NUM_PAGES 25
+#define XE_RAS_ERROR_DWORDS_MAX 16
/* Error bits in IEH global error status register */
#define XE_RAS_SOC_IEH_PUNIT BIT(1)
/* Device memory error categories */
@@ -171,6 +172,31 @@ struct xe_ras_info_queue_data_response {
u8 data[XE_RAS_INFO_QUEUE_MAX_CHUNK_SIZE];
} __packed;
+/**
+ * struct xe_ras_info_queue_dynamic_counter_hdr - Aggregate counter header entry
+ *
+ * When a session requests aggregate counter data, one header per matching
+ * dynamic counter class is prepended to the queue data. The @counter field
+ * identifies the error class, and @error_count is its error count; at most
+ * XE_RAS_NUM_COUNTERS error log entries follow for it.
+ */
+struct xe_ras_info_queue_dynamic_counter_hdr {
+ /** @counter: Error class associated with this counter group */
+ struct xe_ras_error_class counter;
+ /** @error_count: Error count of this class */
+ u32 error_count;
+} __packed;
+
+/**
+ * struct xe_ras_error_log - Single error log entry following dynamic counter headers
+ */
+struct xe_ras_error_log {
+ /** @timestamp: Timestamp when the error was recorded */
+ u64 timestamp;
+ /** @details: Error-specific details */
+ u32 details[XE_RAS_ERROR_DWORDS_MAX];
+} __packed;
+
/**
* struct xe_ras_get_info_queue_request - Request for XE_SYSCTRL_CMD_GET_INFO_QUEUE
*/
--
2.56.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* ✓ CI.KUnit: success for Extend CPER records with RAS info queue data
2026-11-06 18:59 [PATCH v6 0/2] Extend CPER records with RAS info queue data Badal Nilawar
2026-11-06 18:59 ` [PATCH v6 1/2] drm/xe/xe_ras: Add support to retrieve " Badal Nilawar
2026-11-06 18:59 ` [PATCH v6 2/2] drm/xe/cper: Prepare Intel CPER info records Badal Nilawar
@ 2026-11-06 19:08 ` Patchwork
2026-11-06 19:43 ` ✓ Xe.CI.BAT: " Patchwork
2026-11-07 23:49 ` ✓ Xe.CI.FULL: " Patchwork
4 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2026-11-06 19:08 UTC (permalink / raw)
To: Badal Nilawar; +Cc: intel-xe
== Series Details ==
Series: Extend CPER records with RAS info queue data
URL : https://patchwork.freedesktop.org/series/178015/
State : success
== Summary ==
+ trap cleanup EXIT
+ kunitconfigs=('/kernel/drivers/gpu/tests/.kunitconfig' '/kernel/drivers/gpu/drm/xe/.kunitconfig' '/kernel/drivers/gpu/drm/tests/.kunitconfig' '/kernel/drivers/gpu/drm/ttm/tests/.kunitconfig' '/kernel/drivers/dma-buf/.kunitconfig')
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/tests/.kunitconfig
[19:06:02] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[19:06:07] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[19:06:28] Starting KUnit Kernel (1/1)...
[19:06:28] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[19:06:28] ================= gpu_buddy (14 subtests) ==================
[19:06:28] [PASSED] gpu_test_buddy_alloc_limit
[19:06:28] [PASSED] gpu_test_buddy_alloc_optimistic
[19:06:28] [PASSED] gpu_test_buddy_alloc_pessimistic
[19:06:28] [PASSED] gpu_test_buddy_alloc_pathological
[19:06:28] [PASSED] gpu_test_buddy_alloc_contiguous
[19:06:28] [PASSED] gpu_test_buddy_alloc_clear
[19:06:28] [PASSED] gpu_test_buddy_alloc_range
[19:06:28] [PASSED] gpu_test_buddy_alloc_range_bias
[19:06:29] [PASSED] gpu_test_buddy_fragmentation_performance
[19:06:29] [PASSED] gpu_test_buddy_dirty_tracker_performance
[19:06:29] [PASSED] gpu_test_buddy_alloc_exceeds_max_order
[19:06:29] [PASSED] gpu_test_buddy_offset_aligned_allocation
[19:06:29] [PASSED] gpu_test_buddy_subtree_offset_alignment_stress
[19:06:29] [PASSED] gpu_test_buddy_addr_to_block
[19:06:29] ==================== [PASSED] gpu_buddy ====================
[19:06:29] ============================================================
[19:06:29] Testing complete. Ran 14 tests: passed: 14
[19:06:29] Elapsed time: 27.219s total, 5.143s configuring, 20.158s building, 1.852s running
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/xe/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[19:06:30] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[19:06:32] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[19:07:10] Starting KUnit Kernel (1/1)...
[19:07:10] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[19:07:11] ================== guc_buf (11 subtests) ===================
[19:07:11] [PASSED] test_smallest
[19:07:11] [PASSED] test_largest
[19:07:11] [PASSED] test_granular
[19:07:11] [PASSED] test_unique
[19:07:11] [PASSED] test_overlap
[19:07:11] [PASSED] test_reusable
[19:07:11] [PASSED] test_too_big
[19:07:11] [PASSED] test_flush
[19:07:11] [PASSED] test_lookup
[19:07:11] [PASSED] test_data
[19:07:11] [PASSED] test_class
[19:07:11] ===================== [PASSED] guc_buf =====================
[19:07:11] =================== guc_dbm (7 subtests) ===================
[19:07:11] [PASSED] test_empty
[19:07:11] [PASSED] test_default
[19:07:11] ======================== test_size ========================
[19:07:11] [PASSED] 4
[19:07:11] [PASSED] 8
[19:07:11] [PASSED] 32
[19:07:11] [PASSED] 256
[19:07:11] ==================== [PASSED] test_size ====================
[19:07:11] ======================= test_reuse ========================
[19:07:11] [PASSED] 4
[19:07:11] [PASSED] 8
[19:07:11] [PASSED] 32
[19:07:11] [PASSED] 256
[19:07:11] =================== [PASSED] test_reuse ====================
[19:07:11] =================== test_range_overlap ====================
[19:07:11] [PASSED] 4
[19:07:11] [PASSED] 8
[19:07:11] [PASSED] 32
[19:07:11] [PASSED] 256
[19:07:11] =============== [PASSED] test_range_overlap ================
[19:07:11] =================== test_range_compact ====================
[19:07:11] [PASSED] 4
[19:07:11] [PASSED] 8
[19:07:11] [PASSED] 32
[19:07:11] [PASSED] 256
[19:07:11] =============== [PASSED] test_range_compact ================
[19:07:11] ==================== test_range_spare =====================
[19:07:11] [PASSED] 4
[19:07:11] [PASSED] 8
[19:07:11] [PASSED] 32
[19:07:11] [PASSED] 256
[19:07:11] ================ [PASSED] test_range_spare =================
[19:07:11] ===================== [PASSED] guc_dbm =====================
[19:07:11] ================== guc_idm (22 subtests) ===================
[19:07:11] [PASSED] bad_init
[19:07:11] [PASSED] no_init
[19:07:11] [PASSED] init_fini
[19:07:11] [PASSED] check_init_small
[19:07:11] [PASSED] check_init_shared
[19:07:11] [PASSED] check_used
[19:07:11] [PASSED] check_quota
[19:07:11] [PASSED] check_all
[19:07:11] [PASSED] check_limits
[19:07:11] [PASSED] check_overlap
[19:07:11] [PASSED] check_overlap_alloc
[19:07:11] [PASSED] check_overlap_release
[19:07:11] [PASSED] check_overlap_partial_init
[19:07:11] [PASSED] check_overlap_partial_shared_range_blocking
[19:07:11] [PASSED] check_used_usable
[19:07:11] [PASSED] check_used_shareable
[19:07:11] [PASSED] check_used_mixed
[19:07:11] [PASSED] check_release_usable_range
[19:07:11] [PASSED] check_release_shareable_range
[19:07:11] [PASSED] check_split_boundaries
[19:07:11] [PASSED] check_shareable_spare
[19:07:11] [PASSED] check_shareable_spare_fragmented_tail
[19:07:11] ===================== [PASSED] guc_idm =====================
[19:07:11] ============== guc_klv_helpers (13 subtests) ===============
[19:07:11] [PASSED] test_count
[19:07:11] [PASSED] test_encode_u32
[19:07:11] [PASSED] test_encode_u64
[19:07:11] [PASSED] test_encode_string
[19:07:11] [PASSED] test_encode_object_raw
[19:07:11] [PASSED] test_encode_object_klv
[19:07:11] [PASSED] test_encode_object_nested
[19:07:11] [PASSED] test_encode_object_basic
[19:07:11] ===================== test_decode_u16 =====================
[19:07:11] [PASSED] empty
[19:07:11] [PASSED] valid
[19:07:11] [PASSED] max
[19:07:11] [PASSED] big
[19:07:11] [PASSED] long
[19:07:11] ================= [PASSED] test_decode_u16 =================
[19:07:11] ===================== test_decode_u32 =====================
[19:07:11] [PASSED] empty
[19:07:11] [PASSED] valid
[19:07:11] [PASSED] max
[19:07:11] [PASSED] long
[19:07:11] ================= [PASSED] test_decode_u32 =================
[19:07:11] ===================== test_decode_u64 =====================
[19:07:11] [PASSED] empty
[19:07:11] [PASSED] short
[19:07:11] [PASSED] valid
[19:07:11] [PASSED] max
[19:07:11] [PASSED] long
[19:07:11] ================= [PASSED] test_decode_u64 =================
[19:07:11] ===================== test_decode_str =====================
[19:07:11] [PASSED] empty
[19:07:11] [PASSED] one
[19:07:11] [PASSED] one_trash
[19:07:11] [PASSED] two
[19:07:11] [PASSED] two_trash
[19:07:11] [PASSED] three
[19:07:11] [PASSED] dword
[19:07:11] [PASSED] four
[19:07:11] [PASSED] five
[19:07:11] [PASSED] six
[19:07:11] [PASSED] seven
[19:07:11] [PASSED] qword
[19:07:11] ================= [PASSED] test_decode_str =================
[19:07:11] [PASSED] test_print
[19:07:11] ================= [PASSED] guc_klv_helpers =================
[19:07:11] =================== xe_log (4 subtests) ====================
[19:07:11] [PASSED] demo_cper
[19:07:11] [PASSED] demo_dmesg
[19:07:11] ======================= test_dmesg ========================
[19:07:11] [PASSED] test_fatal
[19:07:11] [PASSED] test_fatal_tile
[19:07:11] [PASSED] test_fatal_gt
[19:07:11] [PASSED] test_fatal_comp
[19:07:11] [PASSED] test_fatal_comp_tile
[19:07:11] [PASSED] test_fatal_comp_gt
[19:07:11] [PASSED] test_fatal_all
[19:07:11] [PASSED] test_recoverable
[19:07:11] [PASSED] test_recoverable_tile
[19:07:11] [PASSED] test_recoverable_gt
[19:07:11] [PASSED] test_recoverable_comp
[19:07:11] [PASSED] test_recoverable_comp_tile
[19:07:11] [PASSED] test_recoverable_comp_gt
[19:07:11] [PASSED] test_recoverable_all
[19:07:11] [PASSED] test_info
[19:07:11] [PASSED] test_info_tile
[19:07:11] [PASSED] test_info_gt
[19:07:11] [PASSED] test_info_err
[19:07:11] [PASSED] test_info_comp
[19:07:11] [PASSED] test_info_comp_tile
[19:07:11] [PASSED] test_info_comp_gt
[19:07:11] [PASSED] test_info_all
[19:07:11] [PASSED] test_hw_fatal
[19:07:11] [PASSED] test_hw_recoverable
[19:07:11] [PASSED] test_hw_corrected
[19:07:11] [PASSED] test_hw_informational
[19:07:11] =================== [PASSED] test_dmesg ====================
[19:07:11] ====================== test_invalid =======================
[19:07:11] [SKIPPED] no-component no-location no-warn (requires CONFIG_DRM_XE_DEBUG)
[19:07:11] [SKIPPED] reserved location (requires CONFIG_DRM_XE_DEBUG)
[19:07:11] [SKIPPED] unknown location (requires CONFIG_DRM_XE_DEBUG)
[19:07:11] [SKIPPED] nonzero-device-id location (requires CONFIG_DRM_XE_DEBUG)
[19:07:11] [SKIPPED] invalid-tile-id location (requires CONFIG_DRM_XE_DEBUG)
[19:07:11] [SKIPPED] invalid-gt-id location (requires CONFIG_DRM_XE_DEBUG)
[19:07:11] [SKIPPED] unknown component class (requires CONFIG_DRM_XE_DEBUG)
[19:07:11] [SKIPPED] unknown system component (requires CONFIG_DRM_XE_DEBUG)
[19:07:11] [SKIPPED] unknown hardware component (requires CONFIG_DRM_XE_DEBUG)
[19:07:11] [SKIPPED] unknown component and location (requires CONFIG_DRM_XE_DEBUG)
[19:07:11] ================== [SKIPPED] test_invalid ==================
[19:07:11] ===================== [PASSED] xe_log ======================
[19:07:11] ================== no_relay (3 subtests) ===================
[19:07:11] [PASSED] xe_drops_guc2pf_if_not_ready
[19:07:11] [PASSED] xe_drops_guc2vf_if_not_ready
[19:07:11] [PASSED] xe_rejects_send_if_not_ready
[19:07:11] ==================== [PASSED] no_relay =====================
[19:07:11] ================== pf_relay (14 subtests) ==================
[19:07:11] [PASSED] pf_rejects_guc2pf_too_short
[19:07:11] [PASSED] pf_rejects_guc2pf_too_long
[19:07:11] [PASSED] pf_rejects_guc2pf_no_payload
[19:07:11] [PASSED] pf_fails_no_payload
[19:07:11] [PASSED] pf_fails_bad_origin
[19:07:11] [PASSED] pf_fails_bad_type
[19:07:11] [PASSED] pf_txn_reports_error
[19:07:11] [PASSED] pf_txn_sends_pf2guc
[19:07:11] [PASSED] pf_sends_pf2guc
[19:07:11] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[19:07:11] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[19:07:11] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[19:07:11] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[19:07:11] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[19:07:11] ==================== [PASSED] pf_relay =====================
[19:07:11] ================== vf_relay (3 subtests) ===================
[19:07:11] [PASSED] vf_rejects_guc2vf_too_short
[19:07:11] [PASSED] vf_rejects_guc2vf_too_long
[19:07:11] [PASSED] vf_rejects_guc2vf_no_payload
[19:07:11] ==================== [PASSED] vf_relay =====================
[19:07:11] ================ pf_gt_config (9 subtests) =================
[19:07:11] [PASSED] fair_contexts_1vf
[19:07:11] [PASSED] fair_doorbells_1vf
[19:07:11] [PASSED] fair_ggtt_1vf
[19:07:11] ====================== fair_vram_1vf ======================
[19:07:11] [PASSED] 3.50 GiB
[19:07:11] [PASSED] 11.5 GiB
[19:07:11] [PASSED] 15.5 GiB
[19:07:11] [PASSED] 31.5 GiB
[19:07:11] [PASSED] 63.5 GiB
[19:07:11] [PASSED] 1.91 GiB
[19:07:11] ================== [PASSED] fair_vram_1vf ==================
[19:07:11] ================ fair_vram_1vf_admin_only =================
[19:07:11] [PASSED] 3.50 GiB
[19:07:11] [PASSED] 11.5 GiB
[19:07:11] [PASSED] 15.5 GiB
[19:07:11] [PASSED] 31.5 GiB
[19:07:11] [PASSED] 63.5 GiB
[19:07:11] [PASSED] 1.91 GiB
[19:07:11] ============ [PASSED] fair_vram_1vf_admin_only =============
[19:07:11] ====================== fair_contexts ======================
[19:07:11] [PASSED] 1 VF
[19:07:11] [PASSED] 2 VFs
[19:07:11] [PASSED] 3 VFs
[19:07:11] [PASSED] 4 VFs
[19:07:11] [PASSED] 5 VFs
[19:07:11] [PASSED] 6 VFs
[19:07:11] [PASSED] 7 VFs
[19:07:11] [PASSED] 8 VFs
[19:07:11] [PASSED] 9 VFs
[19:07:11] [PASSED] 10 VFs
[19:07:11] [PASSED] 11 VFs
[19:07:11] [PASSED] 12 VFs
[19:07:11] [PASSED] 13 VFs
[19:07:11] [PASSED] 14 VFs
[19:07:11] [PASSED] 15 VFs
[19:07:11] [PASSED] 16 VFs
[19:07:11] [PASSED] 17 VFs
[19:07:11] [PASSED] 18 VFs
[19:07:11] [PASSED] 19 VFs
[19:07:11] [PASSED] 20 VFs
[19:07:11] [PASSED] 21 VFs
[19:07:11] [PASSED] 22 VFs
[19:07:11] [PASSED] 23 VFs
[19:07:11] [PASSED] 24 VFs
[19:07:11] [PASSED] 25 VFs
[19:07:11] [PASSED] 26 VFs
[19:07:11] [PASSED] 27 VFs
[19:07:11] [PASSED] 28 VFs
[19:07:11] [PASSED] 29 VFs
[19:07:11] [PASSED] 30 VFs
[19:07:11] [PASSED] 31 VFs
[19:07:11] [PASSED] 32 VFs
[19:07:11] [PASSED] 33 VFs
[19:07:11] [PASSED] 34 VFs
[19:07:11] [PASSED] 35 VFs
[19:07:11] [PASSED] 36 VFs
[19:07:11] [PASSED] 37 VFs
[19:07:11] [PASSED] 38 VFs
[19:07:11] [PASSED] 39 VFs
[19:07:11] [PASSED] 40 VFs
[19:07:11] [PASSED] 41 VFs
[19:07:11] [PASSED] 42 VFs
[19:07:11] [PASSED] 43 VFs
[19:07:11] [PASSED] 44 VFs
[19:07:11] [PASSED] 45 VFs
[19:07:11] [PASSED] 46 VFs
[19:07:11] [PASSED] 47 VFs
[19:07:11] [PASSED] 48 VFs
[19:07:11] [PASSED] 49 VFs
[19:07:11] [PASSED] 50 VFs
[19:07:11] [PASSED] 51 VFs
[19:07:11] [PASSED] 52 VFs
[19:07:11] [PASSED] 53 VFs
[19:07:11] [PASSED] 54 VFs
[19:07:11] [PASSED] 55 VFs
[19:07:11] [PASSED] 56 VFs
[19:07:11] [PASSED] 57 VFs
[19:07:11] [PASSED] 58 VFs
[19:07:11] [PASSED] 59 VFs
[19:07:11] [PASSED] 60 VFs
[19:07:11] [PASSED] 61 VFs
[19:07:11] [PASSED] 62 VFs
[19:07:11] [PASSED] 63 VFs
[19:07:11] ================== [PASSED] fair_contexts ==================
[19:07:11] ===================== fair_doorbells ======================
[19:07:11] [PASSED] 1 VF
[19:07:11] [PASSED] 2 VFs
[19:07:11] [PASSED] 3 VFs
[19:07:11] [PASSED] 4 VFs
[19:07:11] [PASSED] 5 VFs
[19:07:11] [PASSED] 6 VFs
[19:07:11] [PASSED] 7 VFs
[19:07:11] [PASSED] 8 VFs
[19:07:11] [PASSED] 9 VFs
[19:07:11] [PASSED] 10 VFs
[19:07:11] [PASSED] 11 VFs
[19:07:11] [PASSED] 12 VFs
[19:07:11] [PASSED] 13 VFs
[19:07:11] [PASSED] 14 VFs
[19:07:11] [PASSED] 15 VFs
[19:07:11] [PASSED] 16 VFs
[19:07:11] [PASSED] 17 VFs
[19:07:11] [PASSED] 18 VFs
[19:07:11] [PASSED] 19 VFs
[19:07:11] [PASSED] 20 VFs
[19:07:11] [PASSED] 21 VFs
[19:07:11] [PASSED] 22 VFs
[19:07:11] [PASSED] 23 VFs
[19:07:11] [PASSED] 24 VFs
[19:07:11] [PASSED] 25 VFs
[19:07:11] [PASSED] 26 VFs
[19:07:11] [PASSED] 27 VFs
[19:07:11] [PASSED] 28 VFs
[19:07:11] [PASSED] 29 VFs
[19:07:11] [PASSED] 30 VFs
[19:07:11] [PASSED] 31 VFs
[19:07:11] [PASSED] 32 VFs
[19:07:11] [PASSED] 33 VFs
[19:07:11] [PASSED] 34 VFs
[19:07:11] [PASSED] 35 VFs
[19:07:11] [PASSED] 36 VFs
[19:07:11] [PASSED] 37 VFs
[19:07:11] [PASSED] 38 VFs
[19:07:11] [PASSED] 39 VFs
[19:07:11] [PASSED] 40 VFs
[19:07:11] [PASSED] 41 VFs
[19:07:11] [PASSED] 42 VFs
[19:07:11] [PASSED] 43 VFs
[19:07:11] [PASSED] 44 VFs
[19:07:11] [PASSED] 45 VFs
[19:07:11] [PASSED] 46 VFs
[19:07:11] [PASSED] 47 VFs
[19:07:11] [PASSED] 48 VFs
[19:07:11] [PASSED] 49 VFs
[19:07:11] [PASSED] 50 VFs
[19:07:11] [PASSED] 51 VFs
[19:07:11] [PASSED] 52 VFs
[19:07:11] [PASSED] 53 VFs
[19:07:11] [PASSED] 54 VFs
[19:07:11] [PASSED] 55 VFs
[19:07:11] [PASSED] 56 VFs
[19:07:11] [PASSED] 57 VFs
[19:07:11] [PASSED] 58 VFs
[19:07:11] [PASSED] 59 VFs
[19:07:11] [PASSED] 60 VFs
[19:07:11] [PASSED] 61 VFs
[19:07:11] [PASSED] 62 VFs
[19:07:11] [PASSED] 63 VFs
[19:07:11] ================= [PASSED] fair_doorbells ==================
[19:07:11] ======================== fair_ggtt ========================
[19:07:11] [PASSED] 1 VF
[19:07:11] [PASSED] 2 VFs
[19:07:11] [PASSED] 3 VFs
[19:07:11] [PASSED] 4 VFs
[19:07:11] [PASSED] 5 VFs
[19:07:11] [PASSED] 6 VFs
[19:07:11] [PASSED] 7 VFs
[19:07:11] [PASSED] 8 VFs
[19:07:11] [PASSED] 9 VFs
[19:07:11] [PASSED] 10 VFs
[19:07:11] [PASSED] 11 VFs
[19:07:11] [PASSED] 12 VFs
[19:07:11] [PASSED] 13 VFs
[19:07:11] [PASSED] 14 VFs
[19:07:11] [PASSED] 15 VFs
[19:07:11] [PASSED] 16 VFs
[19:07:11] [PASSED] 17 VFs
[19:07:11] [PASSED] 18 VFs
[19:07:11] [PASSED] 19 VFs
[19:07:11] [PASSED] 20 VFs
[19:07:11] [PASSED] 21 VFs
[19:07:11] [PASSED] 22 VFs
[19:07:11] [PASSED] 23 VFs
[19:07:11] [PASSED] 24 VFs
[19:07:11] [PASSED] 25 VFs
[19:07:11] [PASSED] 26 VFs
[19:07:11] [PASSED] 27 VFs
[19:07:11] [PASSED] 28 VFs
[19:07:11] [PASSED] 29 VFs
[19:07:11] [PASSED] 30 VFs
[19:07:11] [PASSED] 31 VFs
[19:07:11] [PASSED] 32 VFs
[19:07:11] [PASSED] 33 VFs
[19:07:11] [PASSED] 34 VFs
[19:07:11] [PASSED] 35 VFs
[19:07:11] [PASSED] 36 VFs
[19:07:11] [PASSED] 37 VFs
[19:07:11] [PASSED] 38 VFs
[19:07:11] [PASSED] 39 VFs
[19:07:11] [PASSED] 40 VFs
[19:07:11] [PASSED] 41 VFs
[19:07:11] [PASSED] 42 VFs
[19:07:11] [PASSED] 43 VFs
[19:07:11] [PASSED] 44 VFs
[19:07:11] [PASSED] 45 VFs
[19:07:11] [PASSED] 46 VFs
[19:07:11] [PASSED] 47 VFs
[19:07:11] [PASSED] 48 VFs
[19:07:11] [PASSED] 49 VFs
[19:07:11] [PASSED] 50 VFs
[19:07:11] [PASSED] 51 VFs
[19:07:11] [PASSED] 52 VFs
[19:07:11] [PASSED] 53 VFs
[19:07:11] [PASSED] 54 VFs
[19:07:11] [PASSED] 55 VFs
[19:07:11] [PASSED] 56 VFs
[19:07:11] [PASSED] 57 VFs
[19:07:11] [PASSED] 58 VFs
[19:07:11] [PASSED] 59 VFs
[19:07:11] [PASSED] 60 VFs
[19:07:11] [PASSED] 61 VFs
[19:07:11] [PASSED] 62 VFs
[19:07:11] [PASSED] 63 VFs
[19:07:11] ==================== [PASSED] fair_ggtt ====================
[19:07:11] ======================== fair_vram ========================
[19:07:11] [PASSED] 1 VF
[19:07:11] [PASSED] 2 VFs
[19:07:11] [PASSED] 3 VFs
[19:07:11] [PASSED] 4 VFs
[19:07:11] [PASSED] 5 VFs
[19:07:11] [PASSED] 6 VFs
[19:07:11] [PASSED] 7 VFs
[19:07:11] [PASSED] 8 VFs
[19:07:11] [PASSED] 9 VFs
[19:07:11] [PASSED] 10 VFs
[19:07:11] [PASSED] 11 VFs
[19:07:11] [PASSED] 12 VFs
[19:07:11] [PASSED] 13 VFs
[19:07:11] [PASSED] 14 VFs
[19:07:11] [PASSED] 15 VFs
[19:07:11] [PASSED] 16 VFs
[19:07:11] [PASSED] 17 VFs
[19:07:11] [PASSED] 18 VFs
[19:07:11] [PASSED] 19 VFs
[19:07:11] [PASSED] 20 VFs
[19:07:11] [PASSED] 21 VFs
[19:07:11] [PASSED] 22 VFs
[19:07:11] [PASSED] 23 VFs
[19:07:11] [PASSED] 24 VFs
[19:07:11] [PASSED] 25 VFs
[19:07:11] [PASSED] 26 VFs
[19:07:11] [PASSED] 27 VFs
[19:07:11] [PASSED] 28 VFs
[19:07:11] [PASSED] 29 VFs
[19:07:11] [PASSED] 30 VFs
[19:07:11] [PASSED] 31 VFs
[19:07:11] [PASSED] 32 VFs
[19:07:11] [PASSED] 33 VFs
[19:07:11] [PASSED] 34 VFs
[19:07:11] [PASSED] 35 VFs
[19:07:11] [PASSED] 36 VFs
[19:07:11] [PASSED] 37 VFs
[19:07:11] [PASSED] 38 VFs
[19:07:11] [PASSED] 39 VFs
[19:07:11] [PASSED] 40 VFs
[19:07:11] [PASSED] 41 VFs
[19:07:11] [PASSED] 42 VFs
[19:07:11] [PASSED] 43 VFs
[19:07:11] [PASSED] 44 VFs
[19:07:11] [PASSED] 45 VFs
[19:07:11] [PASSED] 46 VFs
[19:07:11] [PASSED] 47 VFs
[19:07:11] [PASSED] 48 VFs
[19:07:11] [PASSED] 49 VFs
[19:07:11] [PASSED] 50 VFs
[19:07:11] [PASSED] 51 VFs
[19:07:11] [PASSED] 52 VFs
[19:07:11] [PASSED] 53 VFs
[19:07:11] [PASSED] 54 VFs
[19:07:11] [PASSED] 55 VFs
[19:07:11] [PASSED] 56 VFs
[19:07:11] [PASSED] 57 VFs
[19:07:11] [PASSED] 58 VFs
[19:07:11] [PASSED] 59 VFs
[19:07:11] [PASSED] 60 VFs
[19:07:11] [PASSED] 61 VFs
[19:07:11] [PASSED] 62 VFs
[19:07:11] [PASSED] 63 VFs
[19:07:11] ==================== [PASSED] fair_vram ====================
[19:07:11] ================== [PASSED] pf_gt_config ===================
[19:07:11] ===================== lmtt (1 subtest) =====================
[19:07:11] ======================== test_ops =========================
[19:07:11] [PASSED] 2-level
[19:07:11] [PASSED] multi-level
[19:07:11] ==================== [PASSED] test_ops =====================
[19:07:11] ====================== [PASSED] lmtt =======================
[19:07:11] ================= sriov_packet (1 subtest) =================
[19:07:11] [PASSED] test_descriptor_init
[19:07:11] ================== [PASSED] sriov_packet ===================
[19:07:11] ================= pf_service (11 subtests) =================
[19:07:11] [PASSED] pf_negotiate_any
[19:07:11] [PASSED] pf_negotiate_base_match
[19:07:11] [PASSED] pf_negotiate_base_newer
[19:07:11] [PASSED] pf_negotiate_base_next
[19:07:11] [SKIPPED] pf_negotiate_base_older (no older minor)
[19:07:11] [PASSED] pf_negotiate_base_prev
[19:07:11] [PASSED] pf_negotiate_latest_match
[19:07:11] [PASSED] pf_negotiate_latest_newer
[19:07:11] [PASSED] pf_negotiate_latest_next
[19:07:11] [SKIPPED] pf_negotiate_latest_older (no older minor)
[19:07:11] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[19:07:11] =================== [PASSED] pf_service ====================
[19:07:11] ================= xe_guc_g2g (2 subtests) ==================
[19:07:11] ============== xe_live_guc_g2g_kunit_default ==============
[19:07:11] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[19:07:11] ============== xe_live_guc_g2g_kunit_allmem ===============
[19:07:11] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[19:07:11] =================== [SKIPPED] xe_guc_g2g ===================
[19:07:11] =================== xe_mocs (2 subtests) ===================
[19:07:11] ================ xe_live_mocs_kernel_kunit ================
[19:07:11] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[19:07:11] ================ xe_live_mocs_reset_kunit =================
[19:07:11] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[19:07:11] ==================== [SKIPPED] xe_mocs =====================
[19:07:11] ================= xe_migrate (3 subtests) ==================
[19:07:11] ================= xe_migrate_sanity_kunit =================
[19:07:11] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[19:07:11] ================== xe_validate_ccs_kunit ==================
[19:07:11] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[19:07:11] ============= xe_migrate_access_memory_kunit ==============
[19:07:11] ========= [SKIPPED] xe_migrate_access_memory_kunit =========
[19:07:11] =================== [SKIPPED] xe_migrate ===================
[19:07:11] ================== xe_dma_buf (1 subtest) ==================
[19:07:11] ==================== xe_dma_buf_kunit =====================
[19:07:11] ================ [SKIPPED] xe_dma_buf_kunit ================
[19:07:11] =================== [SKIPPED] xe_dma_buf ===================
[19:07:11] ================= xe_bo_shrink (1 subtest) =================
[19:07:11] =================== xe_bo_shrink_kunit ====================
[19:07:11] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[19:07:11] ================== [SKIPPED] xe_bo_shrink ==================
[19:07:11] ==================== xe_bo (2 subtests) ====================
[19:07:11] ================== xe_ccs_migrate_kunit ===================
[19:07:11] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[19:07:11] ==================== xe_bo_evict_kunit ====================
[19:07:11] =============== [SKIPPED] xe_bo_evict_kunit ================
[19:07:11] ===================== [SKIPPED] xe_bo ======================
[19:07:11] =================== xe_any (9 subtests) ====================
[19:07:11] [PASSED] test_to_xe
[19:07:11] [PASSED] test_to_dev
[19:07:11] [PASSED] test_to_pdev
[19:07:11] [PASSED] test_to_drm
[19:07:11] [PASSED] test_if_pdev
[19:07:11] [PASSED] test_if_xe
[19:07:11] [PASSED] test_if_tile
[19:07:11] [PASSED] test_if_gt
[19:07:11] [PASSED] test_to_id
[19:07:11] ===================== [PASSED] xe_any ======================
[19:07:11] ==================== args (13 subtests) ====================
[19:07:11] [PASSED] count_args_test
[19:07:11] [PASSED] call_args_example
[19:07:11] [PASSED] call_args_test
[19:07:11] [PASSED] drop_first_arg_example
[19:07:11] [PASSED] drop_first_arg_test
[19:07:11] [PASSED] first_arg_example
[19:07:11] [PASSED] first_arg_test
[19:07:11] [PASSED] last_arg_example
[19:07:11] [PASSED] last_arg_test
[19:07:11] [PASSED] pick_arg_example
[19:07:11] [PASSED] if_args_example
[19:07:11] [PASSED] if_args_test
[19:07:11] [PASSED] sep_comma_example
[19:07:11] ====================== [PASSED] args =======================
[19:07:11] =================== xe_pci (3 subtests) ====================
[19:07:11] ==================== check_graphics_ip ====================
[19:07:11] [PASSED] 12.00 Xe_LP
[19:07:11] [PASSED] 12.10 Xe_LP+
[19:07:11] [PASSED] 12.55 Xe_HPG
[19:07:11] [PASSED] 12.60 Xe_HPC
[19:07:11] [PASSED] 12.70 Xe_LPG
[19:07:11] [PASSED] 12.71 Xe_LPG
[19:07:11] [PASSED] 12.74 Xe_LPG+
[19:07:11] [PASSED] 20.01 Xe2_HPG
[19:07:11] [PASSED] 20.02 Xe2_HPG
[19:07:11] [PASSED] 20.04 Xe2_LPG
[19:07:11] [PASSED] 30.00 Xe3_LPG
[19:07:11] [PASSED] 30.01 Xe3_LPG
[19:07:11] [PASSED] 30.03 Xe3_LPG
[19:07:11] [PASSED] 30.04 Xe3_LPG
[19:07:11] [PASSED] 30.05 Xe3_LPG
[19:07:11] [PASSED] 35.10 Xe3p_LPG
[19:07:11] [PASSED] 35.11 Xe3p_XPC
[19:07:11] ================ [PASSED] check_graphics_ip ================
[19:07:11] ===================== check_media_ip ======================
[19:07:11] [PASSED] 12.00 Xe_M
[19:07:11] [PASSED] 12.55 Xe_HPM
[19:07:11] [PASSED] 13.00 Xe_LPM+
[19:07:11] [PASSED] 13.01 Xe2_HPM
[19:07:11] [PASSED] 20.00 Xe2_LPM
[19:07:11] [PASSED] 30.00 Xe3_LPM
[19:07:11] [PASSED] 30.02 Xe3_LPM
[19:07:11] [PASSED] 35.00 Xe3p_LPM
[19:07:11] [PASSED] 35.03 Xe3p_HPM
[19:07:11] ================= [PASSED] check_media_ip ==================
[19:07:11] =================== check_platform_desc ===================
[19:07:11] [PASSED] 0x9A60 (TIGERLAKE)
[19:07:11] [PASSED] 0x9A68 (TIGERLAKE)
[19:07:11] [PASSED] 0x9A70 (TIGERLAKE)
[19:07:11] [PASSED] 0x9A40 (TIGERLAKE)
[19:07:11] [PASSED] 0x9A49 (TIGERLAKE)
[19:07:11] [PASSED] 0x9A59 (TIGERLAKE)
[19:07:11] [PASSED] 0x9A78 (TIGERLAKE)
[19:07:11] [PASSED] 0x9AC0 (TIGERLAKE)
[19:07:11] [PASSED] 0x9AC9 (TIGERLAKE)
[19:07:11] [PASSED] 0x9AD9 (TIGERLAKE)
[19:07:11] [PASSED] 0x9AF8 (TIGERLAKE)
[19:07:11] [PASSED] 0x4C80 (ROCKETLAKE)
[19:07:11] [PASSED] 0x4C8A (ROCKETLAKE)
[19:07:11] [PASSED] 0x4C8B (ROCKETLAKE)
[19:07:11] [PASSED] 0x4C8C (ROCKETLAKE)
[19:07:11] [PASSED] 0x4C90 (ROCKETLAKE)
[19:07:11] [PASSED] 0x4C9A (ROCKETLAKE)
[19:07:11] [PASSED] 0x4680 (ALDERLAKE_S)
[19:07:11] [PASSED] 0x4682 (ALDERLAKE_S)
[19:07:11] [PASSED] 0x4688 (ALDERLAKE_S)
[19:07:11] [PASSED] 0x468A (ALDERLAKE_S)
[19:07:11] [PASSED] 0x468B (ALDERLAKE_S)
[19:07:11] [PASSED] 0x4690 (ALDERLAKE_S)
[19:07:11] [PASSED] 0x4692 (ALDERLAKE_S)
[19:07:11] [PASSED] 0x4693 (ALDERLAKE_S)
[19:07:11] [PASSED] 0x46A0 (ALDERLAKE_P)
[19:07:11] [PASSED] 0x46A1 (ALDERLAKE_P)
[19:07:11] [PASSED] 0x46A2 (ALDERLAKE_P)
[19:07:11] [PASSED] 0x46A3 (ALDERLAKE_P)
[19:07:11] [PASSED] 0x46A6 (ALDERLAKE_P)
[19:07:11] [PASSED] 0x46A8 (ALDERLAKE_P)
[19:07:11] [PASSED] 0x46AA (ALDERLAKE_P)
[19:07:11] [PASSED] 0x462A (ALDERLAKE_P)
[19:07:11] [PASSED] 0x4626 (ALDERLAKE_P)
[19:07:11] [PASSED] 0x4628 (ALDERLAKE_P)
[19:07:11] [PASSED] 0x46B0 (ALDERLAKE_P)
[19:07:11] [PASSED] 0x46B1 (ALDERLAKE_P)
[19:07:11] [PASSED] 0x46B2 (ALDERLAKE_P)
[19:07:11] [PASSED] 0x46B3 (ALDERLAKE_P)
[19:07:11] [PASSED] 0x46C0 (ALDERLAKE_P)
[19:07:11] [PASSED] 0x46C1 (ALDERLAKE_P)
[19:07:11] [PASSED] 0x46C2 (ALDERLAKE_P)
[19:07:11] [PASSED] 0x46C3 (ALDERLAKE_P)
[19:07:11] [PASSED] 0x46D0 (ALDERLAKE_N)
[19:07:11] [PASSED] 0x46D1 (ALDERLAKE_N)
[19:07:11] [PASSED] 0x46D2 (ALDERLAKE_N)
[19:07:11] [PASSED] 0x46D3 (ALDERLAKE_N)
[19:07:11] [PASSED] 0x46D4 (ALDERLAKE_N)
[19:07:11] [PASSED] 0xA721 (ALDERLAKE_P)
[19:07:11] [PASSED] 0xA7A1 (ALDERLAKE_P)
[19:07:11] [PASSED] 0xA7A9 (ALDERLAKE_P)
[19:07:11] [PASSED] 0xA7AC (ALDERLAKE_P)
[19:07:11] [PASSED] 0xA7AD (ALDERLAKE_P)
[19:07:11] [PASSED] 0xA720 (ALDERLAKE_P)
[19:07:11] [PASSED] 0xA7A0 (ALDERLAKE_P)
[19:07:11] [PASSED] 0xA7A8 (ALDERLAKE_P)
[19:07:11] [PASSED] 0xA7AA (ALDERLAKE_P)
[19:07:11] [PASSED] 0xA7AB (ALDERLAKE_P)
[19:07:11] [PASSED] 0xA780 (ALDERLAKE_S)
[19:07:11] [PASSED] 0xA781 (ALDERLAKE_S)
[19:07:11] [PASSED] 0xA782 (ALDERLAKE_S)
[19:07:11] [PASSED] 0xA783 (ALDERLAKE_S)
[19:07:11] [PASSED] 0xA788 (ALDERLAKE_S)
[19:07:11] [PASSED] 0xA789 (ALDERLAKE_S)
[19:07:11] [PASSED] 0xA78A (ALDERLAKE_S)
[19:07:11] [PASSED] 0xA78B (ALDERLAKE_S)
[19:07:11] [PASSED] 0x4905 (DG1)
[19:07:11] [PASSED] 0x4906 (DG1)
[19:07:11] [PASSED] 0x4907 (DG1)
[19:07:11] [PASSED] 0x4908 (DG1)
[19:07:11] [PASSED] 0x4909 (DG1)
[19:07:11] [PASSED] 0x56C0 (DG2)
[19:07:11] [PASSED] 0x56C2 (DG2)
[19:07:11] [PASSED] 0x56C1 (DG2)
[19:07:11] [PASSED] 0x7D51 (METEORLAKE)
[19:07:11] [PASSED] 0x7DD1 (METEORLAKE)
[19:07:11] [PASSED] 0x7D41 (METEORLAKE)
[19:07:11] [PASSED] 0x7D67 (METEORLAKE)
[19:07:11] [PASSED] 0xB640 (METEORLAKE)
[19:07:11] [PASSED] 0x56A0 (DG2)
[19:07:11] [PASSED] 0x56A1 (DG2)
[19:07:11] [PASSED] 0x56A2 (DG2)
[19:07:11] [PASSED] 0x56BE (DG2)
[19:07:11] [PASSED] 0x56BF (DG2)
[19:07:11] [PASSED] 0x5690 (DG2)
[19:07:11] [PASSED] 0x5691 (DG2)
[19:07:11] [PASSED] 0x5692 (DG2)
[19:07:11] [PASSED] 0x56A5 (DG2)
[19:07:11] [PASSED] 0x56A6 (DG2)
[19:07:11] [PASSED] 0x56B0 (DG2)
[19:07:11] [PASSED] 0x56B1 (DG2)
[19:07:11] [PASSED] 0x56BA (DG2)
[19:07:11] [PASSED] 0x56BB (DG2)
[19:07:11] [PASSED] 0x56BC (DG2)
[19:07:11] [PASSED] 0x56BD (DG2)
[19:07:11] [PASSED] 0x5693 (DG2)
[19:07:11] [PASSED] 0x5694 (DG2)
[19:07:11] [PASSED] 0x5695 (DG2)
[19:07:11] [PASSED] 0x56A3 (DG2)
[19:07:11] [PASSED] 0x56A4 (DG2)
[19:07:11] [PASSED] 0x56B2 (DG2)
[19:07:11] [PASSED] 0x56B3 (DG2)
[19:07:11] [PASSED] 0x5696 (DG2)
[19:07:11] [PASSED] 0x5697 (DG2)
[19:07:11] [PASSED] 0xB69 (PVC)
[19:07:11] [PASSED] 0xB6E (PVC)
[19:07:11] [PASSED] 0xBD4 (PVC)
[19:07:11] [PASSED] 0xBD5 (PVC)
[19:07:11] [PASSED] 0xBD6 (PVC)
[19:07:11] [PASSED] 0xBD7 (PVC)
[19:07:11] [PASSED] 0xBD8 (PVC)
[19:07:11] [PASSED] 0xBD9 (PVC)
[19:07:11] [PASSED] 0xBDA (PVC)
[19:07:11] [PASSED] 0xBDB (PVC)
[19:07:11] [PASSED] 0xBE0 (PVC)
[19:07:11] [PASSED] 0xBE1 (PVC)
[19:07:11] [PASSED] 0xBE5 (PVC)
[19:07:11] [PASSED] 0x7D40 (METEORLAKE)
[19:07:11] [PASSED] 0x7D45 (METEORLAKE)
[19:07:11] [PASSED] 0x7D55 (METEORLAKE)
[19:07:11] [PASSED] 0x7D60 (METEORLAKE)
[19:07:11] [PASSED] 0x7DD5 (METEORLAKE)
[19:07:11] [PASSED] 0x6420 (LUNARLAKE)
[19:07:11] [PASSED] 0x64A0 (LUNARLAKE)
[19:07:11] [PASSED] 0x64B0 (LUNARLAKE)
[19:07:11] [PASSED] 0xE202 (BATTLEMAGE)
[19:07:11] [PASSED] 0xE209 (BATTLEMAGE)
[19:07:11] [PASSED] 0xE20B (BATTLEMAGE)
[19:07:11] [PASSED] 0xE20C (BATTLEMAGE)
[19:07:11] [PASSED] 0xE20D (BATTLEMAGE)
[19:07:11] [PASSED] 0xE210 (BATTLEMAGE)
[19:07:11] [PASSED] 0xE211 (BATTLEMAGE)
[19:07:11] [PASSED] 0xE212 (BATTLEMAGE)
[19:07:11] [PASSED] 0xE216 (BATTLEMAGE)
[19:07:11] [PASSED] 0xE220 (BATTLEMAGE)
[19:07:11] [PASSED] 0xE221 (BATTLEMAGE)
[19:07:11] [PASSED] 0xE222 (BATTLEMAGE)
[19:07:11] [PASSED] 0xE223 (BATTLEMAGE)
[19:07:11] [PASSED] 0xB080 (PANTHERLAKE)
[19:07:11] [PASSED] 0xB081 (PANTHERLAKE)
[19:07:11] [PASSED] 0xB082 (PANTHERLAKE)
[19:07:11] [PASSED] 0xB083 (PANTHERLAKE)
[19:07:11] [PASSED] 0xB084 (PANTHERLAKE)
[19:07:11] [PASSED] 0xB085 (PANTHERLAKE)
[19:07:11] [PASSED] 0xB086 (PANTHERLAKE)
[19:07:11] [PASSED] 0xB087 (PANTHERLAKE)
[19:07:11] [PASSED] 0xB08F (PANTHERLAKE)
[19:07:11] [PASSED] 0xB090 (PANTHERLAKE)
[19:07:11] [PASSED] 0xB0A0 (PANTHERLAKE)
[19:07:11] [PASSED] 0xB0A1 (PANTHERLAKE)
[19:07:11] [PASSED] 0xB0B0 (PANTHERLAKE)
[19:07:11] [PASSED] 0xFD80 (PANTHERLAKE)
[19:07:11] [PASSED] 0xFD81 (PANTHERLAKE)
[19:07:11] [PASSED] 0xD740 (NOVALAKE_S)
[19:07:11] [PASSED] 0xD741 (NOVALAKE_S)
[19:07:11] [PASSED] 0xD742 (NOVALAKE_S)
[19:07:11] [PASSED] 0xD743 (NOVALAKE_S)
[19:07:11] [PASSED] 0xD745 (NOVALAKE_S)
[19:07:11] [PASSED] 0xD74A (NOVALAKE_S)
[19:07:11] [PASSED] 0xD74B (NOVALAKE_S)
[19:07:11] [PASSED] 0x674C (CRESCENTISLAND)
[19:07:11] [PASSED] 0x674D (CRESCENTISLAND)
[19:07:11] [PASSED] 0x674E (CRESCENTISLAND)
[19:07:11] [PASSED] 0x674F (CRESCENTISLAND)
[19:07:11] [PASSED] 0x6750 (CRESCENTISLAND)
[19:07:11] [PASSED] 0x6751 (CRESCENTISLAND)
[19:07:11] [PASSED] 0x6752 (CRESCENTISLAND)
[19:07:11] [PASSED] 0xD750 (NOVALAKE_P)
[19:07:11] [PASSED] 0xD751 (NOVALAKE_P)
[19:07:11] [PASSED] 0xD752 (NOVALAKE_P)
[19:07:11] [PASSED] 0xD753 (NOVALAKE_P)
[19:07:11] [PASSED] 0xD754 (NOVALAKE_P)
[19:07:11] [PASSED] 0xD755 (NOVALAKE_P)
[19:07:11] [PASSED] 0xD756 (NOVALAKE_P)
[19:07:11] [PASSED] 0xD757 (NOVALAKE_P)
[19:07:11] [PASSED] 0xD75F (NOVALAKE_P)
[19:07:11] =============== [PASSED] check_platform_desc ===============
[19:07:11] ===================== [PASSED] xe_pci ======================
[19:07:11] ============= xe_rtp_tables_test (5 subtests) ==============
[19:07:11] ================== xe_rtp_table_gt_test ===================
[19:07:11] [PASSED] gt_was/14011060649
[19:07:11] [PASSED] gt_was/14011059788
[19:07:11] [PASSED] gt_was/14015795083
[19:07:11] [PASSED] gt_was/16021867713
[19:07:11] [PASSED] gt_was/14019449301
[19:07:11] [PASSED] gt_was/16028005424
[19:07:11] [PASSED] gt_was/14026578760
[19:07:11] [PASSED] gt_was/1409420604
[19:07:11] [PASSED] gt_was/1408615072
[19:07:11] [PASSED] gt_was/22010523718
[19:07:11] [PASSED] gt_was/14011006942
[19:07:11] [PASSED] gt_was/14014830051
[19:07:11] [PASSED] gt_was/18018781329
[19:07:11] [PASSED] gt_was/1509235366
[19:07:11] [PASSED] gt_was/18018781329
[19:07:11] [PASSED] gt_was/16016694945
[19:07:11] [PASSED] gt_was/14018575942
[19:07:11] [PASSED] gt_was/22016670082
[19:07:11] [PASSED] gt_was/22016670082
[19:07:11] [PASSED] gt_was/14017421178
[19:07:11] [PASSED] gt_was/16025250150
[19:07:11] [PASSED] gt_was/14021871409
[19:07:11] [PASSED] gt_was/16021865536
[19:07:11] [PASSED] gt_was/14021486841
[19:07:11] [PASSED] gt_was/14025160223
[19:07:11] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[19:07:11] [PASSED] gt_was/14025635424
[19:07:11] [PASSED] gt_was/16028005424
[19:07:11] ============== [PASSED] xe_rtp_table_gt_test ===============
[19:07:11] ================== xe_rtp_table_gt_test ===================
[19:07:11] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[19:07:11] [PASSED] gt_tunings/Tuning: 32B Access Enable
[19:07:11] [PASSED] gt_tunings/Tuning: L3 cache
[19:07:11] [PASSED] gt_tunings/Tuning: L3 cache - media
[19:07:11] [PASSED] gt_tunings/Tuning: Compression Overfetch
[19:07:11] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[19:07:11] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[19:07:11] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[19:07:11] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[19:07:11] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[19:07:11] [PASSED] gt_tunings/Tuning: Stateless compression control
[19:07:11] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[19:07:11] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[19:07:11] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[19:07:11] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[19:07:11] [PASSED] gt_tunings/Tuning: Force All Non-Compressible Memory Reads to be 256B Overfetches
[19:07:11] ============== [PASSED] xe_rtp_table_gt_test ===============
[19:07:11] ================== xe_rtp_table_oob_test ==================
[19:07:11] [PASSED] oob_was/1607983814
[19:07:11] [PASSED] oob_was/16010904313
[19:07:11] [PASSED] oob_was/18022495364
[19:07:11] [PASSED] oob_was/22012773006
[19:07:11] [PASSED] oob_was/14014475959
[19:07:11] [PASSED] oob_was/22011391025
[19:07:11] [PASSED] oob_was/22012727170
[19:07:11] [PASSED] oob_was/22012727685
[19:07:11] [PASSED] oob_was/22016596838
[19:07:11] [PASSED] oob_was/18020744125
[19:07:11] [PASSED] oob_was/1409600907
[19:07:11] [PASSED] oob_was/22014953428
[19:07:11] [PASSED] oob_was/16017236439
[19:07:11] [PASSED] oob_was/14019821291
[19:07:11] [PASSED] oob_was/14015076503
[19:07:11] [PASSED] oob_was/22016122933
[19:07:11] [PASSED] oob_was/14018913170
[19:07:11] [PASSED] oob_was/14018094691
[19:07:11] [PASSED] oob_was/18024947630
[19:07:11] [PASSED] oob_was/16022287689
[19:07:11] [PASSED] oob_was/13011645652
[19:07:11] [PASSED] oob_was/14022293748
[19:07:11] [PASSED] oob_was/22019794406
[19:07:11] [PASSED] oob_was/22019338487
[19:07:11] [PASSED] oob_was/16023588340
[19:07:11] [PASSED] oob_was/14019789679
[19:07:11] [PASSED] oob_was/14022866841
[19:07:11] [PASSED] oob_was/16021333562
[19:07:11] [PASSED] oob_was/14016712196
[19:07:11] [PASSED] oob_was/14015568240
[19:07:11] [PASSED] oob_was/18013179988
[19:07:11] [PASSED] oob_was/1508761755
[19:07:11] [PASSED] oob_was/16023105232
[19:07:11] [PASSED] oob_was/16026508708
[19:07:11] [PASSED] oob_was/14020001231
[19:07:11] [PASSED] oob_was/16023683509
[19:07:11] [PASSED] oob_was/14025515070
[19:07:11] [PASSED] oob_was/15015404425_disable
[19:07:11] [PASSED] oob_was/16026007364
[19:07:11] [PASSED] oob_was/14020316580
[19:07:11] [PASSED] oob_was/14025883347
[19:07:11] [PASSED] oob_was/16029380221
[19:07:11] [PASSED] oob_was/22022079272
[19:07:11] [PASSED] oob_was/16029897822
[19:07:11] [PASSED] oob_was/14026539277
[19:07:11] [PASSED] oob_was/14027054324
[19:07:11] [PASSED] oob_was/14025941587
[19:07:11] [PASSED] oob_was/16030224309
[19:07:11] [PASSED] oob_was/14028709524
[19:07:11] ============== [PASSED] xe_rtp_table_oob_test ==============
[19:07:11] ================ xe_rtp_table_dev_oob_test ================
[19:07:11] [PASSED] device_oob_was/22010954014
[19:07:11] [PASSED] device_oob_was/15015404425
[19:07:11] [PASSED] device_oob_was/22019338487_display
[19:07:11] [PASSED] device_oob_was/14022085890
[19:07:11] [PASSED] device_oob_was/14026633728
[19:07:11] [PASSED] device_oob_was/14026746987
[19:07:11] [PASSED] device_oob_was/14026779378
[19:07:11] [PASSED] device_oob_was/14028586678
[19:07:11] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[19:07:11] ========== xe_rtp_table_missing_upper_bound_test ==========
[19:07:11] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[19:07:11] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[19:07:11] [PASSED] register_whitelist/1806527549
[19:07:11] [PASSED] register_whitelist/allow_read_ctx_timestamp
[19:07:11] [PASSED] register_whitelist/allow_read_queue_timestamp
[19:07:11] [PASSED] register_whitelist/16014440446
[19:07:11] [PASSED] register_whitelist/16017236439
[19:07:11] [PASSED] register_whitelist/16020183090
[19:07:11] [PASSED] register_whitelist/14024997852
[19:07:11] [PASSED] register_whitelist/14024997852
[19:07:11] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[19:07:11] =============== [PASSED] xe_rtp_tables_test ================
[19:07:11] =================== xe_rtp (3 subtests) ====================
[19:07:11] =================== xe_rtp_rules_tests ====================
[19:07:11] [PASSED] no
[19:07:11] [PASSED] yes
[19:07:11] [PASSED] no-and-no
[19:07:11] [PASSED] no-and-yes
[19:07:11] [PASSED] yes-and-no
[19:07:11] [PASSED] yes-and-yes
[19:07:11] [PASSED] no-or-no
[19:07:11] [PASSED] no-or-yes
[19:07:11] [PASSED] yes-or-no
[19:07:11] [PASSED] yes-or-yes
[19:07:11] [PASSED] no-yes-or-yes-no
[19:07:11] [PASSED] no-yes-or-yes-yes
[19:07:11] [PASSED] yes-yes-or-no-yes
[19:07:11] [PASSED] yes-yes-or-yes-yes
[19:07:11] [PASSED] no-no-or-yes-or-no
[19:07:11] [PASSED] or
[19:07:11] [PASSED] or-yes
[19:07:11] [PASSED] or-no
[19:07:11] [PASSED] yes-or
[19:07:11] [PASSED] no-or
[19:07:11] [PASSED] no-or-or-yes
[19:07:11] [PASSED] yes-or-or-no
[19:07:11] [PASSED] no-or-or-no
[19:07:11] [PASSED] missing-context-engine-class
[19:07:11] [PASSED] missing-context-engine-class-or-yes
[19:07:11] [PASSED] missing-context-engine-class-or-or-yes
[19:07:11] =============== [PASSED] xe_rtp_rules_tests ================
[19:07:11] =============== xe_rtp_process_to_sr_tests ================
[19:07:11] [PASSED] coalesce-same-reg
[19:07:11] [PASSED] coalesce-same-reg-literal-and-func
[19:07:11] [PASSED] no-match-no-add
[19:07:11] [PASSED] two-regs-two-entries
[19:07:11] [PASSED] clr-one-set-other
[19:07:11] [PASSED] set-field
[19:07:11] [PASSED] conflict-duplicate
[19:07:11] [PASSED] conflict-not-disjoint
[19:07:11] [PASSED] conflict-not-disjoint-literal-and-func
[19:07:11] [PASSED] conflict-reg-type
[19:07:11] [PASSED] bad-mcr-reg-forced-to-regular
[19:07:11] [PASSED] bad-regular-reg-forced-to-mcr
[19:07:11] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[19:07:11] ================== xe_rtp_process_tests ===================
[19:07:11] [PASSED] active1
[19:07:11] [PASSED] active2
[19:07:11] [PASSED] active-inactive
[19:07:11] [PASSED] inactive-active
[19:07:11] [PASSED] inactive-active-inactive
[19:07:11] [PASSED] inactive-inactive-inactive
[19:07:11] ============== [PASSED] xe_rtp_process_tests ===============
[19:07:11] ===================== [PASSED] xe_rtp ======================
[19:07:11] ==================== xe_wa (1 subtest) =====================
[19:07:11] ======================== xe_wa_gt =========================
[19:07:11] [PASSED] TIGERLAKE B0
[19:07:11] [PASSED] DG1 A0
[19:07:11] [PASSED] DG1 B0
[19:07:11] [PASSED] ALDERLAKE_S A0
[19:07:11] [PASSED] ALDERLAKE_S B0
[19:07:11] [PASSED] ALDERLAKE_S C0
[19:07:11] [PASSED] ALDERLAKE_S D0
[19:07:11] [PASSED] ALDERLAKE_P A0
[19:07:11] [PASSED] ALDERLAKE_P B0
[19:07:11] [PASSED] ALDERLAKE_P C0
[19:07:11] [PASSED] ALDERLAKE_S RPLS D0
[19:07:11] [PASSED] ALDERLAKE_P RPLU E0
[19:07:11] [PASSED] DG2 G10 C0
[19:07:11] [PASSED] DG2 G11 B1
[19:07:11] [PASSED] DG2 G12 A1
[19:07:11] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[19:07:11] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[19:07:11] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[19:07:11] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[19:07:11] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[19:07:11] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[19:07:11] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[19:07:11] ==================== [PASSED] xe_wa_gt =====================
[19:07:11] ====================== [PASSED] xe_wa ======================
[19:07:11] ============================================================
[19:07:11] Testing complete. Ran 841 tests: passed: 812, skipped: 29
[19:07:11] Elapsed time: 41.520s total, 2.502s configuring, 38.302s building, 0.692s running
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[19:07:11] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[19:07:14] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[19:07:39] Starting KUnit Kernel (1/1)...
[19:07:39] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[19:07:39] ============ drm_test_pick_cmdline (2 subtests) ============
[19:07:39] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[19:07:39] =============== drm_test_pick_cmdline_named ===============
[19:07:39] [PASSED] NTSC
[19:07:39] [PASSED] NTSC-J
[19:07:39] [PASSED] PAL
[19:07:39] [PASSED] PAL-M
[19:07:39] =========== [PASSED] drm_test_pick_cmdline_named ===========
[19:07:39] ============== [PASSED] drm_test_pick_cmdline ==============
[19:07:39] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[19:07:39] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[19:07:39] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[19:07:39] =========== drm_validate_clone_mode (2 subtests) ===========
[19:07:39] ============== drm_test_check_in_clone_mode ===============
[19:07:39] [PASSED] in_clone_mode
[19:07:39] [PASSED] not_in_clone_mode
[19:07:39] ========== [PASSED] drm_test_check_in_clone_mode ===========
[19:07:39] =============== drm_test_check_valid_clones ===============
[19:07:39] [PASSED] not_in_clone_mode
[19:07:39] [PASSED] valid_clone
[19:07:39] [PASSED] invalid_clone
[19:07:39] =========== [PASSED] drm_test_check_valid_clones ===========
[19:07:39] ============= [PASSED] drm_validate_clone_mode =============
[19:07:39] ============= drm_validate_modeset (1 subtest) =============
[19:07:39] [PASSED] drm_test_check_connector_changed_modeset
[19:07:39] ============== [PASSED] drm_validate_modeset ===============
[19:07:39] ====== drm_test_bridge_get_current_state (1 subtest) =======
[19:07:39] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[19:07:39] ======== [PASSED] drm_test_bridge_get_current_state ========
[19:07:39] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[19:07:39] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[19:07:39] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[19:07:39] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[19:07:39] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[19:07:39] ============== drm_bridge_alloc (2 subtests) ===============
[19:07:39] [PASSED] drm_test_drm_bridge_alloc_basic
[19:07:39] [PASSED] drm_test_drm_bridge_alloc_get_put
[19:07:39] ================ [PASSED] drm_bridge_alloc =================
[19:07:39] ============= drm_bridge_bus_fmt (5 subtests) ==============
[19:07:39] [PASSED] drm_test_bridge_rgb_yuv_rgb
[19:07:39] [PASSED] drm_test_bridge_must_convert_to_yuv444
[19:07:39] [PASSED] drm_test_bridge_hdmi_auto_rgb
[19:07:39] [PASSED] drm_test_bridge_auto_first
[19:07:39] [PASSED] drm_test_bridge_rgb_yuv_no_path
[19:07:39] =============== [PASSED] drm_bridge_bus_fmt ================
[19:07:39] ============= drm_cmdline_parser (40 subtests) =============
[19:07:39] [PASSED] drm_test_cmdline_force_d_only
[19:07:39] [PASSED] drm_test_cmdline_force_D_only_dvi
[19:07:39] [PASSED] drm_test_cmdline_force_D_only_hdmi
[19:07:39] [PASSED] drm_test_cmdline_force_D_only_not_digital
[19:07:39] [PASSED] drm_test_cmdline_force_e_only
[19:07:39] [PASSED] drm_test_cmdline_res
[19:07:39] [PASSED] drm_test_cmdline_res_vesa
[19:07:39] [PASSED] drm_test_cmdline_res_vesa_rblank
[19:07:39] [PASSED] drm_test_cmdline_res_rblank
[19:07:39] [PASSED] drm_test_cmdline_res_bpp
[19:07:39] [PASSED] drm_test_cmdline_res_refresh
[19:07:39] [PASSED] drm_test_cmdline_res_bpp_refresh
[19:07:39] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[19:07:39] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[19:07:39] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[19:07:39] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[19:07:39] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[19:07:39] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[19:07:39] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[19:07:39] [PASSED] drm_test_cmdline_res_margins_force_on
[19:07:39] [PASSED] drm_test_cmdline_res_vesa_margins
[19:07:39] [PASSED] drm_test_cmdline_name
[19:07:39] [PASSED] drm_test_cmdline_name_bpp
[19:07:39] [PASSED] drm_test_cmdline_name_option
[19:07:39] [PASSED] drm_test_cmdline_name_bpp_option
[19:07:39] [PASSED] drm_test_cmdline_rotate_0
[19:07:39] [PASSED] drm_test_cmdline_rotate_90
[19:07:39] [PASSED] drm_test_cmdline_rotate_180
[19:07:39] [PASSED] drm_test_cmdline_rotate_270
[19:07:39] [PASSED] drm_test_cmdline_hmirror
[19:07:39] [PASSED] drm_test_cmdline_vmirror
[19:07:39] [PASSED] drm_test_cmdline_margin_options
[19:07:39] [PASSED] drm_test_cmdline_multiple_options
[19:07:39] [PASSED] drm_test_cmdline_bpp_extra_and_option
[19:07:39] [PASSED] drm_test_cmdline_extra_and_option
[19:07:39] [PASSED] drm_test_cmdline_freestanding_options
[19:07:39] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[19:07:39] [PASSED] drm_test_cmdline_panel_orientation
[19:07:39] ================ drm_test_cmdline_invalid =================
[19:07:39] [PASSED] margin_only
[19:07:39] [PASSED] interlace_only
[19:07:39] [PASSED] res_missing_x
[19:07:39] [PASSED] res_missing_y
[19:07:39] [PASSED] res_bad_y
[19:07:39] [PASSED] res_missing_y_bpp
[19:07:39] [PASSED] res_bad_bpp
[19:07:39] [PASSED] res_bad_refresh
[19:07:39] [PASSED] res_bpp_refresh_force_on_off
[19:07:39] [PASSED] res_invalid_mode
[19:07:39] [PASSED] res_bpp_wrong_place_mode
[19:07:39] [PASSED] name_bpp_refresh
[19:07:39] [PASSED] name_refresh
[19:07:39] [PASSED] name_refresh_wrong_mode
[19:07:39] [PASSED] name_refresh_invalid_mode
[19:07:39] [PASSED] rotate_multiple
[19:07:39] [PASSED] rotate_invalid_val
[19:07:39] [PASSED] rotate_truncated
[19:07:39] [PASSED] invalid_option
[19:07:39] [PASSED] invalid_tv_option
[19:07:39] [PASSED] truncated_tv_option
[19:07:39] ============ [PASSED] drm_test_cmdline_invalid =============
[19:07:39] =============== drm_test_cmdline_tv_options ===============
[19:07:39] [PASSED] NTSC
[19:07:39] [PASSED] NTSC_443
[19:07:39] [PASSED] NTSC_J
[19:07:39] [PASSED] PAL
[19:07:39] [PASSED] PAL_M
[19:07:39] [PASSED] PAL_N
[19:07:39] [PASSED] SECAM
[19:07:39] [PASSED] MONO_525
[19:07:39] [PASSED] MONO_625
[19:07:39] =========== [PASSED] drm_test_cmdline_tv_options ===========
[19:07:39] =============== [PASSED] drm_cmdline_parser ================
[19:07:39] ========== drmm_connector_hdmi_init (20 subtests) ==========
[19:07:39] [PASSED] drm_test_connector_hdmi_init_valid
[19:07:39] [PASSED] drm_test_connector_hdmi_init_bpc_8
[19:07:39] [PASSED] drm_test_connector_hdmi_init_bpc_10
[19:07:39] [PASSED] drm_test_connector_hdmi_init_bpc_12
[19:07:39] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[19:07:39] [PASSED] drm_test_connector_hdmi_init_bpc_null
[19:07:39] [PASSED] drm_test_connector_hdmi_init_formats_empty
[19:07:39] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[19:07:39] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[19:07:39] [PASSED] supported_formats=0x9 yuv420_allowed=1
[19:07:39] [PASSED] supported_formats=0x9 yuv420_allowed=0
[19:07:39] [PASSED] supported_formats=0x5 yuv420_allowed=1
[19:07:39] [PASSED] supported_formats=0x5 yuv420_allowed=0
[19:07:39] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[19:07:39] [PASSED] drm_test_connector_hdmi_init_null_ddc
[19:07:39] [PASSED] drm_test_connector_hdmi_init_null_product
[19:07:39] [PASSED] drm_test_connector_hdmi_init_null_vendor
[19:07:39] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[19:07:39] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[19:07:39] [PASSED] drm_test_connector_hdmi_init_product_valid
[19:07:39] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[19:07:39] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[19:07:39] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[19:07:39] ========= drm_test_connector_hdmi_init_type_valid =========
[19:07:39] [PASSED] HDMI-A
[19:07:39] [PASSED] HDMI-B
[19:07:39] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[19:07:39] ======== drm_test_connector_hdmi_init_type_invalid ========
[19:07:39] [PASSED] Unknown
[19:07:39] [PASSED] VGA
[19:07:39] [PASSED] DVI-I
[19:07:39] [PASSED] DVI-D
[19:07:39] [PASSED] DVI-A
[19:07:39] [PASSED] Composite
[19:07:39] [PASSED] SVIDEO
[19:07:39] [PASSED] LVDS
[19:07:39] [PASSED] Component
[19:07:39] [PASSED] DIN
[19:07:39] [PASSED] DP
[19:07:39] [PASSED] TV
[19:07:39] [PASSED] eDP
[19:07:39] [PASSED] Virtual
[19:07:39] [PASSED] DSI
[19:07:39] [PASSED] DPI
[19:07:39] [PASSED] Writeback
[19:07:39] [PASSED] SPI
[19:07:39] [PASSED] USB
[19:07:39] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[19:07:39] ============ [PASSED] drmm_connector_hdmi_init =============
[19:07:39] ============= drmm_connector_init (3 subtests) =============
[19:07:39] [PASSED] drm_test_drmm_connector_init
[19:07:39] [PASSED] drm_test_drmm_connector_init_null_ddc
[19:07:39] ========= drm_test_drmm_connector_init_type_valid =========
[19:07:39] [PASSED] Unknown
[19:07:39] [PASSED] VGA
[19:07:39] [PASSED] DVI-I
[19:07:39] [PASSED] DVI-D
[19:07:39] [PASSED] DVI-A
[19:07:39] [PASSED] Composite
[19:07:39] [PASSED] SVIDEO
[19:07:39] [PASSED] LVDS
[19:07:39] [PASSED] Component
[19:07:39] [PASSED] DIN
[19:07:39] [PASSED] DP
[19:07:39] [PASSED] HDMI-A
[19:07:39] [PASSED] HDMI-B
[19:07:39] [PASSED] TV
[19:07:39] [PASSED] eDP
[19:07:39] [PASSED] Virtual
[19:07:39] [PASSED] DSI
[19:07:39] [PASSED] DPI
[19:07:39] [PASSED] Writeback
[19:07:39] [PASSED] SPI
[19:07:39] [PASSED] USB
[19:07:39] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[19:07:39] =============== [PASSED] drmm_connector_init ===============
[19:07:39] ========= drm_connector_dynamic_init (6 subtests) ==========
[19:07:39] [PASSED] drm_test_drm_connector_dynamic_init
[19:07:39] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[19:07:39] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[19:07:39] [PASSED] drm_test_drm_connector_dynamic_init_properties
[19:07:39] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[19:07:39] [PASSED] Unknown
[19:07:39] [PASSED] VGA
[19:07:39] [PASSED] DVI-I
[19:07:39] [PASSED] DVI-D
[19:07:39] [PASSED] DVI-A
[19:07:39] [PASSED] Composite
[19:07:39] [PASSED] SVIDEO
[19:07:39] [PASSED] LVDS
[19:07:39] [PASSED] Component
[19:07:39] [PASSED] DIN
[19:07:39] [PASSED] DP
[19:07:39] [PASSED] HDMI-A
[19:07:39] [PASSED] HDMI-B
[19:07:39] [PASSED] TV
[19:07:39] [PASSED] eDP
[19:07:39] [PASSED] Virtual
[19:07:39] [PASSED] DSI
[19:07:39] [PASSED] DPI
[19:07:39] [PASSED] Writeback
[19:07:39] [PASSED] SPI
[19:07:39] [PASSED] USB
[19:07:39] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[19:07:39] ======== drm_test_drm_connector_dynamic_init_name =========
[19:07:39] [PASSED] Unknown
[19:07:39] [PASSED] VGA
[19:07:39] [PASSED] DVI-I
[19:07:39] [PASSED] DVI-D
[19:07:39] [PASSED] DVI-A
[19:07:39] [PASSED] Composite
[19:07:39] [PASSED] SVIDEO
[19:07:39] [PASSED] LVDS
[19:07:39] [PASSED] Component
[19:07:39] [PASSED] DIN
[19:07:39] [PASSED] DP
[19:07:39] [PASSED] HDMI-A
[19:07:39] [PASSED] HDMI-B
[19:07:39] [PASSED] TV
[19:07:39] [PASSED] eDP
[19:07:39] [PASSED] Virtual
[19:07:39] [PASSED] DSI
[19:07:39] [PASSED] DPI
[19:07:39] [PASSED] Writeback
[19:07:39] [PASSED] SPI
[19:07:39] [PASSED] USB
[19:07:39] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[19:07:39] =========== [PASSED] drm_connector_dynamic_init ============
[19:07:39] ==== drm_connector_dynamic_register_early (4 subtests) =====
[19:07:39] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[19:07:39] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[19:07:39] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[19:07:39] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[19:07:39] ====== [PASSED] drm_connector_dynamic_register_early =======
[19:07:39] ======= drm_connector_dynamic_register (7 subtests) ========
[19:07:39] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[19:07:39] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[19:07:39] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[19:07:39] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[19:07:39] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[19:07:39] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[19:07:39] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[19:07:39] ========= [PASSED] drm_connector_dynamic_register ==========
[19:07:39] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[19:07:39] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[19:07:39] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[19:07:39] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[19:07:39] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[19:07:39] ========== drm_test_get_tv_mode_from_name_valid ===========
[19:07:39] [PASSED] NTSC
[19:07:39] [PASSED] NTSC-443
[19:07:39] [PASSED] NTSC-J
[19:07:39] [PASSED] PAL
[19:07:39] [PASSED] PAL-M
[19:07:39] [PASSED] PAL-N
[19:07:39] [PASSED] SECAM
[19:07:39] [PASSED] Mono
[19:07:39] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[19:07:39] [PASSED] drm_test_get_tv_mode_from_name_truncated
[19:07:39] ============ [PASSED] drm_get_tv_mode_from_name ============
[19:07:39] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[19:07:39] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[19:07:39] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[19:07:39] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[19:07:39] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[19:07:39] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[19:07:39] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[19:07:39] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[19:07:39] [PASSED] VIC 96
[19:07:39] [PASSED] VIC 97
[19:07:39] [PASSED] VIC 101
[19:07:39] [PASSED] VIC 102
[19:07:39] [PASSED] VIC 106
[19:07:39] [PASSED] VIC 107
[19:07:39] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[19:07:39] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[19:07:39] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[19:07:39] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[19:07:39] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[19:07:39] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[19:07:39] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[19:07:39] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[19:07:39] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[19:07:39] [PASSED] Automatic
[19:07:39] [PASSED] Full
[19:07:39] [PASSED] Limited 16:235
[19:07:39] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[19:07:39] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[19:07:39] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[19:07:39] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[19:07:39] === drm_test_drm_hdmi_connector_get_output_format_name ====
[19:07:39] [PASSED] RGB
[19:07:39] [PASSED] YUV 4:2:0
[19:07:39] [PASSED] YUV 4:2:2
[19:07:39] [PASSED] YUV 4:4:4
[19:07:39] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[19:07:39] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[19:07:39] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[19:07:39] ============= drm_damage_helper (21 subtests) ==============
[19:07:39] [PASSED] drm_test_damage_iter_no_damage
[19:07:39] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[19:07:39] [PASSED] drm_test_damage_iter_no_damage_src_moved
[19:07:39] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[19:07:39] [PASSED] drm_test_damage_iter_no_damage_not_visible
[19:07:39] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[19:07:39] [PASSED] drm_test_damage_iter_no_damage_no_fb
[19:07:39] [PASSED] drm_test_damage_iter_simple_damage
[19:07:39] [PASSED] drm_test_damage_iter_single_damage
[19:07:39] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[19:07:39] [PASSED] drm_test_damage_iter_single_damage_outside_src
[19:07:39] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[19:07:39] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[19:07:39] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[19:07:39] [PASSED] drm_test_damage_iter_single_damage_src_moved
[19:07:39] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[19:07:39] [PASSED] drm_test_damage_iter_damage
[19:07:39] [PASSED] drm_test_damage_iter_damage_one_intersect
[19:07:39] [PASSED] drm_test_damage_iter_damage_one_outside
[19:07:39] [PASSED] drm_test_damage_iter_damage_src_moved
[19:07:39] [PASSED] drm_test_damage_iter_damage_not_visible
[19:07:39] ================ [PASSED] drm_damage_helper ================
[19:07:39] ============== drm_dp_mst_helper (3 subtests) ==============
[19:07:39] ============== drm_test_dp_mst_calc_pbn_mode ==============
[19:07:39] [PASSED] Clock 154000 BPP 30 DSC disabled
[19:07:39] [PASSED] Clock 234000 BPP 30 DSC disabled
[19:07:39] [PASSED] Clock 297000 BPP 24 DSC disabled
[19:07:39] [PASSED] Clock 332880 BPP 24 DSC enabled
[19:07:39] [PASSED] Clock 324540 BPP 24 DSC enabled
[19:07:39] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[19:07:39] ============== drm_test_dp_mst_calc_pbn_div ===============
[19:07:39] [PASSED] Link rate 2000000 lane count 4
[19:07:39] [PASSED] Link rate 2000000 lane count 2
[19:07:39] [PASSED] Link rate 2000000 lane count 1
[19:07:39] [PASSED] Link rate 1350000 lane count 4
[19:07:39] [PASSED] Link rate 1350000 lane count 2
[19:07:39] [PASSED] Link rate 1350000 lane count 1
[19:07:39] [PASSED] Link rate 1000000 lane count 4
[19:07:39] [PASSED] Link rate 1000000 lane count 2
[19:07:39] [PASSED] Link rate 1000000 lane count 1
[19:07:39] [PASSED] Link rate 810000 lane count 4
[19:07:39] [PASSED] Link rate 810000 lane count 2
[19:07:39] [PASSED] Link rate 810000 lane count 1
[19:07:39] [PASSED] Link rate 540000 lane count 4
[19:07:39] [PASSED] Link rate 540000 lane count 2
[19:07:39] [PASSED] Link rate 540000 lane count 1
[19:07:39] [PASSED] Link rate 270000 lane count 4
[19:07:39] [PASSED] Link rate 270000 lane count 2
[19:07:39] [PASSED] Link rate 270000 lane count 1
[19:07:39] [PASSED] Link rate 162000 lane count 4
[19:07:39] [PASSED] Link rate 162000 lane count 2
[19:07:39] [PASSED] Link rate 162000 lane count 1
[19:07:39] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[19:07:39] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[19:07:39] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[19:07:39] [PASSED] DP_POWER_UP_PHY with port number
[19:07:39] [PASSED] DP_POWER_DOWN_PHY with port number
[19:07:39] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[19:07:39] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[19:07:39] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[19:07:39] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[19:07:39] [PASSED] DP_QUERY_PAYLOAD with port number
[19:07:39] [PASSED] DP_QUERY_PAYLOAD with VCPI
[19:07:39] [PASSED] DP_REMOTE_DPCD_READ with port number
[19:07:39] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[19:07:39] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[19:07:39] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[19:07:39] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[19:07:39] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[19:07:39] [PASSED] DP_REMOTE_I2C_READ with port number
[19:07:39] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[19:07:39] [PASSED] DP_REMOTE_I2C_READ with transactions array
[19:07:39] [PASSED] DP_REMOTE_I2C_WRITE with port number
[19:07:39] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[19:07:39] [PASSED] DP_REMOTE_I2C_WRITE with data array
[19:07:39] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[19:07:39] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[19:07:39] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[19:07:39] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[19:07:39] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[19:07:39] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[19:07:39] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[19:07:39] ================ [PASSED] drm_dp_mst_helper ================
[19:07:39] ================== drm_exec (7 subtests) ===================
[19:07:39] [PASSED] sanitycheck
[19:07:39] [PASSED] test_lock
[19:07:39] [PASSED] test_lock_unlock
[19:07:39] [PASSED] test_duplicates
[19:07:39] [PASSED] test_prepare
[19:07:39] [PASSED] test_prepare_array
[19:07:39] [PASSED] test_multiple_loops
[19:07:39] ==================== [PASSED] drm_exec =====================
[19:07:39] =========== drm_format_helper_test (17 subtests) ===========
[19:07:39] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[19:07:39] [PASSED] single_pixel_source_buffer
[19:07:39] [PASSED] single_pixel_clip_rectangle
[19:07:39] [PASSED] well_known_colors
[19:07:39] [PASSED] destination_pitch
[19:07:39] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[19:07:39] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[19:07:39] [PASSED] single_pixel_source_buffer
[19:07:39] [PASSED] single_pixel_clip_rectangle
[19:07:39] [PASSED] well_known_colors
[19:07:39] [PASSED] destination_pitch
[19:07:39] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[19:07:39] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[19:07:39] [PASSED] single_pixel_source_buffer
[19:07:39] [PASSED] single_pixel_clip_rectangle
[19:07:39] [PASSED] well_known_colors
[19:07:39] [PASSED] destination_pitch
[19:07:39] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[19:07:39] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[19:07:39] [PASSED] single_pixel_source_buffer
[19:07:39] [PASSED] single_pixel_clip_rectangle
[19:07:39] [PASSED] well_known_colors
[19:07:39] [PASSED] destination_pitch
[19:07:39] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[19:07:39] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[19:07:39] [PASSED] single_pixel_source_buffer
[19:07:39] [PASSED] single_pixel_clip_rectangle
[19:07:39] [PASSED] well_known_colors
[19:07:39] [PASSED] destination_pitch
[19:07:39] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[19:07:39] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[19:07:39] [PASSED] single_pixel_source_buffer
[19:07:39] [PASSED] single_pixel_clip_rectangle
[19:07:39] [PASSED] well_known_colors
[19:07:39] [PASSED] destination_pitch
[19:07:39] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[19:07:39] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[19:07:39] [PASSED] single_pixel_source_buffer
[19:07:39] [PASSED] single_pixel_clip_rectangle
[19:07:39] [PASSED] well_known_colors
[19:07:39] [PASSED] destination_pitch
[19:07:39] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[19:07:39] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[19:07:39] [PASSED] single_pixel_source_buffer
[19:07:39] [PASSED] single_pixel_clip_rectangle
[19:07:39] [PASSED] well_known_colors
[19:07:39] [PASSED] destination_pitch
[19:07:39] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[19:07:39] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[19:07:39] [PASSED] single_pixel_source_buffer
[19:07:39] [PASSED] single_pixel_clip_rectangle
[19:07:39] [PASSED] well_known_colors
[19:07:39] [PASSED] destination_pitch
[19:07:39] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[19:07:39] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[19:07:39] [PASSED] single_pixel_source_buffer
[19:07:39] [PASSED] single_pixel_clip_rectangle
[19:07:39] [PASSED] well_known_colors
[19:07:39] [PASSED] destination_pitch
[19:07:39] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[19:07:39] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[19:07:39] [PASSED] single_pixel_source_buffer
[19:07:39] [PASSED] single_pixel_clip_rectangle
[19:07:39] [PASSED] well_known_colors
[19:07:39] [PASSED] destination_pitch
[19:07:39] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[19:07:39] ============== drm_test_fb_xrgb8888_to_mono ===============
[19:07:39] [PASSED] single_pixel_source_buffer
[19:07:39] [PASSED] single_pixel_clip_rectangle
[19:07:39] [PASSED] well_known_colors
[19:07:39] [PASSED] destination_pitch
[19:07:39] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[19:07:39] ==================== drm_test_fb_swab =====================
[19:07:39] [PASSED] single_pixel_source_buffer
[19:07:39] [PASSED] single_pixel_clip_rectangle
[19:07:39] [PASSED] well_known_colors
[19:07:39] [PASSED] destination_pitch
[19:07:39] ================ [PASSED] drm_test_fb_swab =================
[19:07:39] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[19:07:39] [PASSED] single_pixel_source_buffer
[19:07:39] [PASSED] single_pixel_clip_rectangle
[19:07:39] [PASSED] well_known_colors
[19:07:39] [PASSED] destination_pitch
[19:07:39] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[19:07:39] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[19:07:39] [PASSED] single_pixel_source_buffer
[19:07:39] [PASSED] single_pixel_clip_rectangle
[19:07:39] [PASSED] well_known_colors
[19:07:39] [PASSED] destination_pitch
[19:07:39] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[19:07:39] ================= drm_test_fb_clip_offset =================
[19:07:39] [PASSED] pass through
[19:07:39] [PASSED] horizontal offset
[19:07:39] [PASSED] vertical offset
[19:07:39] [PASSED] horizontal and vertical offset
[19:07:39] [PASSED] horizontal offset (custom pitch)
[19:07:39] [PASSED] vertical offset (custom pitch)
[19:07:39] [PASSED] horizontal and vertical offset (custom pitch)
[19:07:39] ============= [PASSED] drm_test_fb_clip_offset =============
[19:07:39] =================== drm_test_fb_memcpy ====================
[19:07:39] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[19:07:39] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[19:07:39] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[19:07:39] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[19:07:39] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[19:07:39] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[19:07:39] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[19:07:39] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[19:07:39] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[19:07:39] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[19:07:39] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[19:07:39] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[19:07:39] =============== [PASSED] drm_test_fb_memcpy ================
[19:07:39] ============= [PASSED] drm_format_helper_test ==============
[19:07:39] ================= drm_format (18 subtests) =================
[19:07:39] [PASSED] drm_test_format_block_width_invalid
[19:07:39] [PASSED] drm_test_format_block_width_one_plane
[19:07:39] [PASSED] drm_test_format_block_width_two_plane
[19:07:39] [PASSED] drm_test_format_block_width_three_plane
[19:07:39] [PASSED] drm_test_format_block_width_tiled
[19:07:39] [PASSED] drm_test_format_block_height_invalid
[19:07:39] [PASSED] drm_test_format_block_height_one_plane
[19:07:39] [PASSED] drm_test_format_block_height_two_plane
[19:07:39] [PASSED] drm_test_format_block_height_three_plane
[19:07:39] [PASSED] drm_test_format_block_height_tiled
[19:07:39] [PASSED] drm_test_format_min_pitch_invalid
[19:07:39] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[19:07:39] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[19:07:39] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[19:07:39] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[19:07:39] [PASSED] drm_test_format_min_pitch_two_plane
[19:07:39] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[19:07:39] [PASSED] drm_test_format_min_pitch_tiled
[19:07:39] =================== [PASSED] drm_format ====================
[19:07:39] ============== drm_framebuffer (10 subtests) ===============
[19:07:39] ========== drm_test_framebuffer_check_src_coords ==========
[19:07:39] [PASSED] Success: source fits into fb
[19:07:39] [PASSED] Fail: overflowing fb with x-axis coordinate
[19:07:39] [PASSED] Fail: overflowing fb with y-axis coordinate
[19:07:39] [PASSED] Fail: overflowing fb with source width
[19:07:39] [PASSED] Fail: overflowing fb with source height
[19:07:39] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[19:07:39] [PASSED] drm_test_framebuffer_cleanup
[19:07:39] =============== drm_test_framebuffer_create ===============
[19:07:39] [PASSED] ABGR8888 normal sizes
[19:07:39] [PASSED] ABGR8888 max sizes
[19:07:39] [PASSED] ABGR8888 pitch greater than min required
[19:07:39] [PASSED] ABGR8888 pitch less than min required
[19:07:39] [PASSED] ABGR8888 Invalid width
[19:07:39] [PASSED] ABGR8888 Invalid buffer handle
[19:07:39] [PASSED] No pixel format
[19:07:39] [PASSED] ABGR8888 Width 0
[19:07:39] [PASSED] ABGR8888 Height 0
[19:07:39] [PASSED] ABGR8888 Out of bound height * pitch combination
[19:07:39] [PASSED] ABGR8888 Large buffer offset
[19:07:39] [PASSED] ABGR8888 Buffer offset for inexistent plane
[19:07:39] [PASSED] ABGR8888 Invalid flag
[19:07:39] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[19:07:39] [PASSED] ABGR8888 Valid buffer modifier
[19:07:39] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[19:07:39] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[19:07:39] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[19:07:39] [PASSED] NV12 Normal sizes
[19:07:39] [PASSED] NV12 Max sizes
[19:07:39] [PASSED] NV12 Invalid pitch
[19:07:39] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[19:07:39] [PASSED] NV12 different modifier per-plane
[19:07:39] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[19:07:39] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[19:07:39] [PASSED] NV12 Modifier for inexistent plane
[19:07:39] [PASSED] NV12 Handle for inexistent plane
[19:07:39] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[19:07:39] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[19:07:39] [PASSED] YVU420 Normal sizes
[19:07:39] [PASSED] YVU420 Max sizes
[19:07:39] [PASSED] YVU420 Invalid pitch
[19:07:39] [PASSED] YVU420 Different pitches
[19:07:39] [PASSED] YVU420 Different buffer offsets/pitches
[19:07:39] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[19:07:39] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[19:07:39] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[19:07:39] [PASSED] YVU420 Valid modifier
[19:07:39] [PASSED] YVU420 Different modifiers per plane
[19:07:39] [PASSED] YVU420 Modifier for inexistent plane
[19:07:39] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[19:07:39] [PASSED] X0L2 Normal sizes
[19:07:39] [PASSED] X0L2 Max sizes
[19:07:39] [PASSED] X0L2 Invalid pitch
[19:07:39] [PASSED] X0L2 Pitch greater than minimum required
[19:07:39] [PASSED] X0L2 Handle for inexistent plane
[19:07:39] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[19:07:39] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[19:07:39] [PASSED] X0L2 Valid modifier
[19:07:39] [PASSED] X0L2 Modifier for inexistent plane
[19:07:39] =========== [PASSED] drm_test_framebuffer_create ===========
[19:07:39] [PASSED] drm_test_framebuffer_free
[19:07:39] [PASSED] drm_test_framebuffer_init
[19:07:39] [PASSED] drm_test_framebuffer_init_bad_format
[19:07:39] [PASSED] drm_test_framebuffer_init_dev_mismatch
[19:07:39] [PASSED] drm_test_framebuffer_lookup
[19:07:39] [PASSED] drm_test_framebuffer_lookup_inexistent
[19:07:39] [PASSED] drm_test_framebuffer_modifiers_not_supported
[19:07:39] ================= [PASSED] drm_framebuffer =================
[19:07:39] ================ drm_gem_shmem (8 subtests) ================
[19:07:39] [PASSED] drm_gem_shmem_test_obj_create
[19:07:39] [PASSED] drm_gem_shmem_test_obj_create_private
[19:07:39] [PASSED] drm_gem_shmem_test_pin_pages
[19:07:39] [PASSED] drm_gem_shmem_test_vmap
[19:07:39] [PASSED] drm_gem_shmem_test_get_sg_table
[19:07:39] [PASSED] drm_gem_shmem_test_get_pages_sgt
[19:07:39] [PASSED] drm_gem_shmem_test_madvise
[19:07:39] [PASSED] drm_gem_shmem_test_purge
[19:07:39] ================== [PASSED] drm_gem_shmem ==================
[19:07:39] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[19:07:39] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[19:07:39] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[19:07:39] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[19:07:39] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[19:07:39] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[19:07:39] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[19:07:39] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[19:07:39] [PASSED] Automatic
[19:07:39] [PASSED] Full
[19:07:39] [PASSED] Limited 16:235
[19:07:39] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[19:07:39] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[19:07:39] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[19:07:39] [PASSED] drm_test_check_disable_connector
[19:07:39] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[19:07:39] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[19:07:39] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[19:07:39] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[19:07:39] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[19:07:39] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[19:07:39] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[19:07:39] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[19:07:39] [PASSED] drm_test_check_output_bpc_dvi
[19:07:39] [PASSED] drm_test_check_output_bpc_format_vic_1
[19:07:39] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[19:07:39] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[19:07:39] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[19:07:39] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[19:07:39] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[19:07:39] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[19:07:39] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[19:07:39] ============ drm_test_check_hdmi_color_format =============
[19:07:39] [PASSED] AUTO -> RGB
[19:07:39] [PASSED] YCBCR422 -> YUV422
[19:07:39] [PASSED] YCBCR420 -> YUV420
[19:07:39] [PASSED] YCBCR444 -> YUV444
[19:07:39] [PASSED] RGB -> RGB
[19:07:39] ======== [PASSED] drm_test_check_hdmi_color_format =========
[19:07:39] ======== drm_test_check_hdmi_color_format_420_only ========
[19:07:39] [PASSED] RGB should fail
[19:07:39] [PASSED] YUV444 should fail
[19:07:39] [PASSED] YUV422 should fail
[19:07:39] [PASSED] YUV420 should work
[19:07:39] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[19:07:39] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[19:07:39] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[19:07:39] [PASSED] drm_test_check_broadcast_rgb_value
[19:07:39] [PASSED] drm_test_check_bpc_8_value
[19:07:39] [PASSED] drm_test_check_bpc_10_value
[19:07:39] [PASSED] drm_test_check_bpc_12_value
[19:07:39] [PASSED] drm_test_check_format_value
[19:07:39] [PASSED] drm_test_check_tmds_char_value
[19:07:39] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[19:07:39] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[19:07:39] [PASSED] drm_test_check_mode_valid
[19:07:39] [PASSED] drm_test_check_mode_valid_reject
[19:07:39] [PASSED] drm_test_check_mode_valid_reject_rate
[19:07:39] [PASSED] drm_test_check_mode_valid_reject_max_clock
[19:07:39] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[19:07:39] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[19:07:39] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[19:07:39] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[19:07:39] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[19:07:39] [PASSED] drm_test_check_infoframes
[19:07:39] [PASSED] drm_test_check_reject_avi_infoframe
[19:07:39] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[19:07:39] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[19:07:39] [PASSED] drm_test_check_reject_audio_infoframe
[19:07:39] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[19:07:39] ================= drm_managed (2 subtests) =================
[19:07:39] [PASSED] drm_test_managed_release_action
[19:07:39] [PASSED] drm_test_managed_run_action
[19:07:39] =================== [PASSED] drm_managed ===================
[19:07:39] =================== drm_mm (6 subtests) ====================
[19:07:39] [PASSED] drm_test_mm_init
[19:07:39] [PASSED] drm_test_mm_debug
[19:07:39] [PASSED] drm_test_mm_align32
[19:07:39] [PASSED] drm_test_mm_align64
[19:07:39] [PASSED] drm_test_mm_lowest
[19:07:39] [PASSED] drm_test_mm_highest
[19:07:39] ===================== [PASSED] drm_mm ======================
[19:07:39] ============= drm_modes_analog_tv (5 subtests) =============
[19:07:39] [PASSED] drm_test_modes_analog_tv_mono_576i
[19:07:39] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[19:07:39] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[19:07:39] [PASSED] drm_test_modes_analog_tv_pal_576i
[19:07:39] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[19:07:39] =============== [PASSED] drm_modes_analog_tv ===============
[19:07:39] ============== drm_panic_helper (3 subtests) ===============
[19:07:39] ============= drm_test_panic_screen_user_map ==============
[19:07:39] [PASSED] Panic screen user, mode: 1024 x 768 XR24 little-endian (0x34325258)
[19:07:39] [PASSED] Panic screen user, mode: 494 x 494 XR24 little-endian (0x34325258)
[19:07:39] [PASSED] Panic screen user, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[19:07:39] [PASSED] Panic screen user, mode: 1024 x 768 RG16 little-endian (0x36314752)
[19:07:39] [PASSED] Panic screen user, mode: 1024 x 768 RG24 little-endian (0x34324752)
[19:07:39] [PASSED] Panic screen kmsg, mode: 1024 x 768 XR24 little-endian (0x34325258)
[19:07:39] [PASSED] Panic screen kmsg, mode: 494 x 494 XR24 little-endian (0x34325258)
[19:07:39] [PASSED] Panic screen kmsg, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[19:07:39] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG16 little-endian (0x36314752)
[19:07:39] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG24 little-endian (0x34324752)
[19:07:39] ========= [PASSED] drm_test_panic_screen_user_map ==========
[19:07:39] ============= drm_test_panic_screen_user_page =============
[19:07:39] [PASSED] Panic screen user, mode: 1024 x 768 XR24 little-endian (0x34325258)
[19:07:39] [PASSED] Panic screen user, mode: 494 x 494 XR24 little-endian (0x34325258)
[19:07:39] [PASSED] Panic screen user, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[19:07:39] [PASSED] Panic screen user, mode: 1024 x 768 RG16 little-endian (0x36314752)
[19:07:39] [PASSED] Panic screen user, mode: 1024 x 768 RG24 little-endian (0x34324752)
[19:07:39] [PASSED] Panic screen kmsg, mode: 1024 x 768 XR24 little-endian (0x34325258)
[19:07:39] [PASSED] Panic screen kmsg, mode: 494 x 494 XR24 little-endian (0x34325258)
[19:07:39] [PASSED] Panic screen kmsg, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[19:07:39] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG16 little-endian (0x36314752)
[19:07:39] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG24 little-endian (0x34324752)
[19:07:39] ========= [PASSED] drm_test_panic_screen_user_page =========
[19:07:39] ========== drm_test_panic_screen_user_set_pixel ===========
[19:07:39] [PASSED] Panic screen user, mode: 1024 x 768 XR24 little-endian (0x34325258)
[19:07:39] [PASSED] Panic screen user, mode: 494 x 494 XR24 little-endian (0x34325258)
[19:07:39] [PASSED] Panic screen user, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[19:07:39] [PASSED] Panic screen user, mode: 1024 x 768 RG16 little-endian (0x36314752)
[19:07:39] [PASSED] Panic screen user, mode: 1024 x 768 RG24 little-endian (0x34324752)
[19:07:39] [PASSED] Panic screen kmsg, mode: 1024 x 768 XR24 little-endian (0x34325258)
[19:07:39] [PASSED] Panic screen kmsg, mode: 494 x 494 XR24 little-endian (0x34325258)
[19:07:39] [PASSED] Panic screen kmsg, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[19:07:39] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG16 little-endian (0x36314752)
[19:07:39] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG24 little-endian (0x34324752)
[19:07:39] ====== [PASSED] drm_test_panic_screen_user_set_pixel =======
[19:07:39] ================ [PASSED] drm_panic_helper =================
[19:07:39] ============== drm_plane_helper (2 subtests) ===============
[19:07:39] =============== drm_test_check_plane_state ================
[19:07:39] [PASSED] clipping_simple
[19:07:39] [PASSED] clipping_rotate_reflect
[19:07:39] [PASSED] positioning_simple
[19:07:39] [PASSED] upscaling
[19:07:39] [PASSED] downscaling
[19:07:39] [PASSED] rounding1
[19:07:39] [PASSED] rounding2
[19:07:39] [PASSED] rounding3
[19:07:39] [PASSED] rounding4
[19:07:39] =========== [PASSED] drm_test_check_plane_state ============
[19:07:39] =========== drm_test_check_invalid_plane_state ============
[19:07:39] [PASSED] positioning_invalid
[19:07:39] [PASSED] upscaling_invalid
[19:07:39] [PASSED] downscaling_invalid
[19:07:39] ======= [PASSED] drm_test_check_invalid_plane_state ========
[19:07:39] ================ [PASSED] drm_plane_helper =================
[19:07:39] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[19:07:39] ====== drm_test_connector_helper_tv_get_modes_check =======
[19:07:39] [PASSED] None
[19:07:39] [PASSED] PAL
[19:07:39] [PASSED] NTSC
[19:07:39] [PASSED] Both, NTSC Default
[19:07:39] [PASSED] Both, PAL Default
[19:07:39] [PASSED] Both, NTSC Default, with PAL on command-line
[19:07:39] [PASSED] Both, PAL Default, with NTSC on command-line
[19:07:39] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[19:07:39] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[19:07:39] ================== drm_rect (9 subtests) ===================
[19:07:39] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[19:07:39] [PASSED] drm_test_rect_clip_scaled_not_clipped
[19:07:39] [PASSED] drm_test_rect_clip_scaled_clipped
[19:07:39] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[19:07:39] ================= drm_test_rect_intersect =================
[19:07:39] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[19:07:39] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[19:07:39] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[19:07:39] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[19:07:39] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[19:07:39] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[19:07:39] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[19:07:39] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[19:07:39] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[19:07:39] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[19:07:39] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[19:07:39] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[19:07:39] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[19:07:39] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[19:07:39] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[19:07:39] ============= [PASSED] drm_test_rect_intersect =============
[19:07:39] ================ drm_test_rect_calc_hscale ================
[19:07:39] [PASSED] normal use
[19:07:39] [PASSED] out of max range
[19:07:39] [PASSED] out of min range
[19:07:39] [PASSED] zero dst
[19:07:39] [PASSED] negative src
[19:07:39] [PASSED] negative dst
[19:07:39] ============ [PASSED] drm_test_rect_calc_hscale ============
[19:07:39] ================ drm_test_rect_calc_vscale ================
[19:07:39] [PASSED] normal use
[19:07:39] [PASSED] out of max range
[19:07:39] [PASSED] out of min range
[19:07:39] [PASSED] zero dst
[19:07:39] [PASSED] negative src
[19:07:39] [PASSED] negative dst
[19:07:39] ============ [PASSED] drm_test_rect_calc_vscale ============
[19:07:39] ================== drm_test_rect_rotate ===================
[19:07:39] [PASSED] reflect-x
[19:07:39] [PASSED] reflect-y
[19:07:39] [PASSED] rotate-0
[19:07:39] [PASSED] rotate-90
[19:07:39] [PASSED] rotate-180
[19:07:39] [PASSED] rotate-270
[19:07:39] ============== [PASSED] drm_test_rect_rotate ===============
[19:07:39] ================ drm_test_rect_rotate_inv =================
[19:07:39] [PASSED] reflect-x
[19:07:39] [PASSED] reflect-y
[19:07:39] [PASSED] rotate-0
[19:07:39] [PASSED] rotate-90
[19:07:39] [PASSED] rotate-180
[19:07:39] [PASSED] rotate-270
[19:07:39] ============ [PASSED] drm_test_rect_rotate_inv =============
[19:07:39] ==================== [PASSED] drm_rect =====================
[19:07:39] ============ drm_sysfb_modeset_test (1 subtest) ============
[19:07:39] ============ drm_test_sysfb_build_fourcc_list =============
[19:07:39] [PASSED] no native formats
[19:07:39] [PASSED] XRGB8888 as native format
[19:07:39] [PASSED] remove duplicates
[19:07:39] [PASSED] convert alpha formats
[19:07:39] [PASSED] random formats
[19:07:39] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[19:07:39] ============= [PASSED] drm_sysfb_modeset_test ==============
[19:07:39] ================== drm_fixp (2 subtests) ===================
[19:07:39] [PASSED] drm_test_int2fixp
[19:07:39] [PASSED] drm_test_sm2fixp
[19:07:39] ==================== [PASSED] drm_fixp =====================
[19:07:39] ============================================================
[19:07:39] Testing complete. Ran 667 tests: passed: 667
[19:07:39] Elapsed time: 28.165s total, 2.585s configuring, 25.112s building, 0.457s running
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[19:07:40] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[19:07:42] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[19:07:52] Starting KUnit Kernel (1/1)...
[19:07:52] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[19:07:52] ================= ttm_device (5 subtests) ==================
[19:07:52] [PASSED] ttm_device_init_basic
[19:07:52] [PASSED] ttm_device_init_multiple
[19:07:52] [PASSED] ttm_device_fini_basic
[19:07:52] [PASSED] ttm_device_init_no_vma_man
[19:07:52] ================== ttm_device_init_pools ==================
[19:07:52] [PASSED] No DMA allocations, no DMA32 required
[19:07:52] [PASSED] DMA allocations, DMA32 required
[19:07:52] [PASSED] No DMA allocations, DMA32 required
[19:07:52] [PASSED] DMA allocations, no DMA32 required
[19:07:52] ============== [PASSED] ttm_device_init_pools ==============
[19:07:52] =================== [PASSED] ttm_device ====================
[19:07:52] ================== ttm_pool (8 subtests) ===================
[19:07:52] ================== ttm_pool_alloc_basic ===================
[19:07:52] [PASSED] One page
[19:07:52] [PASSED] More than one page
[19:07:52] [PASSED] Above the allocation limit
[19:07:52] [PASSED] One page, with coherent DMA mappings enabled
[19:07:52] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[19:07:52] ============== [PASSED] ttm_pool_alloc_basic ===============
[19:07:52] ============== ttm_pool_alloc_basic_dma_addr ==============
[19:07:52] [PASSED] One page
[19:07:52] [PASSED] More than one page
[19:07:52] [PASSED] Above the allocation limit
[19:07:52] [PASSED] One page, with coherent DMA mappings enabled
[19:07:52] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[19:07:52] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[19:07:52] [PASSED] ttm_pool_alloc_order_caching_match
[19:07:52] [PASSED] ttm_pool_alloc_caching_mismatch
[19:07:52] [PASSED] ttm_pool_alloc_order_mismatch
[19:07:52] [PASSED] ttm_pool_free_dma_alloc
[19:07:52] [PASSED] ttm_pool_free_no_dma_alloc
[19:07:52] [PASSED] ttm_pool_fini_basic
[19:07:52] ==================== [PASSED] ttm_pool =====================
[19:07:52] ================ ttm_resource (8 subtests) =================
[19:07:52] ================= ttm_resource_init_basic =================
[19:07:52] [PASSED] Init resource in TTM_PL_SYSTEM
[19:07:52] [PASSED] Init resource in TTM_PL_VRAM
[19:07:52] [PASSED] Init resource in a private placement
[19:07:52] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[19:07:52] ============= [PASSED] ttm_resource_init_basic =============
[19:07:52] [PASSED] ttm_resource_init_pinned
[19:07:52] [PASSED] ttm_resource_fini_basic
[19:07:52] [PASSED] ttm_resource_manager_init_basic
[19:07:52] [PASSED] ttm_resource_manager_usage_basic
[19:07:52] [PASSED] ttm_resource_manager_set_used_basic
[19:07:52] [PASSED] ttm_sys_man_alloc_basic
[19:07:52] [PASSED] ttm_sys_man_free_basic
[19:07:52] ================== [PASSED] ttm_resource ===================
[19:07:52] =================== ttm_tt (15 subtests) ===================
[19:07:52] ==================== ttm_tt_init_basic ====================
[19:07:52] [PASSED] Page-aligned size
[19:07:52] [PASSED] Extra pages requested
[19:07:52] ================ [PASSED] ttm_tt_init_basic ================
[19:07:52] [PASSED] ttm_tt_init_misaligned
[19:07:52] [PASSED] ttm_tt_fini_basic
[19:07:52] [PASSED] ttm_tt_fini_sg
[19:07:52] [PASSED] ttm_tt_fini_shmem
[19:07:52] [PASSED] ttm_tt_create_basic
[19:07:52] [PASSED] ttm_tt_create_invalid_bo_type
[19:07:52] [PASSED] ttm_tt_create_ttm_exists
[19:07:52] [PASSED] ttm_tt_create_failed
[19:07:52] [PASSED] ttm_tt_destroy_basic
[19:07:52] [PASSED] ttm_tt_populate_null_ttm
[19:07:52] [PASSED] ttm_tt_populate_populated_ttm
[19:07:52] [PASSED] ttm_tt_unpopulate_basic
[19:07:52] [PASSED] ttm_tt_unpopulate_empty_ttm
[19:07:52] [PASSED] ttm_tt_swapin_basic
[19:07:52] ===================== [PASSED] ttm_tt ======================
[19:07:52] =================== ttm_bo (14 subtests) ===================
[19:07:52] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[19:07:52] [PASSED] Cannot be interrupted and sleeps
[19:07:52] [PASSED] Cannot be interrupted, locks straight away
[19:07:52] [PASSED] Can be interrupted, sleeps
[19:07:52] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[19:07:52] [PASSED] ttm_bo_reserve_locked_no_sleep
[19:07:52] [PASSED] ttm_bo_reserve_no_wait_ticket
[19:07:53] [PASSED] ttm_bo_reserve_double_resv
[19:07:53] [PASSED] ttm_bo_reserve_interrupted
[19:07:53] [PASSED] ttm_bo_reserve_deadlock
[19:07:53] [PASSED] ttm_bo_unreserve_basic
[19:07:53] [PASSED] ttm_bo_unreserve_pinned
[19:07:53] [PASSED] ttm_bo_unreserve_bulk
[19:07:53] [PASSED] ttm_bo_fini_basic
[19:07:53] [PASSED] ttm_bo_fini_shared_resv
[19:07:53] [PASSED] ttm_bo_pin_basic
[19:07:53] [PASSED] ttm_bo_pin_unpin_resource
[19:07:53] [PASSED] ttm_bo_multiple_pin_one_unpin
[19:07:53] ===================== [PASSED] ttm_bo ======================
[19:07:53] ============== ttm_bo_validate (22 subtests) ===============
[19:07:53] ============== ttm_bo_init_reserved_sys_man ===============
[19:07:53] [PASSED] Buffer object for userspace
[19:07:53] [PASSED] Kernel buffer object
[19:07:53] [PASSED] Shared buffer object
[19:07:53] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[19:07:53] ============== ttm_bo_init_reserved_mock_man ==============
[19:07:53] [PASSED] Buffer object for userspace
[19:07:53] [PASSED] Kernel buffer object
[19:07:53] [PASSED] Shared buffer object
[19:07:53] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[19:07:53] [PASSED] ttm_bo_init_reserved_resv
[19:07:53] ================== ttm_bo_validate_basic ==================
[19:07:53] [PASSED] Buffer object for userspace
[19:07:53] [PASSED] Kernel buffer object
[19:07:53] [PASSED] Shared buffer object
[19:07:53] ============== [PASSED] ttm_bo_validate_basic ==============
[19:07:53] [PASSED] ttm_bo_validate_invalid_placement
[19:07:53] ============= ttm_bo_validate_same_placement ==============
[19:07:53] [PASSED] System manager
[19:07:53] [PASSED] VRAM manager
[19:07:53] ========= [PASSED] ttm_bo_validate_same_placement ==========
[19:07:53] [PASSED] ttm_bo_validate_failed_alloc
[19:07:53] [PASSED] ttm_bo_validate_pinned
[19:07:53] [PASSED] ttm_bo_validate_busy_placement
[19:07:53] ================ ttm_bo_validate_multihop =================
[19:07:53] [PASSED] Buffer object for userspace
[19:07:53] [PASSED] Kernel buffer object
[19:07:53] [PASSED] Shared buffer object
[19:07:53] ============ [PASSED] ttm_bo_validate_multihop =============
[19:07:53] ========== ttm_bo_validate_no_placement_signaled ==========
[19:07:53] [PASSED] Buffer object in system domain, no page vector
[19:07:53] [PASSED] Buffer object in system domain with an existing page vector
[19:07:53] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[19:07:53] ======== ttm_bo_validate_no_placement_not_signaled ========
[19:07:53] [PASSED] Buffer object for userspace
[19:07:53] [PASSED] Kernel buffer object
[19:07:53] [PASSED] Shared buffer object
[19:07:53] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[19:07:53] [PASSED] ttm_bo_validate_move_fence_signaled
[19:07:53] ========= ttm_bo_validate_move_fence_not_signaled =========
[19:07:53] [PASSED] Waits for GPU
[19:07:53] [PASSED] Tries to lock straight away
[19:07:53] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[19:07:53] [PASSED] ttm_bo_validate_swapout
[19:07:53] [PASSED] ttm_bo_validate_happy_evict
[19:07:53] [PASSED] ttm_bo_validate_all_pinned_evict
[19:07:53] [PASSED] ttm_bo_validate_allowed_only_evict
[19:07:53] [PASSED] ttm_bo_validate_deleted_evict
[19:07:53] [PASSED] ttm_bo_validate_busy_domain_evict
[19:07:53] [PASSED] ttm_bo_validate_evict_gutting
[19:07:53] [PASSED] ttm_bo_validate_recrusive_evict
[19:07:53] ================= [PASSED] ttm_bo_validate =================
[19:07:53] ============================================================
[19:07:53] Testing complete. Ran 102 tests: passed: 102
[19:07:53] Elapsed time: 13.055s total, 2.538s configuring, 10.303s building, 0.181s running
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/dma-buf/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[19:07:53] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[19:07:55] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[19:08:04] Starting KUnit Kernel (1/1)...
[19:08:04] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[19:08:04] =============== dma-buf-fence (12 subtests) ================
[19:08:04] [PASSED] test_sanitycheck
[19:08:04] [PASSED] test_signaling
[19:08:04] [PASSED] test_add_callback
[19:08:04] [PASSED] test_late_add_callback
[19:08:04] [PASSED] test_rm_callback
[19:08:04] [PASSED] test_late_rm_callback
[19:08:04] [PASSED] test_status
[19:08:04] [PASSED] test_error
[19:08:04] [PASSED] test_wait
[19:08:04] [PASSED] test_wait_timeout
[19:08:04] [PASSED] test_stub
[19:08:04] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[19:08:04] ================== [PASSED] dma-buf-fence ==================
[19:08:04] ============ dma-buf-fence-chain (11 subtests) =============
[19:08:04] [PASSED] test_sanitycheck
[19:08:04] [PASSED] test_find_seqno
[19:08:04] [PASSED] test_find_signaled
[19:08:04] [PASSED] test_find_out_of_order
[19:08:09] [PASSED] test_find_gap
[19:08:09] [PASSED] test_find_race
[19:08:09] [PASSED] test_signal_forward
[19:08:09] [PASSED] test_signal_backward
[19:08:09] [PASSED] test_wait_forward
[19:08:09] [PASSED] test_wait_backward
[19:08:09] [PASSED] test_wait_random
[19:08:09] =============== [PASSED] dma-buf-fence-chain ===============
[19:08:09] ============ dma-buf-fence-unwrap (11 subtests) ============
[19:08:09] [PASSED] test_sanitycheck
[19:08:09] [PASSED] test_unwrap_array
[19:08:09] [PASSED] test_unwrap_chain
[19:08:09] [PASSED] test_unwrap_chain_array
[19:08:09] [PASSED] test_unwrap_merge
[19:08:09] [PASSED] test_unwrap_merge_duplicate
[19:08:09] [PASSED] test_unwrap_merge_seqno
[19:08:09] [PASSED] test_unwrap_merge_order
[19:08:09] [PASSED] test_unwrap_merge_complex
[19:08:09] [PASSED] test_unwrap_merge_complex_seqno
[19:08:09] [PASSED] test_dedup_empty
[19:08:09] ============== [PASSED] dma-buf-fence-unwrap ===============
[19:08:09] ================ dma-buf-resv (5 subtests) =================
[19:08:09] [PASSED] test_sanitycheck
[19:08:09] ===================== test_signaling ======================
[19:08:09] [PASSED] kernel
[19:08:09] [PASSED] write
[19:08:09] [PASSED] read
[19:08:09] [PASSED] bookkeep
[19:08:09] ================= [PASSED] test_signaling ==================
[19:08:09] ====================== test_for_each ======================
[19:08:09] [PASSED] kernel
[19:08:09] [PASSED] write
[19:08:09] [PASSED] read
[19:08:09] [PASSED] bookkeep
[19:08:09] ================== [PASSED] test_for_each ==================
[19:08:09] ================= test_for_each_unlocked ==================
[19:08:09] [PASSED] kernel
[19:08:09] [PASSED] write
[19:08:09] [PASSED] read
[19:08:09] [PASSED] bookkeep
[19:08:09] ============= [PASSED] test_for_each_unlocked ==============
[19:08:09] ===================== test_get_fences =====================
[19:08:09] [PASSED] kernel
[19:08:09] [PASSED] write
[19:08:09] [PASSED] read
[19:08:09] [PASSED] bookkeep
[19:08:09] ================= [PASSED] test_get_fences =================
[19:08:09] ================== [PASSED] dma-buf-resv ===================
[19:08:09] ============================================================
[19:08:09] Testing complete. Ran 51 tests: passed: 50, skipped: 1
[19:08:09] Elapsed time: 16.530s total, 2.452s configuring, 8.706s building, 5.357s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 8+ messages in thread
* ✓ Xe.CI.BAT: success for Extend CPER records with RAS info queue data
2026-11-06 18:59 [PATCH v6 0/2] Extend CPER records with RAS info queue data Badal Nilawar
` (2 preceding siblings ...)
2026-11-06 19:08 ` ✓ CI.KUnit: success for Extend CPER records with RAS info queue data Patchwork
@ 2026-11-06 19:43 ` Patchwork
2026-11-07 23:49 ` ✓ Xe.CI.FULL: " Patchwork
4 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2026-11-06 19:43 UTC (permalink / raw)
To: Badal Nilawar; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 7767 bytes --]
== Series Details ==
Series: Extend CPER records with RAS info queue data
URL : https://patchwork.freedesktop.org/series/178015/
State : success
== Summary ==
CI Bug Log - changes from xe-6082-e96f23b42352b7b9fea6bf92bceed052533fb98e_BAT -> xe-pw-178015v1_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (14 -> 15)
------------------------------
Additional (1): bat-atsm-2
Known issues
------------
Here are the changes found in xe-pw-178015v1_BAT that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@fbdev@write:
- bat-atsm-2: NOTRUN -> [SKIP][1] ([Intel XE#2134]) +4 other tests skip
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/bat-atsm-2/igt@fbdev@write.html
* igt@kms_addfb_basic@addfb25-yf-tiled-legacy:
- bat-atsm-2: NOTRUN -> [SKIP][2] ([i915#6077]) +30 other tests skip
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/bat-atsm-2/igt@kms_addfb_basic@addfb25-yf-tiled-legacy.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- bat-atsm-2: NOTRUN -> [SKIP][3] ([Intel XE#1024] / [Intel XE#782] / [Intel XE#947]) +5 other tests skip
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/bat-atsm-2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
* igt@kms_dsc@dsc-basic:
- bat-atsm-2: NOTRUN -> [SKIP][4] ([Intel XE#1024] / [Intel XE#784] / [Intel XE#947])
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/bat-atsm-2/igt@kms_dsc@dsc-basic.html
* igt@kms_frontbuffer_tracking@basic:
- bat-atsm-2: NOTRUN -> [SKIP][5] ([Intel XE#1024] / [Intel XE#783] / [Intel XE#947])
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/bat-atsm-2/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_hdmi_inject@inject-audio:
- bat-atsm-2: NOTRUN -> [SKIP][6] ([Intel XE#540]) +3 other tests skip
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/bat-atsm-2/igt@kms_hdmi_inject@inject-audio.html
* igt@kms_pipe_crc_basic@nonblocking-crc:
- bat-atsm-2: NOTRUN -> [SKIP][7] ([Intel XE#829] / [i915#1836]) +6 other tests skip
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/bat-atsm-2/igt@kms_pipe_crc_basic@nonblocking-crc.html
* igt@kms_prop_blob@basic:
- bat-atsm-2: NOTRUN -> [SKIP][8] ([Intel XE#780])
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/bat-atsm-2/igt@kms_prop_blob@basic.html
* igt@kms_psr@psr-primary-page-flip:
- bat-atsm-2: NOTRUN -> [SKIP][9] ([Intel XE#1024] / [Intel XE#947]) +6 other tests skip
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/bat-atsm-2/igt@kms_psr@psr-primary-page-flip.html
* igt@xe_compute_preempt@compute-preempt:
- bat-atsm-2: NOTRUN -> [SKIP][10] ([Intel XE#8380]) +1 other test skip
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/bat-atsm-2/igt@xe_compute_preempt@compute-preempt.html
* igt@xe_exec_fault_mode@invalid-va:
- bat-atsm-2: NOTRUN -> [SKIP][11] ([Intel XE#8381])
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/bat-atsm-2/igt@xe_exec_fault_mode@invalid-va.html
* igt@xe_exec_fault_mode@twice-userptr-prefetch:
- bat-atsm-2: NOTRUN -> [SKIP][12] ([Intel XE#288]) +32 other tests skip
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/bat-atsm-2/igt@xe_exec_fault_mode@twice-userptr-prefetch.html
* igt@xe_exec_mix_modes@exec-simple-batch-store-dma-fence:
- bat-atsm-2: NOTRUN -> [SKIP][13] ([Intel XE#8376]) +3 other tests skip
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/bat-atsm-2/igt@xe_exec_mix_modes@exec-simple-batch-store-dma-fence.html
* igt@xe_exec_multi_queue@many-queues-preempt-mode-userptr:
- bat-atsm-2: NOTRUN -> [SKIP][14] ([Intel XE#8364]) +13 other tests skip
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/bat-atsm-2/igt@xe_exec_multi_queue@many-queues-preempt-mode-userptr.html
* igt@xe_exec_system_allocator@twice-free:
- bat-atsm-2: NOTRUN -> [SKIP][15] ([Intel XE#8379]) +11 other tests skip
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/bat-atsm-2/igt@xe_exec_system_allocator@twice-free.html
* igt@xe_huc_copy@huc_copy:
- bat-atsm-2: NOTRUN -> [SKIP][16] ([Intel XE#255])
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/bat-atsm-2/igt@xe_huc_copy@huc_copy.html
* igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit:
- bat-atsm-2: NOTRUN -> [SKIP][17] ([Intel XE#2229])
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/bat-atsm-2/igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit.html
* igt@xe_pat@pat-index-auto:
- bat-atsm-2: NOTRUN -> [SKIP][18] ([Intel XE#8434])
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/bat-atsm-2/igt@xe_pat@pat-index-auto.html
* igt@xe_pat@pat-index-xe2:
- bat-atsm-2: NOTRUN -> [SKIP][19] ([Intel XE#977])
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/bat-atsm-2/igt@xe_pat@pat-index-xe2.html
* igt@xe_pat@pat-index-xehpc:
- bat-atsm-2: NOTRUN -> [SKIP][20] ([Intel XE#2838] / [Intel XE#979])
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/bat-atsm-2/igt@xe_pat@pat-index-xehpc.html
* igt@xe_pat@pat-index-xelpg:
- bat-atsm-2: NOTRUN -> [SKIP][21] ([Intel XE#979])
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/bat-atsm-2/igt@xe_pat@pat-index-xelpg.html
[Intel XE#1024]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1024
[Intel XE#2134]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2134
[Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
[Intel XE#255]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/255
[Intel XE#2838]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2838
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/540
[Intel XE#780]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/780
[Intel XE#782]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/782
[Intel XE#783]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/783
[Intel XE#784]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/784
[Intel XE#829]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/829
[Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
[Intel XE#8376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8376
[Intel XE#8379]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8379
[Intel XE#8380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8380
[Intel XE#8381]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8381
[Intel XE#8434]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8434
[Intel XE#947]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/947
[Intel XE#977]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/977
[Intel XE#979]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/979
[i915#1836]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1836
[i915#6077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6077
Build changes
-------------
* Linux: xe-6082-e96f23b42352b7b9fea6bf92bceed052533fb98e -> xe-pw-178015v1
IGT_9181: 9181
xe-6082-e96f23b42352b7b9fea6bf92bceed052533fb98e: e96f23b42352b7b9fea6bf92bceed052533fb98e
xe-pw-178015v1: 178015v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/index.html
[-- Attachment #2: Type: text/html, Size: 9280 bytes --]
^ permalink raw reply [flat|nested] 8+ messages in thread
* ✓ Xe.CI.FULL: success for Extend CPER records with RAS info queue data
2026-11-06 18:59 [PATCH v6 0/2] Extend CPER records with RAS info queue data Badal Nilawar
` (3 preceding siblings ...)
2026-11-06 19:43 ` ✓ Xe.CI.BAT: " Patchwork
@ 2026-11-07 23:49 ` Patchwork
4 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2026-11-07 23:49 UTC (permalink / raw)
To: Badal Nilawar; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 30538 bytes --]
== Series Details ==
Series: Extend CPER records with RAS info queue data
URL : https://patchwork.freedesktop.org/series/178015/
State : success
== Summary ==
CI Bug Log - changes from xe-6082-e96f23b42352b7b9fea6bf92bceed052533fb98e_FULL -> xe-pw-178015v1_FULL
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (3 -> 3)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in xe-pw-178015v1_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@core_hotunplug@hotunbind-rebind:
- shard-bmg: [PASS][1] -> [ABORT][2] ([Intel XE#9463])
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6082-e96f23b42352b7b9fea6bf92bceed052533fb98e/shard-bmg-5/igt@core_hotunplug@hotunbind-rebind.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-bmg-7/igt@core_hotunplug@hotunbind-rebind.html
* igt@kms_3d@basic:
- shard-lnl: NOTRUN -> [SKIP][3] ([Intel XE#6011])
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-7/igt@kms_3d@basic.html
* igt@kms_async_flips@alternate-sync-async-flip:
- shard-bmg: [PASS][4] -> [FAIL][5] ([Intel XE#3718] / [Intel XE#6078])
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6082-e96f23b42352b7b9fea6bf92bceed052533fb98e/shard-bmg-4/igt@kms_async_flips@alternate-sync-async-flip.html
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-bmg-2/igt@kms_async_flips@alternate-sync-async-flip.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-b-dp-2:
- shard-bmg: [PASS][6] -> [FAIL][7] ([Intel XE#6078])
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6082-e96f23b42352b7b9fea6bf92bceed052533fb98e/shard-bmg-4/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-dp-2.html
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-bmg-2/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-dp-2.html
* igt@kms_big_fb@y-tiled-32bpp-rotate-0:
- shard-lnl: NOTRUN -> [SKIP][8] ([Intel XE#1124]) +3 other tests skip
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-4/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html
- shard-ptl: NOTRUN -> [SKIP][9] ([Intel XE#5808])
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-ptl-8/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0:
- shard-bmg: NOTRUN -> [SKIP][10] ([Intel XE#1124])
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-bmg-5/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs:
- shard-lnl: NOTRUN -> [SKIP][11] ([Intel XE#2887]) +4 other tests skip
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-7/igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs:
- shard-bmg: NOTRUN -> [SKIP][12] ([Intel XE#2887]) +1 other test skip
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-bmg-5/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
- shard-bmg: [PASS][13] -> [INCOMPLETE][14] ([Intel XE#7084] / [Intel XE#8150]) +1 other test incomplete
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6082-e96f23b42352b7b9fea6bf92bceed052533fb98e/shard-bmg-10/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-bmg-5/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
* igt@kms_chamelium_color@ctm-limited-range:
- shard-ptl: NOTRUN -> [SKIP][15] ([Intel XE#5824])
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-ptl-8/igt@kms_chamelium_color@ctm-limited-range.html
* igt@kms_chamelium_color@degamma:
- shard-bmg: NOTRUN -> [SKIP][16] ([Intel XE#2325] / [Intel XE#7358])
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-bmg-5/igt@kms_chamelium_color@degamma.html
* igt@kms_chamelium_color@gamma:
- shard-lnl: NOTRUN -> [SKIP][17] ([Intel XE#306] / [Intel XE#7358]) +1 other test skip
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-7/igt@kms_chamelium_color@gamma.html
* igt@kms_chamelium_edid@hdmi-edid-change-during-suspend:
- shard-ptl: NOTRUN -> [SKIP][18] ([Intel XE#2252])
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-ptl-8/igt@kms_chamelium_edid@hdmi-edid-change-during-suspend.html
* igt@kms_chamelium_hpd@hdmi-hpd-for-each-pipe:
- shard-lnl: NOTRUN -> [SKIP][19] ([Intel XE#373]) +3 other tests skip
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-7/igt@kms_chamelium_hpd@hdmi-hpd-for-each-pipe.html
* igt@kms_content_protection@type1:
- shard-lnl: NOTRUN -> [SKIP][20] ([Intel XE#7642])
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-7/igt@kms_content_protection@type1.html
* igt@kms_cursor_crc@cursor-random-32x10:
- shard-ptl: NOTRUN -> [SKIP][21] ([Intel XE#5900])
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-ptl-8/igt@kms_cursor_crc@cursor-random-32x10.html
- shard-lnl: NOTRUN -> [SKIP][22] ([Intel XE#1424]) +1 other test skip
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-4/igt@kms_cursor_crc@cursor-random-32x10.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size:
- shard-bmg: [PASS][23] -> [INCOMPLETE][24] ([Intel XE#8151])
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6082-e96f23b42352b7b9fea6bf92bceed052533fb98e/shard-bmg-7/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-bmg-3/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic:
- shard-lnl: NOTRUN -> [SKIP][25] ([Intel XE#309] / [Intel XE#7343])
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-7/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size:
- shard-ptl: NOTRUN -> [SKIP][26] ([Intel XE#5962] / [Intel XE#7343])
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-ptl-7/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html
* igt@kms_dsc@dsc-with-bpc:
- shard-ptl: NOTRUN -> [SKIP][27] ([Intel XE#5907])
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-ptl-8/igt@kms_dsc@dsc-with-bpc.html
- shard-lnl: NOTRUN -> [SKIP][28] ([Intel XE#8265]) +2 other tests skip
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-4/igt@kms_dsc@dsc-with-bpc.html
* igt@kms_flip@2x-plain-flip-ts-check:
- shard-lnl: NOTRUN -> [SKIP][29] ([Intel XE#1421]) +2 other tests skip
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-7/igt@kms_flip@2x-plain-flip-ts-check.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling:
- shard-lnl: NOTRUN -> [SKIP][30] ([Intel XE#7178] / [Intel XE#7351]) +1 other test skip
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-7/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling:
- shard-bmg: NOTRUN -> [SKIP][31] ([Intel XE#7178] / [Intel XE#7351])
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-bmg-5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html
* igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-blt:
- shard-ptl: NOTRUN -> [SKIP][32] ([Intel XE#5800] / [Intel XE#6312])
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-ptl-8/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-blt:
- shard-bmg: NOTRUN -> [SKIP][33] ([Intel XE#2311]) +2 other tests skip
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@drrs-slowdraw:
- shard-lnl: NOTRUN -> [SKIP][34] ([Intel XE#6312] / [Intel XE#651]) +3 other tests skip
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-7/igt@kms_frontbuffer_tracking@drrs-slowdraw.html
* igt@kms_frontbuffer_tracking@drrshdr-1p-offscreen-pri-indfb-draw-blt:
- shard-ptl: NOTRUN -> [SKIP][35] ([Intel XE#6312])
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-ptl-8/igt@kms_frontbuffer_tracking@drrshdr-1p-offscreen-pri-indfb-draw-blt.html
- shard-lnl: NOTRUN -> [SKIP][36] ([Intel XE#6312]) +2 other tests skip
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-4/igt@kms_frontbuffer_tracking@drrshdr-1p-offscreen-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbchdr-abgr161616f-draw-mmap-wc:
- shard-lnl: NOTRUN -> [SKIP][37] ([Intel XE#7061]) +2 other tests skip
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-7/igt@kms_frontbuffer_tracking@fbchdr-abgr161616f-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-onoff:
- shard-lnl: NOTRUN -> [SKIP][38] ([Intel XE#656] / [Intel XE#7905]) +10 other tests skip
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-render:
- shard-lnl: NOTRUN -> [SKIP][39] ([Intel XE#7061] / [Intel XE#7356]) +1 other test skip
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-7/igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-scndscrn-indfb-plflip-blt:
- shard-ptl: NOTRUN -> [SKIP][40] ([Intel XE#5812]) +3 other tests skip
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-ptl-8/igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-scndscrn-indfb-plflip-blt.html
- shard-lnl: NOTRUN -> [SKIP][41] ([Intel XE#7905]) +14 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-4/igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-scndscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-scndscrn-spr-indfb-draw-render:
- shard-bmg: NOTRUN -> [SKIP][42] ([Intel XE#2313]) +2 other tests skip
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-scndscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@hdr-1p-primscrn-shrfb-msflip-blt:
- shard-ptl: NOTRUN -> [SKIP][43] ([Intel XE#7865])
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-ptl-8/igt@kms_frontbuffer_tracking@hdr-1p-primscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@psrhdr-1p-offscreen-pri-indfb-draw-blt:
- shard-lnl: NOTRUN -> [SKIP][44] ([Intel XE#7865]) +5 other tests skip
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-7/igt@kms_frontbuffer_tracking@psrhdr-1p-offscreen-pri-indfb-draw-blt.html
* igt@kms_hdr@brightness-with-hdr:
- shard-bmg: NOTRUN -> [SKIP][45] ([Intel XE#3374] / [Intel XE#3544])
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-bmg-5/igt@kms_hdr@brightness-with-hdr.html
* igt@kms_hdr@static-swap:
- shard-lnl: NOTRUN -> [SKIP][46] ([Intel XE#1503])
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-7/igt@kms_hdr@static-swap.html
* igt@kms_joiner@basic-force-ultra-joiner:
- shard-bmg: NOTRUN -> [SKIP][47] ([Intel XE#6911] / [Intel XE#7466])
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-bmg-5/igt@kms_joiner@basic-force-ultra-joiner.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-ptl: NOTRUN -> [SKIP][48] ([Intel XE#7591])
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-ptl-8/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
- shard-lnl: NOTRUN -> [SKIP][49] ([Intel XE#7591])
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-4/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-modifier:
- shard-lnl: NOTRUN -> [SKIP][50] ([Intel XE#7283])
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-7/igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-modifier.html
* igt@kms_pm_backlight@fade:
- shard-bmg: NOTRUN -> [SKIP][51] ([Intel XE#7376] / [Intel XE#7760] / [Intel XE#870])
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-bmg-5/igt@kms_pm_backlight@fade.html
* igt@kms_pm_rpm@dpms-non-lpsp:
- shard-ptl: NOTRUN -> [SKIP][52] ([Intel XE#5849])
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-ptl-8/igt@kms_pm_rpm@dpms-non-lpsp.html
- shard-lnl: NOTRUN -> [SKIP][53] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#7383])
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-4/igt@kms_pm_rpm@dpms-non-lpsp.html
* igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area:
- shard-bmg: NOTRUN -> [SKIP][54] ([Intel XE#1489])
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-bmg-5/igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-lnl: NOTRUN -> [SKIP][55] ([Intel XE#1128] / [Intel XE#7413]) +1 other test skip
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-7/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr2_su@page_flip-p010:
- shard-ptl: NOTRUN -> [SKIP][56] ([Intel XE#7413])
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-ptl-8/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr@fbc-pr-suspend:
- shard-ptl: NOTRUN -> [SKIP][57] ([Intel XE#1406])
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-ptl-8/igt@kms_psr@fbc-pr-suspend.html
* igt@kms_psr@pr-primary-page-flip:
- shard-lnl: NOTRUN -> [SKIP][58] ([Intel XE#1406]) +1 other test skip
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-7/igt@kms_psr@pr-primary-page-flip.html
* igt@kms_rotation_crc@bad-pixel-format:
- shard-ptl: NOTRUN -> [SKIP][59] ([Intel XE#5821])
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-ptl-8/igt@kms_rotation_crc@bad-pixel-format.html
- shard-lnl: NOTRUN -> [SKIP][60] ([Intel XE#3904] / [Intel XE#7342])
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-4/igt@kms_rotation_crc@bad-pixel-format.html
* igt@kms_vrr@flip-suspend@pipe-a-edp-1:
- shard-ptl: [PASS][61] -> [FAIL][62] ([Intel XE#4227] / [Intel XE#7397]) +1 other test fail
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6082-e96f23b42352b7b9fea6bf92bceed052533fb98e/shard-ptl-3/igt@kms_vrr@flip-suspend@pipe-a-edp-1.html
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-ptl-2/igt@kms_vrr@flip-suspend@pipe-a-edp-1.html
* igt@xe_ccs@vm-bind-fault-mode-decompress:
- shard-lnl: NOTRUN -> [SKIP][63] ([Intel XE#7644])
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-7/igt@xe_ccs@vm-bind-fault-mode-decompress.html
* igt@xe_evict@evict-beng-threads-large:
- shard-ptl: NOTRUN -> [SKIP][64] ([Intel XE#5764])
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-ptl-8/igt@xe_evict@evict-beng-threads-large.html
* igt@xe_evict@evict-large-external:
- shard-lnl: NOTRUN -> [SKIP][65] ([Intel XE#6540] / [Intel XE#688]) +2 other tests skip
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-7/igt@xe_evict@evict-large-external.html
* igt@xe_evict@evict-small-external-multi-queue:
- shard-bmg: NOTRUN -> [SKIP][66] ([Intel XE#8370])
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-bmg-5/igt@xe_evict@evict-small-external-multi-queue.html
* igt@xe_exec_balancer@twice-parallel-rebind:
- shard-ptl: NOTRUN -> [SKIP][67] ([Intel XE#7482])
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-ptl-8/igt@xe_exec_balancer@twice-parallel-rebind.html
* igt@xe_exec_balancer@twice-parallel-userptr-invalidate-race:
- shard-lnl: NOTRUN -> [SKIP][68] ([Intel XE#7482]) +5 other tests skip
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-7/igt@xe_exec_balancer@twice-parallel-userptr-invalidate-race.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-null-rebind:
- shard-bmg: NOTRUN -> [SKIP][69] ([Intel XE#2322] / [Intel XE#7372])
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-bmg-5/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-null-rebind.html
* igt@xe_exec_basic@multigpu-no-exec-rebind:
- shard-ptl: NOTRUN -> [SKIP][70] ([Intel XE#5575] / [Intel XE#7484])
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-ptl-8/igt@xe_exec_basic@multigpu-no-exec-rebind.html
* igt@xe_exec_basic@multigpu-once-userptr-invalidate:
- shard-lnl: NOTRUN -> [SKIP][71] ([Intel XE#1392]) +3 other tests skip
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-7/igt@xe_exec_basic@multigpu-once-userptr-invalidate.html
* igt@xe_exec_fault_mode@once-multi-queue-rebind-imm:
- shard-ptl: NOTRUN -> [SKIP][72] ([Intel XE#8374]) +1 other test skip
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-ptl-8/igt@xe_exec_fault_mode@once-multi-queue-rebind-imm.html
- shard-lnl: NOTRUN -> [SKIP][73] ([Intel XE#8374]) +3 other tests skip
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-4/igt@xe_exec_fault_mode@once-multi-queue-rebind-imm.html
* igt@xe_exec_multi_queue@many-execs-dyn-priority-smem:
- shard-bmg: NOTRUN -> [SKIP][74] ([Intel XE#8364])
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-bmg-5/igt@xe_exec_multi_queue@many-execs-dyn-priority-smem.html
* igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-close-fd-smem:
- shard-lnl: NOTRUN -> [SKIP][75] ([Intel XE#8364]) +9 other tests skip
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-7/igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-close-fd-smem.html
* igt@xe_exec_multi_queue@many-execs-priority-smem:
- shard-ptl: NOTRUN -> [SKIP][76] ([Intel XE#8364]) +1 other test skip
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-ptl-8/igt@xe_exec_multi_queue@many-execs-priority-smem.html
* igt@xe_exec_reset@multi-queue-cancel:
- shard-lnl: NOTRUN -> [SKIP][77] ([Intel XE#8369]) +1 other test skip
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-7/igt@xe_exec_reset@multi-queue-cancel.html
* igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-userptr:
- shard-lnl: NOTRUN -> [SKIP][78] ([Intel XE#8378]) +1 other test skip
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-7/igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-userptr.html
* igt@xe_gt_freq@freq_suspend:
- shard-ptl: NOTRUN -> [SKIP][79] ([Intel XE#7070])
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-ptl-8/igt@xe_gt_freq@freq_suspend.html
- shard-lnl: NOTRUN -> [SKIP][80] ([Intel XE#584] / [Intel XE#7369])
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-4/igt@xe_gt_freq@freq_suspend.html
* igt@xe_page_reclaim@binds-1g-partial:
- shard-lnl: NOTRUN -> [SKIP][81] ([Intel XE#7793])
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-7/igt@xe_page_reclaim@binds-1g-partial.html
* igt@xe_pm@s4-mocs:
- shard-ptl: [PASS][82] -> [ABORT][83] ([Intel XE#9362]) +1 other test abort
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6082-e96f23b42352b7b9fea6bf92bceed052533fb98e/shard-ptl-7/igt@xe_pm@s4-mocs.html
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-ptl-2/igt@xe_pm@s4-mocs.html
* igt@xe_pxp@pxp-termination-key-update-post-rpm:
- shard-bmg: NOTRUN -> [SKIP][84] ([Intel XE#4733] / [Intel XE#7417])
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-bmg-5/igt@xe_pxp@pxp-termination-key-update-post-rpm.html
* igt@xe_query@multigpu-query-invalid-cs-cycles:
- shard-lnl: NOTRUN -> [SKIP][85] ([Intel XE#944])
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-7/igt@xe_query@multigpu-query-invalid-cs-cycles.html
* igt@xe_sriov_flr@flr-vf1-clear:
- shard-lnl: NOTRUN -> [SKIP][86] ([Intel XE#3342])
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-7/igt@xe_sriov_flr@flr-vf1-clear.html
#### Possible fixes ####
* igt@kms_hdr@invalid-hdr:
- shard-bmg: [SKIP][87] ([Intel XE#1503]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6082-e96f23b42352b7b9fea6bf92bceed052533fb98e/shard-bmg-4/igt@kms_hdr@invalid-hdr.html
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-bmg-2/igt@kms_hdr@invalid-hdr.html
* igt@xe_pm@s4-basic-exec:
- shard-ptl: [ABORT][89] ([Intel XE#9362]) -> [PASS][90] +1 other test pass
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6082-e96f23b42352b7b9fea6bf92bceed052533fb98e/shard-ptl-2/igt@xe_pm@s4-basic-exec.html
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-ptl-8/igt@xe_pm@s4-basic-exec.html
- shard-lnl: [ABORT][91] ([Intel XE#9362]) -> [PASS][92] +1 other test pass
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6082-e96f23b42352b7b9fea6bf92bceed052533fb98e/shard-lnl-2/igt@xe_pm@s4-basic-exec.html
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-lnl-4/igt@xe_pm@s4-basic-exec.html
#### Warnings ####
* igt@kms_tiled_display@basic-test-pattern:
- shard-bmg: [SKIP][93] ([Intel XE#2426] / [Intel XE#5848]) -> [FAIL][94] ([Intel XE#1729] / [Intel XE#7424])
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6082-e96f23b42352b7b9fea6bf92bceed052533fb98e/shard-bmg-8/igt@kms_tiled_display@basic-test-pattern.html
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/shard-bmg-10/igt@kms_tiled_display@basic-test-pattern.html
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1128]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1128
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
[Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
[Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
[Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
[Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
[Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
[Intel XE#3342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3342
[Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
[Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
[Intel XE#3718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3718
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
[Intel XE#4227]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4227
[Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
[Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
[Intel XE#5764]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5764
[Intel XE#5800]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5800
[Intel XE#5808]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5808
[Intel XE#5812]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5812
[Intel XE#5821]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5821
[Intel XE#5824]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5824
[Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584
[Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
[Intel XE#5849]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5849
[Intel XE#5900]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5900
[Intel XE#5907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5907
[Intel XE#5962]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5962
[Intel XE#6011]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6011
[Intel XE#6078]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6078
[Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#6911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6911
[Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
[Intel XE#7070]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7070
[Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084
[Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
[Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
[Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
[Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
[Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
[Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
[Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
[Intel XE#7369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7369
[Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
[Intel XE#7376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7376
[Intel XE#7383]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7383
[Intel XE#7397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7397
[Intel XE#7413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7413
[Intel XE#7417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7417
[Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
[Intel XE#7466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7466
[Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
[Intel XE#7484]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7484
[Intel XE#7591]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7591
[Intel XE#7642]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7642
[Intel XE#7644]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7644
[Intel XE#7760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7760
[Intel XE#7793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7793
[Intel XE#7865]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7865
[Intel XE#7905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7905
[Intel XE#8150]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8150
[Intel XE#8151]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8151
[Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
[Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
[Intel XE#8369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8369
[Intel XE#8370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8370
[Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
[Intel XE#8378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8378
[Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
[Intel XE#9362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9362
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
[Intel XE#9463]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9463
Build changes
-------------
* Linux: xe-6082-e96f23b42352b7b9fea6bf92bceed052533fb98e -> xe-pw-178015v1
IGT_9181: 9181
xe-6082-e96f23b42352b7b9fea6bf92bceed052533fb98e: e96f23b42352b7b9fea6bf92bceed052533fb98e
xe-pw-178015v1: 178015v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-178015v1/index.html
[-- Attachment #2: Type: text/html, Size: 34213 bytes --]
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v6 1/2] drm/xe/xe_ras: Add support to retrieve info queue data
2026-11-06 18:59 ` [PATCH v6 1/2] drm/xe/xe_ras: Add support to retrieve " Badal Nilawar
@ 2026-11-10 10:53 ` Raag Jadav
0 siblings, 0 replies; 8+ messages in thread
From: Raag Jadav @ 2026-11-10 10:53 UTC (permalink / raw)
To: Badal Nilawar
Cc: intel-xe, anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio,
riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
himal.prasad.ghimiray, arvind.yadav, syed.abdul.muqthyar.ahmed,
nitin.r.gote, matthew.d.roper
On Sat, Nov 07, 2026 at 12:29:05AM +0530, Badal Nilawar wrote:
> Retrieve the RAS info queue data, in multiple chunks, and assemble it into
> a flat buffer.
>
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> ---
> v6:
> - Replace destination buffer checks with xe_assert() (Raag)
> - Extract get_first_chunk() and get_remaining_chunks() helpers (Raag)
> ---
> drivers/gpu/drm/xe/xe_ras.c | 140 ++++++++++++++++++
> drivers/gpu/drm/xe/xe_ras.h | 4 +-
> drivers/gpu/drm/xe/xe_ras_types.h | 91 +++++++++++-
> drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h | 2 +
> 4 files changed, 234 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index 2c01c183d02b..7f218ab2bd1b 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -1106,6 +1106,146 @@ int xe_ras_set_threshold(struct xe_device *xe, u8 severity, u8 component, u32 th
> return 0;
> }
>
> +static int get_info_queue(struct xe_device *xe,
> + struct xe_ras_get_info_queue_request *request,
> + struct xe_ras_get_info_queue_response *response)
> +{
> + struct xe_sysctrl_mailbox_command command = {0};
> + const struct xe_ras_info_queue_header *hdr;
> + size_t rlen;
> + int ret;
> +
> + xe_sysctrl_create_command(&command, XE_SYSCTRL_GROUP_GFSP, XE_SYSCTRL_CMD_GET_INFO_QUEUE,
> + request, sizeof(*request), response, sizeof(*response));
> +
> + ret = xe_sysctrl_send_command(&xe->sc, &command, &rlen);
> + if (ret) {
> + xe_err(xe, "sysctrl: failed to get info queue %d\n", ret);
> + return ret;
> + }
> +
> + if (rlen != sizeof(*response)) {
> + xe_err(xe, "sysctrl: unexpected get info queue response length %zu (expected %zu)\n",
> + rlen, sizeof(*response));
> + return -EIO;
> + }
> +
> + ret = ras_status_to_errno(response->status);
> + if (ret) {
> + xe_err(xe, "sysctrl: get info queue command failed with status %#x\n",
> + response->status);
> + return ret;
> + }
> +
> + hdr = &response->queue_response.header;
> + xe_dbg(xe, "[RAS] info queue: total_size=%u chunk_offset=%u chunk_size=%u flags=0x%x num_headers=%u\n",
"[RAS] get info queue". Also, "flags=%#x".
> + hdr->total_size, hdr->chunk_offset, hdr->chunk_size,
> + hdr->flags, hdr->num_headers);
Can be less lines?
> + return 0;
> +}
> +
> +static bool chunk_is_valid(const struct xe_ras_info_queue_header *hdr,
> + u32 expected_offset, u32 dest_size)
> +{
> + u32 end;
> +
> + return hdr->chunk_offset == expected_offset &&
> + hdr->chunk_size && hdr->chunk_size <= XE_RAS_INFO_QUEUE_MAX_CHUNK_SIZE &&
Should we also check hdr->total_size <= XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE?
> + !check_add_overflow(hdr->chunk_offset, hdr->chunk_size, &end) &&
> + end <= XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE && end <= dest_size;
With above in place, you can replace XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE
with hdr->total_size.
> +}
> +
> +static u32 get_first_chunk(struct xe_device *xe,
> + const struct xe_ras_get_counter_response *response,
'counter_resp'
> + u8 *dest_buf, u32 dest_size, u32 *flags)
> +{
> + const struct xe_ras_info_queue_header *hdr = &response->first.header;
> +
> + if (!chunk_is_valid(hdr, 0, dest_size)) {
> + xe_warn(xe, "[RAS]: invalid first info queue chunk (offset=%u size=%u, expected offset=%u)\n",
With hdr->total_size check above, we'd probably also need to log
total_size here. Use the same ordering as get_info_queue() log,
i.e. "total=%u offset=%u size=%u, ..."
> + hdr->chunk_offset, hdr->chunk_size, 0);
> + return 0;
> + }
> +
> + memcpy(dest_buf, response->first.data, hdr->chunk_size);
> + *flags = hdr->flags;
> +
> + return hdr->chunk_size;
> +}
> +
> +static u32 get_remaining_chunks(struct xe_device *xe,
> + const struct xe_ras_get_counter_response *response,
'counter_resp'
> + u8 *dest_buf, u32 dest_size, u32 offset, u32 flags)
> +{
> + int ret;
> +
> + while ((flags & XE_RAS_INFO_QUEUE_FLAG_MORE_DATA) && offset < dest_size) {
This fails silently on offset > dest_size, so let chunk_is_valid()
take care of this.
> + struct xe_ras_get_info_queue_request request = {};
> + struct xe_ras_get_info_queue_response queue_response = {};
'response'
> + struct xe_ras_info_queue_header *hdr;
> +
> + request.queue_request.offset = offset;
> + request.queue_request.size = min(XE_RAS_INFO_QUEUE_MAX_CHUNK_SIZE,
> + dest_size - offset);
> + request.queue_request.session_id = response->counter;
Use a local qdata_request pointer, this'll help remove the wrapping.
> + ret = get_info_queue(xe, &request, &queue_response);
> + if (ret) {
> + xe_err(xe, "[RAS]: info queue drain aborted: fetch at offset=%u, ret = %d\n",
> + offset, ret);
> + return offset;
> + }
> +
> + hdr = &queue_response.queue_response.header;
> +
> + if (!chunk_is_valid(hdr, offset, dest_size)) {
> + xe_warn(xe, "[RAS]: invalid info queue chunk (offset=%u size=%u, expected offset=%u)\n",
Same as above, also log total_size here.
> + hdr->chunk_offset, hdr->chunk_size, offset);
> + return offset;
> + }
History has been evidence that we shouldn't blindly trust the firmware,
especially inside a loop. We've introduce XE_SYSCTRL_FLOOD_LIMIT for
this reason, which looks like also should be used here.
> + memcpy(dest_buf + offset, queue_response.queue_response.data, hdr->chunk_size);
> + offset += hdr->chunk_size;
> + flags = hdr->flags;
> + }
> +
> + return min(offset, response->first.header.total_size);
> +}
> +
> +/**
> + * xe_ras_drain_info_queue() - Drain the full RAS info queue into a flat buffer
> + * @xe: xe device
> + * @response: counter response carrying the first embedded chunk
> + * @dest_buf: destination buffer supplied by the caller
> + * @dest_size: size of @dest_buf in bytes; also caps the total amount of data
> + * assembled from the info queue
Not sure if I follow, is the capping done here or is it caller responsibility?
> + * Copies the first chunk already embedded in @response, then loops
> + * issuing GET_INFO_QUEUE to fetch any remaining chunks until the queue
> + * signals no more data or a transport/bounds error is encountered. On
> + * transport or bounds errors the function stops and returns whatever has
> + * been assembled so far.
> + *
> + * Returns: Number of valid bytes written into @dest_buf.
> + */
> +u32 xe_ras_drain_info_queue(struct xe_device *xe,
> + const struct xe_ras_get_counter_response *response,
> + u8 *dest_buf, u32 dest_size)
> +{
> + u32 flags, offset;
> +
> + xe_assert(xe, response->has_info_queue);
I think this can be explicit if() condition, so the caller doesn't
need to worry about this.
> + xe_assert(xe, dest_buf);
> + xe_assert(xe, dest_size);
> +
> + offset = get_first_chunk(xe, response, dest_buf, dest_size, &flags);
> + if (!offset)
> + return 0;
> +
> + return get_remaining_chunks(xe, response, dest_buf, dest_size, offset, flags);
> +}
> +
> static ssize_t gpu_health_show(struct device *dev, struct device_attribute *attr, char *buf)
> {
> struct xe_ras_get_health_response response = {0};
> diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h
> index c44fa172011f..5bdac147098f 100644
> --- a/drivers/gpu/drm/xe/xe_ras.h
> +++ b/drivers/gpu/drm/xe/xe_ras.h
> @@ -25,5 +25,7 @@ bool xe_ras_get_disable_vram_page_offline(struct xe_device *xe);
> u32 xe_ras_get_max_pages(struct xe_device *xe);
> int xe_ras_get_counter_response(struct xe_device *xe, const struct xe_ras_error_class *counter,
> struct xe_ras_get_counter_response *response);
> -
> +u32 xe_ras_drain_info_queue(struct xe_device *xe,
> + const struct xe_ras_get_counter_response *response,
> + u8 *dest_buf, u32 dest_size);
> #endif
> diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
> index a86f9d2b8c92..67d57182aac9 100644
> --- a/drivers/gpu/drm/xe/xe_ras_types.h
> +++ b/drivers/gpu/drm/xe/xe_ras_types.h
> @@ -19,6 +19,10 @@
> #define XE_RAS_MEMORY_POISON BIT(2)
> #define XE_RAS_MEMORY_DATA_PARITY BIT(5)
>
> +#define XE_RAS_INFO_QUEUE_MAX_CHUNK_SIZE 200
> +#define XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE 5120
> +#define XE_RAS_INFO_QUEUE_FLAG_MORE_DATA 0x02
> +
> /**
> * enum xe_ras_page_action - Page offline actions for page offline request
> *
> @@ -110,6 +114,83 @@ struct xe_ras_threshold_crossed {
> struct xe_ras_error_class counters[XE_RAS_NUM_COUNTERS];
> } __packed;
>
> +/**
> + * struct xe_ras_info_queue_header - Metadata for large info queue data transfers
> + *
> + * Provides chunk metadata for commands that support extended info queue
> + * functionality. Used when the total data exceeds a single mailbox response.
> + */
> +struct xe_ras_info_queue_header {
> + /** @total_size: Total size of the complete info queue data in bytes */
> + u32 total_size;
> + /** @chunk_offset: Offset of this chunk within the total data in bytes */
> + u32 chunk_offset;
> + /** @chunk_size: Size of the data in this chunk in bytes */
> + u32 chunk_size;
> + /** @reserved0: Reserved for future use */
> + u32 reserved0;
> + /** @flags: Info queue control flags (XE_RAS_INFO_QUEUE_FLAG_*) */
> + u32 flags:8;
> + /** @reserved1: Reserved for future use */
> + u32 reserved1:4;
> + /** @num_headers: Number of detailed counter headers at start of the data */
> + u32 num_headers:5;
> + /** @reserved2: Reserved for future use */
> + u32 reserved2:15;
> + /** @reserved3: Reserved for future use */
> + u32 reserved3;
> +} __packed;
> +
> +/**
> + * struct xe_ras_info_queue_data_request - Request for a specific chunk of info queue data
> + *
> + * Allows the driver to request continuation of large info queue transfers
> + * by specifying an offset and size within the full data set.
> + */
> +struct xe_ras_info_queue_data_request {
> + /** @offset: Byte offset of the requested data chunk */
> + u32 offset;
> + /** @size: Maximum size of the requested chunk in bytes */
> + u32 size;
> + /** @session_id: Session ID to correlate multi-chunk transfers */
> + struct xe_ras_error_class session_id;
> + /** @reserved: Reserved for future use */
> + u32 reserved;
> +} __packed;
> +
> +/**
> + * struct xe_ras_info_queue_data_response - Generic response for commands with info queues
> + *
> + * Standard response format for any command that returns an info queue
> + * payload. May be embedded in a command-specific response structure.
> + */
> +struct xe_ras_info_queue_data_response {
> + /** @header: Info queue metadata for this chunk */
> + struct xe_ras_info_queue_header header;
> + /** @data: Info queue data for this chunk */
> + u8 data[XE_RAS_INFO_QUEUE_MAX_CHUNK_SIZE];
> +} __packed;
> +
> +/**
> + * struct xe_ras_get_info_queue_request - Request for XE_SYSCTRL_CMD_GET_INFO_QUEUE
> + */
> +struct xe_ras_get_info_queue_request {
> + /** @queue_request: Info queue request parameters */
> + struct xe_ras_info_queue_data_request queue_request;
'qdata_request'
> + /** @reserved: Reserved for future use */
> + u32 reserved[16];
> +} __packed;
> +
> +/**
> + * struct xe_ras_get_info_queue_response - Response for XE_SYSCTRL_CMD_GET_INFO_QUEUE
> + */
> +struct xe_ras_get_info_queue_response {
> + /** @status: Status of the retrieval operation */
> + u32 status;
> + /** @queue_response: Info queue data chunk */
> + struct xe_ras_info_queue_data_response queue_response;
'qdata_response'
Raag
> +} __packed;
> +
> /**
> * struct xe_ras_get_counter_request - Request structure for get counter
> */
> @@ -132,8 +213,14 @@ struct xe_ras_get_counter_response {
> u64 timestamp;
> /** @threshold: Threshold value for the counter */
> u32 threshold;
> - /** @reserved: Reserved */
> - u32 reserved[57];
> + /** @reserved: Reserved for future use */
> + u32 reserved:9;
> + /** @has_info_queue: Set if info queue is available */
> + u32 has_info_queue:1;
> + /** @reserved1: Reserved for future use */
> + u32 reserved1:22;
> + /** @first: First info queue chunk, if @has_info_queue is set */
> + struct xe_ras_info_queue_data_response first;
> } __packed;
>
> /**
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
> index cdacceebca06..50b1d9abaf1f 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
> +++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
> @@ -37,6 +37,7 @@ enum xe_sysctrl_group {
> * @XE_SYSCTRL_CMD_GET_OFFLINE_QUEUE: Retrieve list of offlined queued pages from firmware
> * @XE_SYSCTRL_CMD_GET_HEALTH: Retrieve gpu health
> * @XE_SYSCTRL_CMD_SET_HEALTH: Set gpu health
> + * @XE_SYSCTRL_CMD_GET_INFO_QUEUE: Retrieve a chunk of info queue data
> */
> enum xe_sysctrl_gfsp_cmd {
> XE_SYSCTRL_CMD_GET_SOC_ERROR = 0x01,
> @@ -50,6 +51,7 @@ enum xe_sysctrl_gfsp_cmd {
> XE_SYSCTRL_CMD_GET_OFFLINE_QUEUE = 0x0A,
> XE_SYSCTRL_CMD_GET_HEALTH = 0x0B,
> XE_SYSCTRL_CMD_SET_HEALTH = 0x0C,
> + XE_SYSCTRL_CMD_GET_INFO_QUEUE = 0x0D,
> };
>
> /**
> --
> 2.56.0
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v6 2/2] drm/xe/cper: Prepare Intel CPER info records
2026-11-06 18:59 ` [PATCH v6 2/2] drm/xe/cper: Prepare Intel CPER info records Badal Nilawar
@ 2026-11-11 10:36 ` Raag Jadav
0 siblings, 0 replies; 8+ messages in thread
From: Raag Jadav @ 2026-11-11 10:36 UTC (permalink / raw)
To: Badal Nilawar
Cc: intel-xe, anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio,
riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
himal.prasad.ghimiray, arvind.yadav, syed.abdul.muqthyar.ahmed,
nitin.r.gote, matthew.d.roper
On Sat, Nov 07, 2026 at 12:29:06AM +0530, Badal Nilawar wrote:
> The RAS info queue contains error logs for detail counters, or dynamic
> counter headers followed by error logs for aggregate counters.
>
> Build CPER info records from the queue data, converting each error log
> into an CPER event. For aggregate counters, group logs by their dynamic
> counter header and build one info record per header.
>
> Emit a CPER record for each generated info record.
>
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> ---
> v6:
> - Reintroduce event_ prefixes
> - %s/einfo/info/
> - Split cper_prepare_einfo() into queue-fetch and info-array construction helpers (Raag)
> - Rename the dynamic counter header's count field to error_count (Raag)
> ---
> drivers/gpu/drm/xe/xe_cper.c | 287 +++++++++++++++++++++++++++--
> drivers/gpu/drm/xe/xe_cper_types.h | 59 +++++-
> drivers/gpu/drm/xe/xe_ras_types.h | 26 +++
> 3 files changed, 357 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
> index bb90030bcd2d..9e2d4240200e 100644
> --- a/drivers/gpu/drm/xe/xe_cper.c
> +++ b/drivers/gpu/drm/xe/xe_cper.c
> @@ -89,7 +89,7 @@ static u64 cper_timestamp_now(void)
>
> static void cper_init_intel_hdr(struct xe_device *xe, const struct xe_ras_error_class *counter,
> u64 first_timestamp, u32 sig_id, u32 error_count,
> - struct xe_cper_intel_hdr *ihdr)
> + u32 info_size, struct xe_cper_intel_hdr *ihdr)
> {
> ihdr->counter = *counter;
> ihdr->validation_bits |= XE_CPER_VALID_LOCATION;
> @@ -106,6 +106,7 @@ static void cper_init_intel_hdr(struct xe_device *xe, const struct xe_ras_error_
> }
>
> ihdr->error_count = error_count;
> + ihdr->info_log_size = info_size;
>
> strscpy(ihdr->pci_bdf, pci_name(to_pci_dev(xe->drm.dev)), sizeof(ihdr->pci_bdf));
> ihdr->validation_bits |= XE_CPER_VALID_PCI_BDF;
> @@ -147,11 +148,11 @@ static void cper_init_record_hdr(struct xe_device *xe, u8 severity,
>
> static void cper_init_section_desc(struct xe_device *xe, u8 severity,
> struct cper_section_descriptor *sdesc,
> - u32 einfo_len)
> + u32 info_len)
> {
> sdesc->section_offset = sizeof(struct cper_record_header) +
> sizeof(struct cper_section_descriptor);
> - sdesc->section_length = sizeof(struct xe_cper_intel_hdr) + einfo_len;
> + sdesc->section_length = sizeof(struct xe_cper_intel_hdr) + info_len;
> sdesc->revision = CPER_SEC_REV;
> sdesc->validation_bits = 0;
> sdesc->section_type = INTEL_CPER_SECTION_ACCEL_GENERIC;
> @@ -166,14 +167,14 @@ static void cper_init_section_desc(struct xe_device *xe, u8 severity,
> static void cper_record_emit(struct xe_device *xe, u8 severity,
> const guid_t *notification_type,
> const struct xe_cper_intel_hdr *ihdr,
> - const void *einfo, u32 einfo_len)
> + const void *info, u32 info_len)
> {
> struct cper_section_descriptor *sdesc;
> struct xe_cper_nonstd_record *rec;
> struct cper_record_header *rhdr;
> u32 total_len;
>
> - total_len = sizeof(struct xe_cper_nonstd_record) + einfo_len;
> + total_len = sizeof(struct xe_cper_nonstd_record) + info_len;
> rec = kzalloc(total_len, GFP_KERNEL);
> if (!rec)
> return;
> @@ -185,14 +186,14 @@ static void cper_record_emit(struct xe_device *xe, u8 severity,
> cper_init_record_hdr(xe, severity, notification_type, rhdr, total_len);
>
> /* Assemble the section descriptor (UEFI Appendix N.2.2) */
> - cper_init_section_desc(xe, severity, sdesc, einfo_len);
> + cper_init_section_desc(xe, severity, sdesc, info_len);
>
> /* Copy the Intel-specific section header */
> rec->intel_hdr = *ihdr;
>
> /* Append optional variable-length error info */
> - if (einfo && einfo_len)
> - memcpy((u8 *)rec + sizeof(*rec), einfo, einfo_len);
> + if (info && info_len)
> + memcpy((u8 *)rec + sizeof(*rec), info, info_len);
Note, my 's/einfo/info' suggestion[1] was only for function and struct
names. So you can retain einfo as variable names and avoid all this churn.
Also use consistent naming in new code.
[1] https://lore.kernel.org/intel-xe/auhAl1p1PBAcEaLg@black.igk.intel.com/
> trace_xe_error_cper(xe, &rhdr->platform_id, &sdesc->fru_id, severity,
> &rec->intel_hdr, total_len, (u8 *)rec);
> @@ -200,6 +201,237 @@ static void cper_record_emit(struct xe_device *xe, u8 severity,
> kfree(rec);
> }
>
> +static struct xe_cper_intel_info *
> +build_info(const struct xe_ras_error_log *logs, u32 num_logs,
> + const struct xe_ras_error_class *counter, u32 error_count)
Make the parameter ordering consistent with other functions, i.e.
(counter, error_count, logs, num_logs)
> +{
> + struct xe_cper_intel_event *entry;
> + struct xe_cper_intel_info *info;
> + u32 queue_size, i;
> +
> + queue_size = num_logs * XE_CPER_RAS_LOG_ENTRY_SIZE;
'event_queue_size'
> + info = kzalloc_flex(*info, event_queue, queue_size);
> + if (!info)
> + return NULL;
> +
> + info->error_count = error_count;
> + info->event_queue_size = queue_size;
> + info->event_queue_count = num_logs;
> + info->counter = *counter;
Either align all the '=' or don't, but use consistent spacing.
> + entry = (struct xe_cper_intel_event *)info->event_queue;
> + for (i = 0; i < num_logs; i++) {
> + entry->size = sizeof_field(struct xe_ras_error_log, details);
> + entry->timestamp = logs[i].timestamp;
Ditto
> + memcpy(entry->metadata, logs[i].details, sizeof(logs[i].details));
> + entry = (void *)entry + XE_CPER_RAS_LOG_ENTRY_SIZE;
> + }
> +
> + return info;
> +}
> +
> +static void free_info_arr(struct xe_cper_info_entry *info_arr, u32 num_entries)
> +{
> + u32 i;
> +
> + for (i = 0; i < num_entries; i++)
> + kfree(info_arr[i].info);
> + kfree(info_arr);
> +}
> +
> +static bool fill_info_entry(struct xe_cper_info_entry *entry,
> + const struct xe_ras_error_class *counter, u32 error_count,
> + const struct xe_ras_error_log *logs, u32 num_logs)
> +{
> + entry->info = build_info(logs, num_logs, counter, error_count);
Since we're inside fill_info_entry(), perhaps this can be fill_info()?
> + if (!entry->info)
> + return false;
> +
> + entry->info_size = struct_size(entry->info, event_queue,
> + entry->info->event_queue_size);
> + /* The first log is the first occurrence of the error */
> + entry->timestamp = logs[0].timestamp;
> + entry->hdr.counter = *counter;
> + entry->hdr.error_count = error_count;
> + return true;
> +}
> +
> +static u32 build_detail_info(const struct xe_ras_error_class *counter,
'build_detailed_info()'
> + u32 error_count,
> + const struct xe_ras_error_log *logs, u32 num_logs,
> + struct xe_cper_info_entry *info_arr)
Can be less lines?
> +{
> + /* All logs belong to the queried class; the error count may exceed the logs kept */
> + if (!num_logs)
> + return 0;
> +
> + num_logs = min_t(u32, num_logs, XE_RAS_NUM_COUNTERS);
> +
> + return fill_info_entry(&info_arr[0], counter, error_count, logs, num_logs) ? 1 : 0;
> +}
> +
> +static u32 build_aggregate_info(struct xe_device *xe,
> + const struct xe_ras_info_queue_dynamic_counter_hdr *hdrs,
> + u32 num_hdrs, const struct xe_ras_error_log *logs,
> + u32 avail_logs, struct xe_cper_info_entry *info_arr)
> +{
> + u32 log_offset = 0, num_entries = 0, i;
> +
> + for (i = 0; i < num_hdrs; i++) {
> + u32 num_logs = min_t(u32, hdrs[i].error_count, XE_RAS_NUM_COUNTERS);
> +
> + if (num_logs > avail_logs - log_offset) {
> + xe_warn(xe, "CPER: header[%u] claims %u logs but only %u remain\n",
> + i, num_logs, avail_logs - log_offset);
> + break;
> + }
> +
> + if (!num_logs)
> + continue;
> +
> + if (!fill_info_entry(&info_arr[num_entries], &hdrs[i].counter,
> + hdrs[i].error_count, &logs[log_offset], num_logs))
> + break;
> +
> + log_offset += num_logs;
> + num_entries++;
> + }
> +
> + return num_entries;
> +}
> +
> +static u8 *cper_get_info_queue_buffer(struct xe_device *xe,
> + const struct xe_ras_get_counter_response *counter_resp,
> + u32 *raw_total)
> +{
> + const struct xe_ras_info_queue_header *first_qhdr = &counter_resp->first.header;
> + u32 buf_size;
> + u8 *raw_buf;
> +
> + if (!first_qhdr->total_size) {
> + xe_warn(xe, "CPER: info queue reports zero total size\n");
> + return NULL;
> + }
> +
> + if (first_qhdr->total_size > XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE)
> + xe_warn(xe, "CPER: info queue size %u exceeds max %u, truncating\n",
> + first_qhdr->total_size, XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE);
> +
> + buf_size = min(first_qhdr->total_size, XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE);
> + raw_buf = kzalloc_objs(*raw_buf, buf_size);
> + if (!raw_buf)
> + return NULL;
> +
> + *raw_total = xe_ras_drain_info_queue(xe, counter_resp, raw_buf, buf_size);
> + if (!*raw_total) {
> + kfree(raw_buf);
> + return NULL;
> + }
> +
> + return raw_buf;
> +}
> +
> +static struct xe_cper_info_entry *
> +cper_build_info_arr(struct xe_device *xe,
> + const struct xe_ras_get_counter_response *counter_resp,
> + const struct xe_ras_error_class *counter,
> + const u8 *raw_buf, u32 raw_total, u32 *num_entries)
> +{
> + const struct xe_ras_error_log *logs;
> + struct xe_cper_info_entry *info_arr;
> + u32 num_headers, headers_size, avail_logs;
> +
> + num_headers = counter_resp->first.header.num_headers;
> + headers_size = num_headers * sizeof(struct xe_ras_info_queue_dynamic_counter_hdr);
> + if (headers_size > raw_total) {
> + xe_warn(xe, "CPER: aggregate headers size (%u) exceeds raw total (%u)\n",
> + headers_size, raw_total);
> + return NULL;
> + }
> +
> + logs = (const struct xe_ras_error_log *)(raw_buf + headers_size);
> + avail_logs = (raw_total - headers_size) / sizeof(*logs);
> +
> + info_arr = kzalloc_objs(*info_arr, num_headers ?: 1);
> + if (!info_arr)
> + return NULL;
> +
> + if (num_headers)
> + *num_entries = build_aggregate_info(xe, (const void *)raw_buf,
> + num_headers, logs, avail_logs,
> + info_arr);
> + else
> + *num_entries = build_detail_info(counter, counter_resp->value,
> + logs, avail_logs, info_arr);
> +
> + if (!*num_entries) {
> + kfree(info_arr);
> + return NULL;
> + }
> +
> + return info_arr;
> +}
> +
> +/**
> + * cper_prepare_info() - Build the CPER error info records from RAS info queue data
> + * @xe: xe device instance
> + * @counter_resp: counter response containing the first embedded chunk
> + * @counter: RAS error class used for info record of details counter
> + * @num_entries: output number of entries in the returned array
> + *
> + * Assembles the complete raw info queue data from the first chunk already
> + * embedded in @counter_resp and any additional chunks fetched via
> + * GET_INFO_QUEUE. Two use cases are supported based on num_headers in
> + * the info queue header:
> + *
> + * Detail error counter (num_headers == 0)::
> + *
> + * [xe_ras_error_log * N]
> + *
> + * Returns one xe_cper_info_entry covering up to XE_RAS_NUM_COUNTERS logs.
> + *
> + * Aggregate error counter (num_headers > 0)::
> + *
> + * [xe_ras_info_queue_dynamic_counter_hdr * num_headers]
> + * [xe_ras_error_log * N]
> + *
> + * Returns one xe_cper_info_entry per header. Each header's @counter
> + * identifies its error class, and @error_count gives its error count. Up to
> + * XE_RAS_NUM_COUNTERS xe_ras_error_log entries are associated with each
> + * header. The header's counter populates the entry's info->counter.
> + *
> + * Returns: allocated xe_cper_info_entry array on success (caller must free it
> + * with free_info_arr()), NULL if no info queue is available or no
> + * error info could be built. @num_entries is set to the number of
> + * entries in the array, or zero when returning NULL.
> + */
> +static struct xe_cper_info_entry *
> +cper_prepare_info(struct xe_device *xe,
> + const struct xe_ras_get_counter_response *counter_resp,
> + const struct xe_ras_error_class *counter, u32 *num_entries)
> +{
> + struct xe_cper_info_entry *info_arr = NULL;
> + u32 raw_total;
> + u8 *raw_buf = NULL;
> +
> + *num_entries = 0;
Hm, see below[1].
> + if (!counter_resp->has_info_queue)
This looks like should be in xe_ras layer.
> + return NULL;
> +
> + raw_buf = cper_get_info_queue_buffer(xe, counter_resp, &raw_total);
> + if (!raw_buf)
> + goto out;
> +
> + info_arr = cper_build_info_arr(xe, counter_resp, counter, raw_buf,
Same as below[1], this'll cleanup a lot of ugly num_entries checks in
this call.
> + raw_total, num_entries);
> +out:
> + kfree(raw_buf);
> + if (!info_arr)
> + xe_warn(xe, "CPER: failed to build error info from info queue, emitting record without it\n");
> +
> + return info_arr;
> +}
> +
> /**
> * xe_cper_emit_counter() - Emit CPER records for an already fetched error counter
> * @xe: The &xe_device
> @@ -208,19 +440,48 @@ static void cper_record_emit(struct xe_device *xe, u8 severity,
> * @counter: RAS error class
> * @response: Counter response returned by firmware for @counter
> *
> - * Build and emit a CPER record from @response.
> + * Build and emit CPER records from @response, including any info queue data.
> + * Must be called from a sleepable context with a runtime PM reference held.
> */
> void xe_cper_emit_counter(struct xe_device *xe, int cper_sev, enum xe_sigid sigid,
> const struct xe_ras_error_class *counter,
> const struct xe_ras_get_counter_response *response)
I missed this in the previous series. The 'counter' argument is not
needed here, as you already got it as part of 'counter_resp'.
Please refactor this in a separate patch which is ordered before
this patch.
> {
> - struct xe_cper_intel_hdr ihdr = {};
> + struct xe_cper_info_entry *info_arr = NULL, *entries;
Redundant initialization.
> + struct xe_cper_info_entry single = {};
> + u32 num_entries = 0, count, i;
Ditto, see below[1].
> xe_assert(xe, is_hw_sigid(sigid));
>
> - cper_init_intel_hdr(xe, counter, response->timestamp,
> - sigid, response->value, &ihdr);
> - cper_record_emit(xe, cper_sev, &INTEL_CPER_NOTIFY_GPU_ERROR, &ihdr, NULL, 0);
> + /* Draining the info queue sends sysctrl commands */
> + might_sleep();
> + xe_device_assert_mem_access(xe);
> +
> + /* Without info queue data, emit a single record from the counter itself */
> + single.hdr.counter = *counter;
> + single.hdr.error_count = response->value;
> + single.timestamp = response->timestamp;
> + entries = &single;
> + count = 1;
> +
> + info_arr = cper_prepare_info(xe, response, counter, &num_entries);
Same as above, you already got a 'counter' as part of 'counter_resp'.
[1] Also, IMO the semantics here should be the other around, i.e. you
get num_entries as a return value and info_arr prepared as an argument
which should be used only if (num_entries).
Raag
> + if (info_arr) {
> + entries = info_arr;
> + count = num_entries;
> + }
> +
> + for (i = 0; i < count; i++) {
> + struct xe_cper_intel_hdr ihdr = {};
> +
> + cper_init_intel_hdr(xe, &entries[i].hdr.counter, entries[i].timestamp,
> + sigid, entries[i].hdr.error_count,
> + entries[i].info_size, &ihdr);
> +
> + cper_record_emit(xe, cper_sev, &INTEL_CPER_NOTIFY_GPU_ERROR, &ihdr,
> + entries[i].info, entries[i].info_size);
> + }
> +
> + free_info_arr(info_arr, num_entries);
> }
>
> static void cper_emit_hw_err(struct xe_device *xe, int cper_sev, enum xe_sigid sigid,
> diff --git a/drivers/gpu/drm/xe/xe_cper_types.h b/drivers/gpu/drm/xe/xe_cper_types.h
> index 68e30df0440e..2502a73bd3f9 100644
> --- a/drivers/gpu/drm/xe/xe_cper_types.h
> +++ b/drivers/gpu/drm/xe/xe_cper_types.h
> @@ -12,6 +12,11 @@
>
> #include "xe_ras_types.h"
>
> +/* Entries built from RAS error logs carry fixed-size details */
> +#define XE_CPER_RAS_LOG_ENTRY_SIZE \
> + (offsetof(struct xe_cper_intel_event, metadata) + \
> + sizeof_field(struct xe_ras_error_log, details))
> +
> /*
> * Validation bits definition for validation_bits in struct
> * xe_cper_intel_hdr. When set, corresponding fields in header
> @@ -67,14 +72,50 @@ struct xe_cper_intel_hdr {
> /** @drv_version: Driver source version string (THIS_MODULE->srcversion) */
> char drv_version[25];
> /** @reserved: Reserved for future use, must be zero */
> - u8 reserved[261];
> + u8 reserved[258];
> + /** @info_log_size: Size of xe_cper_intel_info */
> + u16 info_log_size;
> + /** @reserved1: Reserved for future use, must be zero */
> + u8 reserved1;
> +} __packed;
> +
> +/**
> + * struct xe_cper_intel_info - Variable-length Intel-specific CPER error information
> + *
> + * Contains the counter and event queue, and is appended after
> + * &xe_cper_intel_hdr when detailed error information is available.
> + */
> +struct xe_cper_intel_info {
> + /** @counter: Error class (severity, component, location, cause) */
> + struct xe_ras_error_class counter;
> + /** @error_count: Total number of errors recorded */
> + u32 error_count;
> + /** @event_queue_size: Total size of @event_queue in bytes */
> + u32 event_queue_size;
> + /** @event_queue_count: Number of events in @event_queue */
> + u32 event_queue_count;
> + /** @event_queue: Packed array of xe_cper_intel_event records */
> + u8 event_queue[];
> +} __packed;
> +
> +/**
> + * struct xe_cper_intel_event - Single error event in the CPER event queue
> + */
> +struct xe_cper_intel_event {
> + /** @size: Byte size of the @metadata payload */
> + u32 size;
> + /** @timestamp: &xe_ras_error_log::timestamp */
> + u64 timestamp;
> + /** @metadata: &xe_ras_error_log::details */
> + u8 metadata[];
> } __packed;
>
> /**
> * struct xe_cper_nonstd_record - Intel GPU CPER record
> *
> * Contains the standard CPER record header, section descriptor, and the
> - * Intel error section header.
> + * Intel section header. A &xe_cper_intel_info payload may be
> + * appended dynamically.
> */
> struct xe_cper_nonstd_record {
> /** @record_hdr: Standard CPER record header (UEFI Appendix N.2.1) */
> @@ -99,6 +140,20 @@ struct xe_device_guid_entry {
> guid_t guid;
> };
>
> +/**
> + * struct xe_cper_info_entry - One CPER info payload and its source counter
> + */
> +struct xe_cper_info_entry {
> + /** @hdr: Error class and error count used for the CPER section header */
> + struct xe_ras_info_queue_dynamic_counter_hdr hdr;
> + /** @info: Allocated info payload, NULL if none */
> + struct xe_cper_intel_info *info;
> + /** @info_size: Byte size of @info including the event queue */
> + u32 info_size;
> + /** @timestamp: Timestamp of the first occurrence of this error class */
> + u64 timestamp;
> +};
> +
> /**
> * struct xe_cper - Xe CPER state
> */
> diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
> index 67d57182aac9..cec6f8427973 100644
> --- a/drivers/gpu/drm/xe/xe_ras_types.h
> +++ b/drivers/gpu/drm/xe/xe_ras_types.h
> @@ -12,6 +12,7 @@
> #define XE_RAS_NUM_COUNTERS 16
> #define XE_RAS_NUM_ERROR_ARR 3
> #define XE_RAS_NUM_PAGES 25
> +#define XE_RAS_ERROR_DWORDS_MAX 16
> /* Error bits in IEH global error status register */
> #define XE_RAS_SOC_IEH_PUNIT BIT(1)
> /* Device memory error categories */
> @@ -171,6 +172,31 @@ struct xe_ras_info_queue_data_response {
> u8 data[XE_RAS_INFO_QUEUE_MAX_CHUNK_SIZE];
> } __packed;
>
> +/**
> + * struct xe_ras_info_queue_dynamic_counter_hdr - Aggregate counter header entry
> + *
> + * When a session requests aggregate counter data, one header per matching
> + * dynamic counter class is prepended to the queue data. The @counter field
> + * identifies the error class, and @error_count is its error count; at most
> + * XE_RAS_NUM_COUNTERS error log entries follow for it.
> + */
> +struct xe_ras_info_queue_dynamic_counter_hdr {
> + /** @counter: Error class associated with this counter group */
> + struct xe_ras_error_class counter;
> + /** @error_count: Error count of this class */
> + u32 error_count;
> +} __packed;
> +
> +/**
> + * struct xe_ras_error_log - Single error log entry following dynamic counter headers
> + */
> +struct xe_ras_error_log {
> + /** @timestamp: Timestamp when the error was recorded */
> + u64 timestamp;
> + /** @details: Error-specific details */
> + u32 details[XE_RAS_ERROR_DWORDS_MAX];
> +} __packed;
> +
> /**
> * struct xe_ras_get_info_queue_request - Request for XE_SYSCTRL_CMD_GET_INFO_QUEUE
> */
> --
> 2.56.0
>
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2026-11-11 10:36 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-11-06 18:59 [PATCH v6 0/2] Extend CPER records with RAS info queue data Badal Nilawar
2026-11-06 18:59 ` [PATCH v6 1/2] drm/xe/xe_ras: Add support to retrieve " Badal Nilawar
2026-11-10 10:53 ` Raag Jadav
2026-11-06 18:59 ` [PATCH v6 2/2] drm/xe/cper: Prepare Intel CPER info records Badal Nilawar
2026-11-11 10:36 ` Raag Jadav
2026-11-06 19:08 ` ✓ CI.KUnit: success for Extend CPER records with RAS info queue data Patchwork
2026-11-06 19:43 ` ✓ Xe.CI.BAT: " Patchwork
2026-11-07 23:49 ` ✓ Xe.CI.FULL: " Patchwork
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