Re: [PATCH v2 1/9] dt-bindings: i3c: Document generic bus timing properties

From: Frank Li <Frank.li@oss.nxp.com>
To: Billy Tsai <billy_tsai@aspeedtech.com>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>,
	Frank Li <Frank.Li@nxp.com>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>, Joel Stanley <joel@jms.id.au>,
	Andrew Jeffery <andrew@codeconstruct.com.au>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Miquel Raynal <miquel.raynal@bootlin.com>,
	Ryan Chen <ryan_chen@aspeedtech.com>,
	tbevis@amazon.com, linux-i3c@lists.infradead.org,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/9] dt-bindings: i3c: Document generic bus timing properties
Date: Wed, 11 Nov 2026 11:50:22 -0500	[thread overview]
Message-ID: <avSczhZGS9cCcNSu@lizhi-Precision-Tower-5810> (raw)
In-Reply-To: <20261111-b4-i3c-hci-ast2700-v2-1-4d8fff5c5196@aspeedtech.com>

On Wed, Nov 11, 2026 at 11:16:29AM +0800, Billy Tsai wrote:
> The push-pull and open-drain SCL periods, push-pull SDA output hold
> time, and the tCAS/tCBP periods around START and STOP conditions are
> normally derived from i3c-scl-hz, but board-level trace length,
> pull-up strength and capacitive loading can require different values
> than what that derivation produces for a given board.
>
> Document properties to override each of these independently, naming
> them after the MIPI I3C Basic Specification v1.1.1 timing parameters
> they adjust:
>
>  - i3c-pp-scl-high-period-ns, i3c-pp-scl-low-period-ns
>    tHIGH, tLOW: Table 87 (I3C Push-Pull Timing Parameters)
>
>  - i3c-od-scl-high-period-ns, i3c-od-scl-low-period-ns
>    tHIGH, tLOW_OD: Table 86 (I3C Open Drain Timing Parameters)
>
>  - i3c-pp-sda-hold-ns
>    tHD_PP: Table 87 (I3C Push-Pull Timing Parameters)
>
>  - i3c-cas-period-ns, i3c-cbp-period-ns
>    tCAS, tCBP: Table 86, Figures 144/145 (I3C Open Drain Timing
>    Parameters). These carry the protocol minima as constraints.
>
>  - i3c-sr-p-scl-low-period-ns
>    The SCL low period held while a Controller stalls the clock in
>    the T-Bit phase before a STOP or repeated START, per Section
>    5.1.2.5 "Controller Clock Stalling" (Figures 19 and 20). The
>    specification describes this requirement qualitatively and does
>    not assign it a dedicated timing symbol, unlike the other
>    properties above.
>
> Any property left out keeps the derived default.
>
> Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
> ---
>  Documentation/devicetree/bindings/i3c/i3c.yaml | 86 ++++++++++++++++++++++++++
>  1 file changed, 86 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/i3c/i3c.yaml b/Documentation/devicetree/bindings/i3c/i3c.yaml
> index 5603f2e7807d..30f65fd1afa7 100644
> --- a/Documentation/devicetree/bindings/i3c/i3c.yaml
> +++ b/Documentation/devicetree/bindings/i3c/i3c.yaml
> @@ -57,6 +57,82 @@ properties:
>
>        May not be supported by all controllers.
>
> +  i3c-pp-scl-high-period-ns:
> +    description: |

Needn't |

> +      Push-pull SCL high period override, in nanoseconds (tHIGH, MIPI
> +      I3C Basic Specification v1.1.1 Table 87). When undefined, the
> +      value is derived from i3c-scl-hz.
> +
> +      May not be supported by all controllers.

Add

    minimum:
    maximum:

to restrict validate rang.

> +
...
>      type: boolean
>      description: |
> @@ -67,6 +143,16 @@ required:
>    - "#address-cells"
>    - "#size-cells"
>
> +dependencies:
> +  i3c-pp-scl-high-period-ns:
> +    - i3c-pp-scl-low-period-ns
> +  i3c-pp-scl-low-period-ns:
> +    - i3c-pp-scl-high-period-ns
> +  i3c-od-scl-high-period-ns:
> +    - i3c-od-scl-low-period-ns
> +  i3c-od-scl-low-period-ns:
> +    - i3c-od-scl-high-period-ns
> +

why need these dependencies? Suppose it should be default value if not
existing.

Frank

>  patternProperties:
>    "@[0-9a-f]+$":
>      type: object
>
> --
> 2.34.1
>