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From: "Nuno Sá" <nuno.sa@analog.com>
To: Takahiro.Kuwano@infineon.com
Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org,
	pratyush@kernel.org, mwalle@kernel.org,
	miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com
Subject: Re: [PATCH v4] mtd: spi-nor: micron-st: Add support for is25wx01g
Date: Thu, 12 Nov 2026 09:29:43 +0000	[thread overview]
Message-ID: <avWFGvcOQEkKv3wA@nsa> (raw)
In-Reply-To: <f3510faf94ae4f878a96d4382dfd3d35@infineon.com>

On Thu, Nov 12, 2026 at 02:25:18AM +0000, Takahiro.Kuwano@infineon.com wrote:
> Hi,
> 
> > Add support for the ISSI IS25WX01G, a 1 Gbit (128 MiB) octal NOR flash.
> > The part is fully described by SFDP, so only the flash ID and small
> > post_bfpt and post_sfdp fixups are needed.
> > 
> > WRITE STATUS REGISTER (01h) takes a single data byte and only affects
> > status register bits 7:2, so the default 16-bit Write Status assumption
> > does not hold. Clear write_sr1_and_sr2 so that the single byte write_sr1
> > path is taken; write_sr1 is already set to 01h by the BFPT parsing.
> > 
> > The flash also has no Status Register 2. Configuration registers are read
> > with B5h/85h and written with B1h/81h, and the 35h Read Configuration
> > Register command does not exist, so clear read_sr2 as well.
> > 
> > Software write protection is done through the block protect bits in the
> > status register: BP0-BP2 at bits 4:2, BP3 at bit 6 and a Top/Bottom bit at
> > bit 5, which is exactly what SPI_NOR_HAS_LOCK, SPI_NOR_4BIT_BP,
> > SPI_NOR_BP3_SR_BIT6 and SPI_NOR_HAS_TB describe, so set those flags to get
> > the generic locking support.
> > 
> > The flash also supports 8D-8D-8D, but this could not be tested. Since the
> > SFDP has no SCCR map, the core would select 8D-8D-8D on a capable
> > controller but never switch the flash into it. Hence, drop the 8D-8D-8D
> > capabilities in a post_sfdp fixup for now.
> > 
> To fix missing SCCR map,
> 	.fixup_flags = SPI_NOR_IO_MODE_EN_VOLATILE
> is needed.

No sure I'm following... You mean that I could already set the flag
together with is25wx01g_post_sfdp_fixup()? I could do that but the only
advantage would less changes on a future patch enabling dtr.

> 
> Could you check if it works?

I can't test 8D-8D-8D for now... That is why I have the sfdp_fixup.
Please look at the comment in there where I do state we'll need to set
the SPI_NOR_IO_MODE_EN_VOLATILE for dtr to work.

- Nuno Sá

> 
> Thanks,
> Takahiro
> 

______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

WARNING: multiple messages have this Message-ID (diff)
From: "Nuno Sá" <nuno.sa@analog.com>
To: Takahiro.Kuwano@infineon.com
Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org,
	pratyush@kernel.org, mwalle@kernel.org,
	miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com
Subject: Re: [PATCH v4] mtd: spi-nor: micron-st: Add support for is25wx01g
Date: Thu, 12 Nov 2026 09:29:43 +0000	[thread overview]
Message-ID: <avWFGvcOQEkKv3wA@nsa> (raw)
In-Reply-To: <f3510faf94ae4f878a96d4382dfd3d35@infineon.com>

On Thu, Nov 12, 2026 at 02:25:18AM +0000, Takahiro.Kuwano@infineon.com wrote:
> Hi,
> 
> > Add support for the ISSI IS25WX01G, a 1 Gbit (128 MiB) octal NOR flash.
> > The part is fully described by SFDP, so only the flash ID and small
> > post_bfpt and post_sfdp fixups are needed.
> > 
> > WRITE STATUS REGISTER (01h) takes a single data byte and only affects
> > status register bits 7:2, so the default 16-bit Write Status assumption
> > does not hold. Clear write_sr1_and_sr2 so that the single byte write_sr1
> > path is taken; write_sr1 is already set to 01h by the BFPT parsing.
> > 
> > The flash also has no Status Register 2. Configuration registers are read
> > with B5h/85h and written with B1h/81h, and the 35h Read Configuration
> > Register command does not exist, so clear read_sr2 as well.
> > 
> > Software write protection is done through the block protect bits in the
> > status register: BP0-BP2 at bits 4:2, BP3 at bit 6 and a Top/Bottom bit at
> > bit 5, which is exactly what SPI_NOR_HAS_LOCK, SPI_NOR_4BIT_BP,
> > SPI_NOR_BP3_SR_BIT6 and SPI_NOR_HAS_TB describe, so set those flags to get
> > the generic locking support.
> > 
> > The flash also supports 8D-8D-8D, but this could not be tested. Since the
> > SFDP has no SCCR map, the core would select 8D-8D-8D on a capable
> > controller but never switch the flash into it. Hence, drop the 8D-8D-8D
> > capabilities in a post_sfdp fixup for now.
> > 
> To fix missing SCCR map,
> 	.fixup_flags = SPI_NOR_IO_MODE_EN_VOLATILE
> is needed.

No sure I'm following... You mean that I could already set the flag
together with is25wx01g_post_sfdp_fixup()? I could do that but the only
advantage would less changes on a future patch enabling dtr.

> 
> Could you check if it works?

I can't test 8D-8D-8D for now... That is why I have the sfdp_fixup.
Please look at the comment in there where I do state we'll need to set
the SPI_NOR_IO_MODE_EN_VOLATILE for dtr to work.

- Nuno Sá

> 
> Thanks,
> Takahiro
> 

  reply	other threads:[~2026-11-12  9:28 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-06 16:33 [PATCH v4] mtd: spi-nor: micron-st: Add support for is25wx01g Nuno Sá
2026-11-06 16:33 ` Nuno Sá
2026-11-12  2:25 ` Takahiro.Kuwano
2026-11-12  2:25   ` Takahiro.Kuwano
2026-11-12  9:29   ` Nuno Sá [this message]
2026-11-12  9:29     ` Nuno Sá

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