From: Sebastian Reichel <sebastian.reichel@collabora.com>
To: aiyengar1990@gmail.com
Cc: Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
"Joerg Roedel (AMD)" <joro@8bytes.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Heiko Stuebner <heiko@sntech.de>,
Niklas Cassel <cassel@kernel.org>,
Pranjal Shrivastava <praan@google.com>,
linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-rockchip@lists.infradead.org,
Shawn Lin <shawn.lin@rock-chips.com>,
Simon Xue <xxm@rock-chips.com>,
Finley Xiao <finley.xiao@rock-chips.com>
Subject: Re: [PATCH v2 4/4] arm64: dts: rockchip: Add the reset of the RK3588 PCIe SMMU
Date: Thu, 12 Nov 2026 17:33:16 +0100 [thread overview]
Message-ID: <avXqMZkpY7d0sbfR@venus> (raw)
In-Reply-To: <20261112-smmu-v3-pcie-pd-v2-4-3a77bbb6b2c4@gmail.com>
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Hi,
On Thu, Nov 12, 2026 at 08:20:25AM +0000, Arun Iyengar via B4 Relay wrote:
> From: Arun Iyengar <aiyengar1990@gmail.com>
>
> The MMU-600 for the PCIe controllers (mmu600_pcie) has a reset line in
> the CRU, SRST_A_MMU_PCIE, which its node does not describe. Add it, so
> that the node describes both the clock and the reset of the MMU-600.
>
> Signed-off-by: Arun Iyengar <aiyengar1990@gmail.com>
> ---
squash this into the previous commit.
-- Sebastian
> arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> index dfed34a8aa57..45c1bb335447 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> @@ -560,6 +560,7 @@ mmu600_pcie: iommu@fc900000 {
> <GIC_SPI 367 IRQ_TYPE_EDGE_RISING 0>;
> interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
> clocks = <&cru ACLK_MMU_PCIE>;
> + resets = <&cru SRST_A_MMU_PCIE>;
> #iommu-cells = <1>;
> };
>
>
> --
> 2.55.0
>
>
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WARNING: multiple messages have this Message-ID (diff)
From: Sebastian Reichel <sebastian.reichel@collabora.com>
To: aiyengar1990@gmail.com
Cc: Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
"Joerg Roedel (AMD)" <joro@8bytes.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Heiko Stuebner <heiko@sntech.de>,
Niklas Cassel <cassel@kernel.org>,
Pranjal Shrivastava <praan@google.com>,
linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-rockchip@lists.infradead.org,
Shawn Lin <shawn.lin@rock-chips.com>,
Simon Xue <xxm@rock-chips.com>,
Finley Xiao <finley.xiao@rock-chips.com>
Subject: Re: [PATCH v2 4/4] arm64: dts: rockchip: Add the reset of the RK3588 PCIe SMMU
Date: Thu, 12 Nov 2026 17:33:16 +0100 [thread overview]
Message-ID: <avXqMZkpY7d0sbfR@venus> (raw)
In-Reply-To: <20261112-smmu-v3-pcie-pd-v2-4-3a77bbb6b2c4@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 1150 bytes --]
Hi,
On Thu, Nov 12, 2026 at 08:20:25AM +0000, Arun Iyengar via B4 Relay wrote:
> From: Arun Iyengar <aiyengar1990@gmail.com>
>
> The MMU-600 for the PCIe controllers (mmu600_pcie) has a reset line in
> the CRU, SRST_A_MMU_PCIE, which its node does not describe. Add it, so
> that the node describes both the clock and the reset of the MMU-600.
>
> Signed-off-by: Arun Iyengar <aiyengar1990@gmail.com>
> ---
squash this into the previous commit.
-- Sebastian
> arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> index dfed34a8aa57..45c1bb335447 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> @@ -560,6 +560,7 @@ mmu600_pcie: iommu@fc900000 {
> <GIC_SPI 367 IRQ_TYPE_EDGE_RISING 0>;
> interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
> clocks = <&cru ACLK_MMU_PCIE>;
> + resets = <&cru SRST_A_MMU_PCIE>;
> #iommu-cells = <1>;
> };
>
>
> --
> 2.55.0
>
>
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next prev parent reply other threads:[~2026-11-12 16:33 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-12 8:20 [PATCH v2 0/4] iommu/arm-smmu-v3: Keep the clock of the RK3588 PCIe SMMU running Arun Iyengar
2026-11-12 8:20 ` Arun Iyengar via B4 Relay
2026-11-12 8:20 ` Arun Iyengar via B4 Relay
2026-11-12 8:20 ` [PATCH v2 1/4] dt-bindings: iommu: arm,smmu-v3: Allow a clock and a reset Arun Iyengar
2026-11-12 8:20 ` Arun Iyengar via B4 Relay
2026-11-12 8:20 ` Arun Iyengar via B4 Relay
2026-11-12 16:38 ` Sebastian Reichel
2026-11-12 16:38 ` Sebastian Reichel
2026-11-12 8:20 ` [PATCH v2 2/4] iommu/arm-smmu-v3: Enable an optional clock Arun Iyengar
2026-11-12 8:20 ` Arun Iyengar via B4 Relay
2026-11-12 8:20 ` Arun Iyengar via B4 Relay
2026-11-12 8:20 ` [PATCH v2 3/4] arm64: dts: rockchip: Add the clock of the RK3588 PCIe SMMU Arun Iyengar
2026-11-12 8:20 ` Arun Iyengar via B4 Relay
2026-11-12 8:20 ` Arun Iyengar via B4 Relay
2026-11-12 8:20 ` [PATCH v2 4/4] arm64: dts: rockchip: Add the reset " Arun Iyengar
2026-11-12 8:20 ` Arun Iyengar via B4 Relay
2026-11-12 8:20 ` Arun Iyengar via B4 Relay
2026-11-12 16:33 ` Sebastian Reichel [this message]
2026-11-12 16:33 ` Sebastian Reichel
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