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From: Frank Li <Frank.li@oss.nxp.com>
To: nathan.lynch@amd.com
Cc: Vinod Koul <vkoul@kernel.org>, Frank Li <Frank.Li@kernel.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	David Rientjes <rientjes@google.com>,
	John.Kariuki@amd.com, Jonathan Cameron <jic23@kernel.org>,
	Kinsey Ho <kinseyho@google.com>,
	Mario Limonciello <mario.limonciello@amd.com>,
	PradeepVineshReddy.Kodamati@amd.com,
	Shivank Garg <shivankg@amd.com>,
	Stephen Bates <Stephen.Bates@amd.com>,
	Tycho Andersen <tycho@kernel.org>, Wei Huang <wei.huang2@amd.com>,
	Wei Xu <weixugc@google.com>,
	dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-pci@vger.kernel.org
Subject: Re: [PATCH v4 06/25] dmaengine: sdxi: Configure context tables
Date: Thu, 12 Nov 2026 15:49:04 -0600	[thread overview]
Message-ID: <avYz3knsBmmFa7fs@SMW015318> (raw)
In-Reply-To: <20261103-sdxi-base-v4-6-3668ccc7aab8@amd.com>

On Tue, Nov 03, 2026 at 08:49:47PM -0600, Nathan Lynch via B4 Relay wrote:
> From: Nathan Lynch <nathan.lynch@amd.com>
>
> SDXI uses a two-level table hierarchy to track contexts. There is a
> single level 2 table per function which enumerates up to 512 level 1
> tables. Each level 1 table enumerates up to 128 contexts.
>
> Allocate and install the L2 table and a single L1 table, enough for
> context IDs 0-127 (i.e. the admin context with reserved id 0, plus 127
> client contexts). For now, to avoid dynamic management of additional
> L1 tables, cap ctl2.max_cxt to 127.
>
> Since the table allocations are devres-managed, there is no
> corresponding cleanup code required.
>
> Co-developed-by: Wei Huang <wei.huang2@amd.com>
> Signed-off-by: Wei Huang <wei.huang2@amd.com>
> Signed-off-by: Nathan Lynch <nathan.lynch@amd.com>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

>  drivers/dma/sdxi/device.c | 39 ++++++++++++++++++++++++++++++++++--
>  drivers/dma/sdxi/hw.h     | 50 +++++++++++++++++++++++++++++++++++++++++++++++
>  drivers/dma/sdxi/mmio.h   |  3 +++
>  drivers/dma/sdxi/sdxi.h   |  5 +++++
>  4 files changed, 95 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/dma/sdxi/device.c b/drivers/dma/sdxi/device.c
> index c03af5833414..baf55f6b6826 100644
> --- a/drivers/dma/sdxi/device.c
> +++ b/drivers/dma/sdxi/device.c
> @@ -13,11 +13,13 @@
>  #include <linux/iopoll.h>
>  #include <linux/jiffies.h>
>  #include <linux/limits.h>
> +#include <linux/log2.h>
>  #include <linux/minmax.h>
>  #include <linux/sizes.h>
>  #include <linux/slab.h>
>  #include <linux/time.h>
>
> +#include "hw.h"
>  #include "mmio.h"
>  #include "sdxi.h"
>
> @@ -284,7 +286,8 @@ static int sdxi_fn_prepare(struct sdxi_dev *sdxi)
>   */
>  static int sdxi_fn_activate(struct sdxi_dev *sdxi)
>  {
> -	u64 version, cap0, cap1, ctl2;
> +	u64 version, cap0, cap1, ctl2, cxt_l2, lv01_ptr;
> +	struct sdxi_cxt_L2_ent *L2_ent;
>
>  	version = sdxi_read64(sdxi, SDXI_MMIO_VERSION);
>  	dev_info(sdxi->dev, "SDXI %llu.%llu device found\n",
> @@ -301,7 +304,13 @@ static int sdxi_fn_activate(struct sdxi_dev *sdxi)
>  	sdxi->max_buffer = FIELD_GET(SDXI_MMIO_CAP1_MAX_BUFFER, cap1);
>  	dma_set_max_seg_size(sdxi->dev,
>  			     min((u64)SZ_2M << sdxi->max_buffer, U32_MAX));
> -	sdxi->max_cxtid = FIELD_GET(SDXI_MMIO_CAP1_MAX_CXT, cap1);
> +
> +	/*
> +	 * Constrain the number of client contexts supported by the
> +	 * driver to what fits in a single L1 table.
> +	 */
> +	sdxi->max_cxtid = min(SDXI_L1_TABLE_ENTRIES - 1,
> +			      FIELD_GET(SDXI_MMIO_CAP1_MAX_CXT, cap1));
>
>  	/* Apply our configuration. */
>  	ctl2 = FIELD_PREP(SDXI_MMIO_CTL2_MAX_CXT, sdxi->max_cxtid);
> @@ -313,6 +322,32 @@ static int sdxi_fn_activate(struct sdxi_dev *sdxi)
>  			   FIELD_GET(SDXI_MMIO_CAP1_OPB_000_CAP, cap1));
>  	sdxi_write64(sdxi, SDXI_MMIO_CTL2, ctl2);
>
> +	/* SDXI 1.0 4.1.8.2 Context Level 2 Table Setup */
> +	sdxi->L2_table = dmam_alloc_coherent(sdxi->dev,
> +					     sizeof(*sdxi->L2_table),
> +					     &sdxi->L2_dma, GFP_KERNEL);
> +	if (!sdxi->L2_table)
> +		return -ENOMEM;
> +
> +	cxt_l2 = FIELD_PREP(SDXI_MMIO_CXT_L2_PTR, sdxi->L2_dma >> ilog2(SZ_4K));
> +	sdxi_write64(sdxi, SDXI_MMIO_CXT_L2, cxt_l2);
> +
> +	/* SDXI 1.0 4.1.8.3 Context Level 1 Table Setup */
> +	sdxi->L1_table = dmam_alloc_coherent(sdxi->dev,
> +					     sizeof(*sdxi->L1_table),
> +					     &sdxi->L1_dma, GFP_KERNEL);
> +	if (!sdxi->L1_table)
> +		return -ENOMEM;
> +	/*
> +	 * SDXI 1.0 4.1.8.3.c: Initialize the Context level 2 table to
> +	 * point to the Context Level 1 [table].
> +	 */
> +	L2_ent = &sdxi->L2_table->entry[0];
> +	lv01_ptr = FIELD_PREP(SDXI_CXT_L2_ENT_VL, 1) |
> +		   FIELD_PREP(SDXI_CXT_L2_ENT_LV01_PTR,
> +			      sdxi->L1_dma >> ilog2(SZ_4K));
> +	L2_ent->lv01_ptr = cpu_to_le64(lv01_ptr);
> +
>  	return 0;
>  }
>
> diff --git a/drivers/dma/sdxi/hw.h b/drivers/dma/sdxi/hw.h
> new file mode 100644
> index 000000000000..0551c2b52980
> --- /dev/null
> +++ b/drivers/dma/sdxi/hw.h
> @@ -0,0 +1,50 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/* Copyright Advanced Micro Devices, Inc. */
> +
> +/*
> + * Hardware layouts and constants follow SDXI specification names and
> + * definition order. Reserved fields and bits must be zero unless specified
> + * otherwise.
> + */
> +
> +#ifndef DMA_SDXI_HW_H
> +#define DMA_SDXI_HW_H
> +
> +#include <linux/bits.h>
> +#include <linux/build_bug.h>
> +#include <linux/types.h>
> +#include <asm/byteorder.h>
> +
> +/* SDXI 1.0 Table 3-2: Context Level 2 Table Entry (CXT_L2_ENT) */
> +struct sdxi_cxt_L2_ent {
> +	__le64 lv01_ptr;
> +#define SDXI_CXT_L2_ENT_VL       BIT_ULL(0)
> +#define SDXI_CXT_L2_ENT_LV01_PTR GENMASK_ULL(63, 12)
> +} __packed __aligned(8);
> +static_assert(sizeof(struct sdxi_cxt_L2_ent) == 8);
> +
> +/* SDXI 1.0 3.2.1 Context Level 2 Table */
> +#define SDXI_L2_TABLE_ENTRIES 512
> +struct sdxi_cxt_L2_table {
> +	struct sdxi_cxt_L2_ent entry[SDXI_L2_TABLE_ENTRIES];
> +};
> +static_assert(sizeof(struct sdxi_cxt_L2_table) == 4096);
> +
> +/* SDXI 1.0 Table 3-3: Context Level 1 Table Entry (CXT_L1_ENT) */
> +struct sdxi_cxt_L1_ent {
> +	__le64 cxt_ctl_ptr;
> +	__le64 akey_ptr;
> +	__le32 misc0;
> +	__le32 opb_000_enb;
> +	__u8 rsvd_0[8];
> +} __packed __aligned(32);
> +static_assert(sizeof(struct sdxi_cxt_L1_ent) == 32);
> +
> +/* SDXI 1.0 3.2.2 Context Level 1 Table */
> +#define SDXI_L1_TABLE_ENTRIES 128
> +struct sdxi_cxt_L1_table {
> +	struct sdxi_cxt_L1_ent entry[SDXI_L1_TABLE_ENTRIES];
> +};
> +static_assert(sizeof(struct sdxi_cxt_L1_table) == 4096);
> +
> +#endif /* DMA_SDXI_HW_H */
> diff --git a/drivers/dma/sdxi/mmio.h b/drivers/dma/sdxi/mmio.h
> index 7c416de9f874..b040d2283fb2 100644
> --- a/drivers/dma/sdxi/mmio.h
> +++ b/drivers/dma/sdxi/mmio.h
> @@ -68,6 +68,9 @@ enum sdxi_reg {
>  #define SDXI_MMIO_VERSION_MINOR GENMASK_ULL(7, 0)
>  #define SDXI_MMIO_VERSION_MAJOR GENMASK_ULL(23, 16)
>
> +/* SDXI 1.0 Table 9-9: MMIO_CXT_L2 */
> +#define SDXI_MMIO_CXT_L2_PTR GENMASK_ULL(63, 12)
> +
>  /* SDXI 1.0 Table 9-10: MMIO_RKEY */
>  #define SDXI_MMIO_RKEY_EN BIT_ULL(0)
>
> diff --git a/drivers/dma/sdxi/sdxi.h b/drivers/dma/sdxi/sdxi.h
> index 7569b8395ce1..856a3838eec3 100644
> --- a/drivers/dma/sdxi/sdxi.h
> +++ b/drivers/dma/sdxi/sdxi.h
> @@ -44,6 +44,11 @@ struct sdxi_dev {
>  	u8 max_buffer;			/* Configured log2 buffer size minus 21. */
>  	u32 op_grp_cap;			/* supported operation group cap */
>
> +	struct sdxi_cxt_L2_table *L2_table;
> +	dma_addr_t L2_dma;
> +	struct sdxi_cxt_L1_table *L1_table;
> +	dma_addr_t L1_dma;
> +
>  	bool has_mailbox;
>
>  	const struct sdxi_bus_ops *bus_ops;
>
> --
> 2.56.0
>
>

  parent reply	other threads:[~2026-11-12 21:52 UTC|newest]

Thread overview: 91+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-04  2:49 [PATCH v4 00/25] dmaengine: Smart Data Accelerator Interface (SDXI) basic support Nathan Lynch
2026-11-04  2:49 ` Nathan Lynch via B4 Relay
2026-11-04  2:49 ` [PATCH v4 01/25] PCI: Add SNIA SDXI accelerator sub-class Nathan Lynch
2026-11-04  2:49   ` Nathan Lynch via B4 Relay
2026-11-04  2:55   ` sashiko-bot
2026-11-05 18:10   ` Frank Li
2026-11-05 18:25     ` Lynch, Nathan
2026-11-12 21:28   ` Bjorn Helgaas
2026-11-04  2:49 ` [PATCH v4 02/25] MAINTAINERS: Add entry for SDXI driver Nathan Lynch
2026-11-04  2:49   ` Nathan Lynch via B4 Relay
2026-11-12 21:19   ` Frank Li
2026-11-04  2:49 ` [PATCH v4 03/25] dmaengine: sdxi: Add PCI initialization Nathan Lynch
2026-11-04  2:49   ` Nathan Lynch via B4 Relay
2026-11-04  2:56   ` sashiko-bot
2026-11-05 17:59   ` Frank Li
2026-11-05 18:07     ` Lynch, Nathan
2026-11-04  2:49 ` [PATCH v4 04/25] dmaengine: sdxi: Prepare function and sanitize MMIO state Nathan Lynch
2026-11-04  2:49   ` Nathan Lynch via B4 Relay
2026-11-04  3:06   ` sashiko-bot
2026-11-12 21:26   ` Frank Li
2026-11-04  2:49 ` [PATCH v4 05/25] dmaengine: sdxi: Feature discovery and initial configuration Nathan Lynch
2026-11-04  2:49   ` Nathan Lynch via B4 Relay
2026-11-04  2:54   ` sashiko-bot
2026-11-12 21:32   ` Frank Li
2026-11-04  2:49 ` [PATCH v4 06/25] dmaengine: sdxi: Configure context tables Nathan Lynch
2026-11-04  2:49   ` Nathan Lynch via B4 Relay
2026-11-04  2:55   ` sashiko-bot
2026-11-12 21:49   ` Frank Li [this message]
2026-11-04  2:49 ` [PATCH v4 07/25] dmaengine: sdxi: Allocate context control DMA pool Nathan Lynch
2026-11-04  2:49   ` Nathan Lynch via B4 Relay
2026-11-04  2:54   ` sashiko-bot
2026-11-12 21:50   ` Frank Li
2026-11-04  2:49 ` [PATCH v4 08/25] dmaengine: sdxi: Introduce submission queue Nathan Lynch
2026-11-04  2:49   ` Nathan Lynch via B4 Relay
2026-11-04  2:56   ` sashiko-bot
2026-11-12 21:58   ` Frank Li
2026-11-04  2:49 ` [PATCH v4 09/25] dmaengine: sdxi: Allocate administrative context Nathan Lynch
2026-11-04  2:49   ` Nathan Lynch via B4 Relay
2026-11-04  2:56   ` sashiko-bot
2026-11-12 22:10   ` Frank Li
2026-11-04  2:49 ` [PATCH v4 10/25] dmaengine: sdxi: Install " Nathan Lynch
2026-11-04  2:49   ` Nathan Lynch via B4 Relay
2026-11-04  2:58   ` sashiko-bot
2026-11-12 22:17   ` Frank Li
2026-11-04  2:49 ` [PATCH v4 11/25] dmaengine: sdxi: Start functions on probe, stop on remove Nathan Lynch
2026-11-04  2:49   ` Nathan Lynch via B4 Relay
2026-11-04  3:04   ` sashiko-bot
2026-11-04  2:49 ` [PATCH v4 12/25] dmaengine: sdxi: Add client context allocation API Nathan Lynch
2026-11-04  2:49   ` Nathan Lynch via B4 Relay
2026-11-04  3:02   ` sashiko-bot
2026-11-04  2:49 ` [PATCH v4 13/25] dmaengine: sdxi: Add descriptor ring management Nathan Lynch
2026-11-04  2:49   ` Nathan Lynch via B4 Relay
2026-11-04  3:08   ` sashiko-bot
2026-11-04  2:49 ` [PATCH v4 14/25] dmaengine: sdxi: Add unit tests for descriptor ring reservations Nathan Lynch
2026-11-04  2:49   ` Nathan Lynch via B4 Relay
2026-11-04  3:02   ` sashiko-bot
2026-11-04  2:49 ` [PATCH v4 15/25] dmaengine: sdxi: Per-context access key (AKey) table entry allocator Nathan Lynch
2026-11-04  2:49   ` Nathan Lynch via B4 Relay
2026-11-04  2:59   ` sashiko-bot
2026-11-04  2:49 ` [PATCH v4 16/25] dmaengine: sdxi: Add completion status block API Nathan Lynch
2026-11-04  2:49   ` Nathan Lynch via B4 Relay
2026-11-04  2:59   ` sashiko-bot
2026-11-04  2:49 ` [PATCH v4 17/25] dmaengine: sdxi: Add unit tests for completion pool ownership Nathan Lynch
2026-11-04  2:49   ` Nathan Lynch via B4 Relay
2026-11-04  3:00   ` sashiko-bot
2026-11-04  2:49 ` [PATCH v4 18/25] dmaengine: sdxi: Add context submission helper Nathan Lynch
2026-11-04  2:49   ` Nathan Lynch via B4 Relay
2026-11-04  3:01   ` sashiko-bot
2026-11-04  2:50 ` [PATCH v4 19/25] dmaengine: sdxi: Encode context start, stop, update, and sync descriptors Nathan Lynch
2026-11-04  2:50   ` Nathan Lynch via B4 Relay
2026-11-04  3:01   ` sashiko-bot
2026-11-05 16:52   ` Tycho Andersen
2026-11-04  2:50 ` [PATCH v4 20/25] dmaengine: sdxi: Add client context release with update and sync Nathan Lynch
2026-11-04  2:50   ` Nathan Lynch via B4 Relay
2026-11-04  3:12   ` sashiko-bot
2026-11-04  2:50 ` [PATCH v4 21/25] dmaengine: sdxi: Provide context start and stop APIs Nathan Lynch
2026-11-04  2:50   ` Nathan Lynch via B4 Relay
2026-11-04  3:04   ` sashiko-bot
2026-11-04  2:50 ` [PATCH v4 22/25] dmaengine: sdxi: Encode copy and interrupt descriptors Nathan Lynch
2026-11-04  2:50   ` Nathan Lynch via B4 Relay
2026-11-04  3:07   ` sashiko-bot
2026-11-05 17:00   ` Tycho Andersen
2026-11-04  2:50 ` [PATCH v4 23/25] dmaengine: sdxi: Add unit tests for descriptor encoding Nathan Lynch
2026-11-04  2:50   ` Nathan Lynch via B4 Relay
2026-11-04  3:05   ` sashiko-bot
2026-11-04  2:50 ` [PATCH v4 24/25] dmaengine: sdxi: MSI/MSI-X vector allocation and mapping Nathan Lynch
2026-11-04  2:50   ` Nathan Lynch via B4 Relay
2026-11-04  3:15   ` sashiko-bot
2026-11-04  2:50 ` [PATCH v4 25/25] dmaengine: sdxi: Add DMA engine provider Nathan Lynch
2026-11-04  2:50   ` Nathan Lynch via B4 Relay
2026-11-04  3:24   ` sashiko-bot

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