* [PATCH v5 0/5] lx2160a: change the pad muxes through the RCW override
@ 2026-11-15 11:05 ` Vincent Jardin via B4 Relay
0 siblings, 0 replies; 14+ messages in thread
From: Vincent Jardin @ 2026-11-15 11:05 UTC (permalink / raw)
To: Dong Aisheng, Fabio Estevam, Frank Li, Jacky Bai,
Pengutronix Kernel Team, NXP S32 Linux Team, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Christophe Leroy (CS GROUP), Shawn Guo, Sascha Hauer
Cc: linux-gpio, devicetree, linux-kernel, linuxppc-dev,
linux-arm-kernel, imx, Vladimir Oltean, Ioana Ciornei,
Vincent Jardin
The LX2160A muxes its IIC, XSPI, SDHC, UART, IRQ and EVT pads from
fields of the RCW. They are read-only in RCWSR12..14 of DCFG, and are
changed at runtime through the override registers in the DCSR view of
DCFG, which read 0 until written.
Since commit 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c
gpio to support bus recovery"), fsl-lx216x.dtsi drives the override
registers with pinctrl-single for the I2C bus recovery. Its first pin
state clears every other field of the word: a board whose RCW programs
a non-zero pad mux loses those pads at the first I2C probe.
This series reads the fields in effect from RCWSR and writes RCWCR, as
fsl_guts_rcw_rmw() already does for the SerDes protocols:
- patches 1 and 2 describe the pad mux as a child of the DCFG node,
which gains its DCSR view
- patch 3 exports the RCW override of fsl-guts for the pad-mux fields
only
- patch 4 adds the pinctrl driver: one group per RCW field, one
function per encoding
- patch 5 moves the pad muxes of fsl-lx216x.dtsi under DCFG. Labels
and pin node names stay, so no board file changes, and the
pinctrl-single node goes
Patch 4 uses the exports of patch 3, so it cannot be applied alone:
patches 1 to 4 could be for the the pinctrl tree with an Ack of
the soc/fsl maintainer on patch 3,
and patch 5 through the i.MX tree once the driver is in,
since the I2C pin states of fsl-lx216x.dtsi then belong to it.
DTBs built before patch 5 keep their pinctrl-single node and behave as
before. There is no Fixes: tag, since patch 5 depends on a new driver.
I did not believe it should be backported then.
Tested on a Nodebox v3 (LX2160A) whose RCW muxes XSPI1_A_DATA[7:4],
SDHC1 and IIC5 are not set with the defaults, so I could confirm:
- with pinctrl-single the first I2C probe cleared those fields
- with this series RCWSR12..14 read after boot exactly what the RCW and
the board's pin states select
- all I2C controllers come up with their recovery states and a
forced bus recovery on IIC1 (multi-master enabled for the test)
changes only that field
Thanks to Vladimir Oltean for pointing at fsl_guts_rcw_rmw() when I
tried to prime the override registers from the RCW instead:
https://github.com/nxp-qoriq/rcw/pull/8
Signed-off-by: Vincent Jardin <vjardin@free.fr>
---
Changes in v5:
- soc: fsl: guts: the exports become fsl_guts_pmux_read(),
fsl_guts_pmux_override() and fsl_guts_pmux_override_supported(). guts
lists the pad-mux fields of the LX2160A and refuses any other field
or register, so the serdes fields cannot be changed (Vladimir Oltean)
- dt-bindings, pinctrl, dts: add the EC1, EC2, USB_EXT, GTX_CLK and
SDHC1_DS pad muxes of RCWSR27, the second reg of the node (Vladimir Oltean)
- Patch 3 is reworked: drop the review tags, new round of review is
needed (TBC, from Christophe Leroy and Frank Li)
- Patch 1 gets a reg, 5 groups and 4 functions:
same drop the the Reviewed-by of Rob Herring and Frank Li
- Patch 2: its description names RCWSR27 too, I assume the
Reviewed-by of Rob Herring can remain
- Link to v4: https://lore.kernel.org/r/20261114-for-upstream-lx2160a-rcw-pinmux-v1-v4-0-eefcea066a55@free.fr
Changes in v4:
- pinctrl: MAINTAINERS with imx@lists.linux.dev
FUNC and GROUP macros with LX2160A_PMUX_ prefix (Frank Li)
- Add the Reviewed and Ack tags of Rob Herring and Frank Li
- Patches 1, 2, 3 and 5 are not changed
- Link to v3: https://lore.kernel.org/r/20261108-for-upstream-lx2160a-rcw-pinmux-v1-v3-0-5a0063f1da9e@free.fr
Changes in v3:
- dt-bindings, dts: the pad-mux child is bus-addressed like the
clock-controller child of the LS1028A dcfg: its reg is the RCWSR12
to RCWSR14 window, under #address-cells, #size-cells and ranges on
the dcfg node, the override registers stay the DCSR view of the
parent (Krzysztof Kozlowski)
- cover letter: patch 4 cannot be applied without patch 3 (Linus Walleij)
- Patches 3 and 4 are unchanged
- Link to v2: https://lore.kernel.org/r/20261103-for-upstream-lx2160a-rcw-pinmux-v1-v2-0-3aad0860b984@free.fr
Changes in v2:
- dt-bindings: list, for each function, the groups, so the
schema refuses the associations the driver refuses (Frank Li)
- Patches 2 to 5 are unchanged
- Link to v1: https://lore.kernel.org/r/20261103-for-upstream-lx2160a-rcw-pinmux-v1-v1-0-0a61a9837744@free.fr
---
Vincent Jardin (5):
dt-bindings: pinctrl: add the NXP LX2160A RCW pad mux
dt-bindings: soc: fsl: layerscape-dcfg: add the LX2160A pad-mux child
soc: fsl: guts: add the RCW override of the pad muxes
pinctrl: freescale: add the LX2160A RCW pad-mux driver
arm64: dts: lx2160a: describe the pad muxes as the DCFG RCW override
.../bindings/pinctrl/fsl,lx2160a-rcw-pinmux.yaml | 309 ++++++++++++++++
.../bindings/soc/fsl/fsl,layerscape-dcfg.yaml | 18 +
MAINTAINERS | 8 +
arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi | 377 ++++++++++---------
drivers/pinctrl/freescale/Kconfig | 15 +
drivers/pinctrl/freescale/Makefile | 1 +
drivers/pinctrl/freescale/pinctrl-lx2160a.c | 401 +++++++++++++++++++++
drivers/soc/fsl/guts.c | 122 ++++++-
include/linux/fsl/guts.h | 3 +
9 files changed, 1078 insertions(+), 176 deletions(-)
---
base-commit: 6628e7d4c6b25c8d18f1345e3a20d21829aae7e4
change-id: 20261103-for-upstream-lx2160a-rcw-pinmux-v1-31f9ad97dc86
Best regards,
--
Vincent Jardin <vjardin@free.fr>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v5 0/5] lx2160a: change the pad muxes through the RCW override
@ 2026-11-15 11:05 ` Vincent Jardin via B4 Relay
0 siblings, 0 replies; 14+ messages in thread
From: Vincent Jardin via B4 Relay @ 2026-11-15 11:05 UTC (permalink / raw)
To: Dong Aisheng, Fabio Estevam, Frank Li, Jacky Bai,
Pengutronix Kernel Team, NXP S32 Linux Team, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Christophe Leroy (CS GROUP), Shawn Guo, Sascha Hauer
Cc: linux-gpio, devicetree, linux-kernel, linuxppc-dev,
linux-arm-kernel, imx, Vladimir Oltean, Ioana Ciornei,
Vincent Jardin
The LX2160A muxes its IIC, XSPI, SDHC, UART, IRQ and EVT pads from
fields of the RCW. They are read-only in RCWSR12..14 of DCFG, and are
changed at runtime through the override registers in the DCSR view of
DCFG, which read 0 until written.
Since commit 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c
gpio to support bus recovery"), fsl-lx216x.dtsi drives the override
registers with pinctrl-single for the I2C bus recovery. Its first pin
state clears every other field of the word: a board whose RCW programs
a non-zero pad mux loses those pads at the first I2C probe.
This series reads the fields in effect from RCWSR and writes RCWCR, as
fsl_guts_rcw_rmw() already does for the SerDes protocols:
- patches 1 and 2 describe the pad mux as a child of the DCFG node,
which gains its DCSR view
- patch 3 exports the RCW override of fsl-guts for the pad-mux fields
only
- patch 4 adds the pinctrl driver: one group per RCW field, one
function per encoding
- patch 5 moves the pad muxes of fsl-lx216x.dtsi under DCFG. Labels
and pin node names stay, so no board file changes, and the
pinctrl-single node goes
Patch 4 uses the exports of patch 3, so it cannot be applied alone:
patches 1 to 4 could be for the the pinctrl tree with an Ack of
the soc/fsl maintainer on patch 3,
and patch 5 through the i.MX tree once the driver is in,
since the I2C pin states of fsl-lx216x.dtsi then belong to it.
DTBs built before patch 5 keep their pinctrl-single node and behave as
before. There is no Fixes: tag, since patch 5 depends on a new driver.
I did not believe it should be backported then.
Tested on a Nodebox v3 (LX2160A) whose RCW muxes XSPI1_A_DATA[7:4],
SDHC1 and IIC5 are not set with the defaults, so I could confirm:
- with pinctrl-single the first I2C probe cleared those fields
- with this series RCWSR12..14 read after boot exactly what the RCW and
the board's pin states select
- all I2C controllers come up with their recovery states and a
forced bus recovery on IIC1 (multi-master enabled for the test)
changes only that field
Thanks to Vladimir Oltean for pointing at fsl_guts_rcw_rmw() when I
tried to prime the override registers from the RCW instead:
https://github.com/nxp-qoriq/rcw/pull/8
Signed-off-by: Vincent Jardin <vjardin@free.fr>
---
Changes in v5:
- soc: fsl: guts: the exports become fsl_guts_pmux_read(),
fsl_guts_pmux_override() and fsl_guts_pmux_override_supported(). guts
lists the pad-mux fields of the LX2160A and refuses any other field
or register, so the serdes fields cannot be changed (Vladimir Oltean)
- dt-bindings, pinctrl, dts: add the EC1, EC2, USB_EXT, GTX_CLK and
SDHC1_DS pad muxes of RCWSR27, the second reg of the node (Vladimir Oltean)
- Patch 3 is reworked: drop the review tags, new round of review is
needed (TBC, from Christophe Leroy and Frank Li)
- Patch 1 gets a reg, 5 groups and 4 functions:
same drop the the Reviewed-by of Rob Herring and Frank Li
- Patch 2: its description names RCWSR27 too, I assume the
Reviewed-by of Rob Herring can remain
- Link to v4: https://lore.kernel.org/r/20261114-for-upstream-lx2160a-rcw-pinmux-v1-v4-0-eefcea066a55@free.fr
Changes in v4:
- pinctrl: MAINTAINERS with imx@lists.linux.dev
FUNC and GROUP macros with LX2160A_PMUX_ prefix (Frank Li)
- Add the Reviewed and Ack tags of Rob Herring and Frank Li
- Patches 1, 2, 3 and 5 are not changed
- Link to v3: https://lore.kernel.org/r/20261108-for-upstream-lx2160a-rcw-pinmux-v1-v3-0-5a0063f1da9e@free.fr
Changes in v3:
- dt-bindings, dts: the pad-mux child is bus-addressed like the
clock-controller child of the LS1028A dcfg: its reg is the RCWSR12
to RCWSR14 window, under #address-cells, #size-cells and ranges on
the dcfg node, the override registers stay the DCSR view of the
parent (Krzysztof Kozlowski)
- cover letter: patch 4 cannot be applied without patch 3 (Linus Walleij)
- Patches 3 and 4 are unchanged
- Link to v2: https://lore.kernel.org/r/20261103-for-upstream-lx2160a-rcw-pinmux-v1-v2-0-3aad0860b984@free.fr
Changes in v2:
- dt-bindings: list, for each function, the groups, so the
schema refuses the associations the driver refuses (Frank Li)
- Patches 2 to 5 are unchanged
- Link to v1: https://lore.kernel.org/r/20261103-for-upstream-lx2160a-rcw-pinmux-v1-v1-0-0a61a9837744@free.fr
---
Vincent Jardin (5):
dt-bindings: pinctrl: add the NXP LX2160A RCW pad mux
dt-bindings: soc: fsl: layerscape-dcfg: add the LX2160A pad-mux child
soc: fsl: guts: add the RCW override of the pad muxes
pinctrl: freescale: add the LX2160A RCW pad-mux driver
arm64: dts: lx2160a: describe the pad muxes as the DCFG RCW override
.../bindings/pinctrl/fsl,lx2160a-rcw-pinmux.yaml | 309 ++++++++++++++++
.../bindings/soc/fsl/fsl,layerscape-dcfg.yaml | 18 +
MAINTAINERS | 8 +
arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi | 377 ++++++++++---------
drivers/pinctrl/freescale/Kconfig | 15 +
drivers/pinctrl/freescale/Makefile | 1 +
drivers/pinctrl/freescale/pinctrl-lx2160a.c | 401 +++++++++++++++++++++
drivers/soc/fsl/guts.c | 122 ++++++-
include/linux/fsl/guts.h | 3 +
9 files changed, 1078 insertions(+), 176 deletions(-)
---
base-commit: 6628e7d4c6b25c8d18f1345e3a20d21829aae7e4
change-id: 20261103-for-upstream-lx2160a-rcw-pinmux-v1-31f9ad97dc86
Best regards,
--
Vincent Jardin <vjardin@free.fr>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v5 1/5] dt-bindings: pinctrl: add the NXP LX2160A RCW pad mux
2026-11-15 11:05 ` Vincent Jardin via B4 Relay
@ 2026-11-15 11:05 ` Vincent Jardin via B4 Relay
-1 siblings, 0 replies; 14+ messages in thread
From: Vincent Jardin @ 2026-11-15 11:05 UTC (permalink / raw)
To: Dong Aisheng, Fabio Estevam, Frank Li, Jacky Bai,
Pengutronix Kernel Team, NXP S32 Linux Team, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Christophe Leroy (CS GROUP), Shawn Guo, Sascha Hauer
Cc: linux-gpio, devicetree, linux-kernel, linuxppc-dev,
linux-arm-kernel, imx, Vladimir Oltean, Ioana Ciornei,
Vincent Jardin
The LX2160A muxes its IIC, XSPI, SDHC, UART, IRQ, EVT, EC and USB pads
from fields of the RCW: read-only in RCWSR12..14 and RCWSR27 of DCFG,
changed at runtime through the override registers of its DCSR view.
Describe the pad mux as a child of DCFG at its RCWSR12 to RCWSR14 and
RCWSR27 windows: the override registers are at the same offsets of the
DCSR view of the parent. One group per RCW field, one function per
encoding.
Each function lists the groups that take it, so a pair the driver
would refuse, such as can on iic1, is refused by the schema.
Signed-off-by: Vincent Jardin <vjardin@free.fr>
---
.../bindings/pinctrl/fsl,lx2160a-rcw-pinmux.yaml | 309 +++++++++++++++++++++
1 file changed, 309 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,lx2160a-rcw-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,lx2160a-rcw-pinmux.yaml
new file mode 100644
index 000000000000..f835ebe332a9
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,lx2160a-rcw-pinmux.yaml
@@ -0,0 +1,309 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/fsl,lx2160a-rcw-pinmux.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP LX2160A RCW pad muxes
+
+maintainers:
+ - Vincent Jardin <vjardin@free.fr>
+
+description:
+ The LX2160A muxes its IIC, XSPI, SDHC, UART, IRQ, EVT, EC and USB pads based
+ on its RCW. The related fields are from the read-only RCWSR12 to RCWSR14 and
+ RCWSR27 registers of DCFG, and can be changed at runtime by writing the RCW
+ override registers in the DCSR view of DCFG. The node is a child of the DCFG
+ node, which owns both views. Its reg are the RCWSR12 to RCWSR14 and the
+ RCWSR27 windows of the CCSR view, and the override registers are at the same
+ offsets of the DCSR view.
+
+properties:
+ compatible:
+ const: fsl,lx2160a-rcw-pinmux
+
+ reg:
+ items:
+ - description: RCWSR12 to RCWSR14
+ - description: RCWSR27
+
+patternProperties:
+ '-pins$':
+ type: object
+ $ref: pinmux-node.yaml#
+ additionalProperties: false
+
+ properties:
+ function:
+ enum: [ asleep, can, evt, flexspi, flextimer, gpio, gtx-clk, i2c,
+ irq, reset-req, rgmii, sdhc, sdhc-clk, sdhc-data, sdhc-data4,
+ sdhc-spi, spi, tsec-1588, uart, uart3, uart4, usb ]
+
+ groups:
+ items:
+ enum: [ iic1, iic2, iic3, iic4, iic5, iic6, xspi1-data74,
+ xspi1-data30, xspi1-base, sdhc1-base, sdhc1-dir,
+ sdhc2-data74, sdhc2-base, uart1-soutsin, uart1-rtscts,
+ uart2-soutsin, uart2-rtscts, irq11-8, irq7-4, irq3-0,
+ evt4-3, evt2-0, clk-out, asleep, reset-req, ec1, ec2,
+ usb-ext, gtx-clk, sdhc1-ds ]
+
+ required:
+ - function
+ - groups
+
+ allOf:
+ - if:
+ properties:
+ function:
+ const: asleep
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ asleep ]
+
+ - if:
+ properties:
+ function:
+ const: can
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ iic3, iic4 ]
+
+ - if:
+ properties:
+ function:
+ const: evt
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ iic3, iic4, evt4-3, evt2-0, asleep ]
+
+ - if:
+ properties:
+ function:
+ const: flexspi
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ xspi1-data74, xspi1-data30, xspi1-base,
+ sdhc2-data74, sdhc2-base ]
+
+ - if:
+ properties:
+ function:
+ const: flextimer
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ iic2, irq7-4, irq3-0, evt4-3, evt2-0, clk-out ]
+
+ - if:
+ properties:
+ function:
+ const: gpio
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ iic2, iic3, iic4, iic5, iic6, xspi1-data74,
+ xspi1-data30, xspi1-base, sdhc1-base, sdhc1-dir,
+ sdhc2-data74, sdhc2-base, uart1-soutsin,
+ uart1-rtscts, uart2-soutsin, uart2-rtscts,
+ irq11-8, irq7-4, irq3-0, evt4-3, evt2-0, clk-out,
+ asleep, reset-req, iic1, ec1, ec2, usb-ext, gtx-clk,
+ sdhc1-ds ]
+
+ - if:
+ properties:
+ function:
+ const: gtx-clk
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ gtx-clk ]
+
+ - if:
+ properties:
+ function:
+ const: i2c
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ iic2, iic3, iic4, iic5, iic6, sdhc2-data74, iic1 ]
+
+ - if:
+ properties:
+ function:
+ const: irq
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ irq11-8, irq7-4, irq3-0 ]
+
+ - if:
+ properties:
+ function:
+ const: reset-req
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ reset-req ]
+
+ - if:
+ properties:
+ function:
+ const: rgmii
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ ec1, ec2 ]
+
+ - if:
+ properties:
+ function:
+ const: sdhc
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ iic2, sdhc1-base, sdhc1-dir, sdhc2-data74,
+ sdhc2-base, sdhc1-ds ]
+
+ - if:
+ properties:
+ function:
+ const: sdhc-clk
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ iic5, iic6 ]
+
+ - if:
+ properties:
+ function:
+ const: sdhc-data
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ sdhc1-dir ]
+
+ - if:
+ properties:
+ function:
+ const: sdhc-data4
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ sdhc1-base ]
+
+ - if:
+ properties:
+ function:
+ const: sdhc-spi
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ sdhc1-base ]
+
+ - if:
+ properties:
+ function:
+ const: spi
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ iic5, sdhc1-base, sdhc1-dir, sdhc2-base, sdhc1-ds ]
+
+ - if:
+ properties:
+ function:
+ const: tsec-1588
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ ec2 ]
+
+ - if:
+ properties:
+ function:
+ const: uart
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ uart1-soutsin, uart1-rtscts, uart2-soutsin,
+ uart2-rtscts ]
+
+ - if:
+ properties:
+ function:
+ const: uart3
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ uart1-rtscts ]
+
+ - if:
+ properties:
+ function:
+ const: uart4
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ uart2-rtscts ]
+
+ - if:
+ properties:
+ function:
+ const: usb
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ usb-ext ]
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - $ref: pinctrl.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ pinctrl@12c {
+ compatible = "fsl,lx2160a-rcw-pinmux";
+ reg = <0x12c 0xc>, <0x168 0x4>;
+
+ iic3-i2c-pins {
+ function = "i2c";
+ groups = "iic3";
+ };
+
+ iic3-gpio-pins {
+ function = "gpio";
+ groups = "iic3";
+ };
+ };
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v5 1/5] dt-bindings: pinctrl: add the NXP LX2160A RCW pad mux
@ 2026-11-15 11:05 ` Vincent Jardin via B4 Relay
0 siblings, 0 replies; 14+ messages in thread
From: Vincent Jardin via B4 Relay @ 2026-11-15 11:05 UTC (permalink / raw)
To: Dong Aisheng, Fabio Estevam, Frank Li, Jacky Bai,
Pengutronix Kernel Team, NXP S32 Linux Team, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Christophe Leroy (CS GROUP), Shawn Guo, Sascha Hauer
Cc: linux-gpio, devicetree, linux-kernel, linuxppc-dev,
linux-arm-kernel, imx, Vladimir Oltean, Ioana Ciornei,
Vincent Jardin
From: Vincent Jardin <vjardin@free.fr>
The LX2160A muxes its IIC, XSPI, SDHC, UART, IRQ, EVT, EC and USB pads
from fields of the RCW: read-only in RCWSR12..14 and RCWSR27 of DCFG,
changed at runtime through the override registers of its DCSR view.
Describe the pad mux as a child of DCFG at its RCWSR12 to RCWSR14 and
RCWSR27 windows: the override registers are at the same offsets of the
DCSR view of the parent. One group per RCW field, one function per
encoding.
Each function lists the groups that take it, so a pair the driver
would refuse, such as can on iic1, is refused by the schema.
Signed-off-by: Vincent Jardin <vjardin@free.fr>
---
.../bindings/pinctrl/fsl,lx2160a-rcw-pinmux.yaml | 309 +++++++++++++++++++++
1 file changed, 309 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,lx2160a-rcw-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,lx2160a-rcw-pinmux.yaml
new file mode 100644
index 000000000000..f835ebe332a9
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,lx2160a-rcw-pinmux.yaml
@@ -0,0 +1,309 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/fsl,lx2160a-rcw-pinmux.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP LX2160A RCW pad muxes
+
+maintainers:
+ - Vincent Jardin <vjardin@free.fr>
+
+description:
+ The LX2160A muxes its IIC, XSPI, SDHC, UART, IRQ, EVT, EC and USB pads based
+ on its RCW. The related fields are from the read-only RCWSR12 to RCWSR14 and
+ RCWSR27 registers of DCFG, and can be changed at runtime by writing the RCW
+ override registers in the DCSR view of DCFG. The node is a child of the DCFG
+ node, which owns both views. Its reg are the RCWSR12 to RCWSR14 and the
+ RCWSR27 windows of the CCSR view, and the override registers are at the same
+ offsets of the DCSR view.
+
+properties:
+ compatible:
+ const: fsl,lx2160a-rcw-pinmux
+
+ reg:
+ items:
+ - description: RCWSR12 to RCWSR14
+ - description: RCWSR27
+
+patternProperties:
+ '-pins$':
+ type: object
+ $ref: pinmux-node.yaml#
+ additionalProperties: false
+
+ properties:
+ function:
+ enum: [ asleep, can, evt, flexspi, flextimer, gpio, gtx-clk, i2c,
+ irq, reset-req, rgmii, sdhc, sdhc-clk, sdhc-data, sdhc-data4,
+ sdhc-spi, spi, tsec-1588, uart, uart3, uart4, usb ]
+
+ groups:
+ items:
+ enum: [ iic1, iic2, iic3, iic4, iic5, iic6, xspi1-data74,
+ xspi1-data30, xspi1-base, sdhc1-base, sdhc1-dir,
+ sdhc2-data74, sdhc2-base, uart1-soutsin, uart1-rtscts,
+ uart2-soutsin, uart2-rtscts, irq11-8, irq7-4, irq3-0,
+ evt4-3, evt2-0, clk-out, asleep, reset-req, ec1, ec2,
+ usb-ext, gtx-clk, sdhc1-ds ]
+
+ required:
+ - function
+ - groups
+
+ allOf:
+ - if:
+ properties:
+ function:
+ const: asleep
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ asleep ]
+
+ - if:
+ properties:
+ function:
+ const: can
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ iic3, iic4 ]
+
+ - if:
+ properties:
+ function:
+ const: evt
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ iic3, iic4, evt4-3, evt2-0, asleep ]
+
+ - if:
+ properties:
+ function:
+ const: flexspi
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ xspi1-data74, xspi1-data30, xspi1-base,
+ sdhc2-data74, sdhc2-base ]
+
+ - if:
+ properties:
+ function:
+ const: flextimer
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ iic2, irq7-4, irq3-0, evt4-3, evt2-0, clk-out ]
+
+ - if:
+ properties:
+ function:
+ const: gpio
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ iic2, iic3, iic4, iic5, iic6, xspi1-data74,
+ xspi1-data30, xspi1-base, sdhc1-base, sdhc1-dir,
+ sdhc2-data74, sdhc2-base, uart1-soutsin,
+ uart1-rtscts, uart2-soutsin, uart2-rtscts,
+ irq11-8, irq7-4, irq3-0, evt4-3, evt2-0, clk-out,
+ asleep, reset-req, iic1, ec1, ec2, usb-ext, gtx-clk,
+ sdhc1-ds ]
+
+ - if:
+ properties:
+ function:
+ const: gtx-clk
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ gtx-clk ]
+
+ - if:
+ properties:
+ function:
+ const: i2c
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ iic2, iic3, iic4, iic5, iic6, sdhc2-data74, iic1 ]
+
+ - if:
+ properties:
+ function:
+ const: irq
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ irq11-8, irq7-4, irq3-0 ]
+
+ - if:
+ properties:
+ function:
+ const: reset-req
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ reset-req ]
+
+ - if:
+ properties:
+ function:
+ const: rgmii
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ ec1, ec2 ]
+
+ - if:
+ properties:
+ function:
+ const: sdhc
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ iic2, sdhc1-base, sdhc1-dir, sdhc2-data74,
+ sdhc2-base, sdhc1-ds ]
+
+ - if:
+ properties:
+ function:
+ const: sdhc-clk
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ iic5, iic6 ]
+
+ - if:
+ properties:
+ function:
+ const: sdhc-data
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ sdhc1-dir ]
+
+ - if:
+ properties:
+ function:
+ const: sdhc-data4
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ sdhc1-base ]
+
+ - if:
+ properties:
+ function:
+ const: sdhc-spi
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ sdhc1-base ]
+
+ - if:
+ properties:
+ function:
+ const: spi
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ iic5, sdhc1-base, sdhc1-dir, sdhc2-base, sdhc1-ds ]
+
+ - if:
+ properties:
+ function:
+ const: tsec-1588
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ ec2 ]
+
+ - if:
+ properties:
+ function:
+ const: uart
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ uart1-soutsin, uart1-rtscts, uart2-soutsin,
+ uart2-rtscts ]
+
+ - if:
+ properties:
+ function:
+ const: uart3
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ uart1-rtscts ]
+
+ - if:
+ properties:
+ function:
+ const: uart4
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ uart2-rtscts ]
+
+ - if:
+ properties:
+ function:
+ const: usb
+ then:
+ properties:
+ groups:
+ items:
+ enum: [ usb-ext ]
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - $ref: pinctrl.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ pinctrl@12c {
+ compatible = "fsl,lx2160a-rcw-pinmux";
+ reg = <0x12c 0xc>, <0x168 0x4>;
+
+ iic3-i2c-pins {
+ function = "i2c";
+ groups = "iic3";
+ };
+
+ iic3-gpio-pins {
+ function = "gpio";
+ groups = "iic3";
+ };
+ };
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v5 2/5] dt-bindings: soc: fsl: layerscape-dcfg: add the LX2160A pad-mux child
2026-11-15 11:05 ` Vincent Jardin via B4 Relay
@ 2026-11-15 11:05 ` Vincent Jardin via B4 Relay
-1 siblings, 0 replies; 14+ messages in thread
From: Vincent Jardin @ 2026-11-15 11:05 UTC (permalink / raw)
To: Dong Aisheng, Fabio Estevam, Frank Li, Jacky Bai,
Pengutronix Kernel Team, NXP S32 Linux Team, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Christophe Leroy (CS GROUP), Shawn Guo, Sascha Hauer
Cc: linux-gpio, devicetree, linux-kernel, linuxppc-dev,
linux-arm-kernel, imx, Vladimir Oltean, Ioana Ciornei,
Vincent Jardin
On the LX2160A the DCFG node holds the pad mux, overridden through its
DCSR view. Allow fsl,lx2160a-dcfg with simple-mfd, so that the child is
populated, and the pinctrl child, on the LX2160A only.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Vincent Jardin <vjardin@free.fr>
---
.../bindings/soc/fsl/fsl,layerscape-dcfg.yaml | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-dcfg.yaml b/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-dcfg.yaml
index fc14fd0bf84b..bb9dbcfec188 100644
--- a/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-dcfg.yaml
+++ b/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-dcfg.yaml
@@ -32,6 +32,7 @@ properties:
- items:
- enum:
- fsl,ls1028a-dcfg
+ - fsl,lx2160a-dcfg
- const: syscon
- const: simple-mfd
@@ -66,10 +67,27 @@ patternProperties:
"^clock-controller@[0-9a-f]+$":
$ref: /schemas/clock/fsl,flexspi-clock.yaml#
+ "^pinctrl@[0-9a-f]+$":
+ $ref: /schemas/pinctrl/fsl,lx2160a-rcw-pinmux.yaml#
+ description:
+ The pad muxes of the RCW on the LX2160A, at their RCWSR12 to RCWSR14
+ and RCWSR27 windows, overridden through the DCSR view of this block.
+
required:
- compatible
- reg
+allOf:
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ const: fsl,lx2160a-dcfg
+ then:
+ patternProperties:
+ "^pinctrl@[0-9a-f]+$": false
+
additionalProperties: false
examples:
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v5 2/5] dt-bindings: soc: fsl: layerscape-dcfg: add the LX2160A pad-mux child
@ 2026-11-15 11:05 ` Vincent Jardin via B4 Relay
0 siblings, 0 replies; 14+ messages in thread
From: Vincent Jardin via B4 Relay @ 2026-11-15 11:05 UTC (permalink / raw)
To: Dong Aisheng, Fabio Estevam, Frank Li, Jacky Bai,
Pengutronix Kernel Team, NXP S32 Linux Team, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Christophe Leroy (CS GROUP), Shawn Guo, Sascha Hauer
Cc: linux-gpio, devicetree, linux-kernel, linuxppc-dev,
linux-arm-kernel, imx, Vladimir Oltean, Ioana Ciornei,
Vincent Jardin
From: Vincent Jardin <vjardin@free.fr>
On the LX2160A the DCFG node holds the pad mux, overridden through its
DCSR view. Allow fsl,lx2160a-dcfg with simple-mfd, so that the child is
populated, and the pinctrl child, on the LX2160A only.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Vincent Jardin <vjardin@free.fr>
---
.../bindings/soc/fsl/fsl,layerscape-dcfg.yaml | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-dcfg.yaml b/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-dcfg.yaml
index fc14fd0bf84b..bb9dbcfec188 100644
--- a/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-dcfg.yaml
+++ b/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-dcfg.yaml
@@ -32,6 +32,7 @@ properties:
- items:
- enum:
- fsl,ls1028a-dcfg
+ - fsl,lx2160a-dcfg
- const: syscon
- const: simple-mfd
@@ -66,10 +67,27 @@ patternProperties:
"^clock-controller@[0-9a-f]+$":
$ref: /schemas/clock/fsl,flexspi-clock.yaml#
+ "^pinctrl@[0-9a-f]+$":
+ $ref: /schemas/pinctrl/fsl,lx2160a-rcw-pinmux.yaml#
+ description:
+ The pad muxes of the RCW on the LX2160A, at their RCWSR12 to RCWSR14
+ and RCWSR27 windows, overridden through the DCSR view of this block.
+
required:
- compatible
- reg
+allOf:
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ const: fsl,lx2160a-dcfg
+ then:
+ patternProperties:
+ "^pinctrl@[0-9a-f]+$": false
+
additionalProperties: false
examples:
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v5 3/5] soc: fsl: guts: add the RCW override of the pad muxes
2026-11-15 11:05 ` Vincent Jardin via B4 Relay
@ 2026-11-15 11:05 ` Vincent Jardin via B4 Relay
-1 siblings, 0 replies; 14+ messages in thread
From: Vincent Jardin @ 2026-11-15 11:05 UTC (permalink / raw)
To: Dong Aisheng, Fabio Estevam, Frank Li, Jacky Bai,
Pengutronix Kernel Team, NXP S32 Linux Team, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Christophe Leroy (CS GROUP), Shawn Guo, Sascha Hauer
Cc: linux-gpio, devicetree, linux-kernel, linuxppc-dev,
linux-arm-kernel, imx, Vladimir Oltean, Ioana Ciornei,
Vincent Jardin
fsl_guts_rcw_rmw() only serves the SerDes lane modes. Export it for
the pad-mux fields of the RCW, and for them only:
- fsl_guts_pmux_read() reads the pad-mux fields of a status register
- fsl_guts_pmux_override() changes pad-mux fields of one under
rcwcr_lock and waits for the status register to follow
- fsl_guts_pmux_override_supported() tells whether the SoC has pad-mux
fields and whether the DCSR view of DCFG, which holds the override
registers, is mapped
Each SoC lists in its fsl_soc_data the fields that can be overridden,
per RCWSR: a register or a field outside of this list is refused, so
the SerDes protocols stay with fsl_guts_lane_set_mode(). The LX2160A
lists the pad muxes of RCWSR12 to RCWSR14 and of RCWSR27.
Suggested-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Vincent Jardin <vjardin@free.fr>
---
drivers/soc/fsl/guts.c | 122 ++++++++++++++++++++++++++++++++++++++++++++++-
include/linux/fsl/guts.h | 3 ++
2 files changed, 124 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/fsl/guts.c b/drivers/soc/fsl/guts.c
index 28361c63e26c..d8b8de6fbe32 100644
--- a/drivers/soc/fsl/guts.c
+++ b/drivers/soc/fsl/guts.c
@@ -53,6 +53,12 @@ struct fsl_soc_serdes_rcw_override {
int val;
};
+/* Pad-mux fields of the one-based RCWSRn, the ones that may be overridden */
+struct fsl_soc_pmux_mask {
+ unsigned int rcwsr;
+ u32 mask;
+};
+
struct fsl_soc_data {
const char *sfp_compat;
u32 uid_offset;
@@ -62,6 +68,7 @@ struct fsl_soc_data {
int (*serdes_get_rcw_override)(int index, int lane,
enum lynx_lane_mode lane_mode,
struct fsl_soc_serdes_rcw_override *override);
+ const struct fsl_soc_pmux_mask *pmux;
};
enum qoriq_die {
@@ -369,6 +376,107 @@ int fsl_guts_lane_set_mode(int serdes_idx, int lane, enum lynx_lane_mode lane_mo
}
EXPORT_SYMBOL_NS_GPL(fsl_guts_lane_set_mode, "FSL_GUTS");
+static const struct fsl_soc_pmux_mask *
+fsl_guts_get_pmux_mask(unsigned int rcwsr)
+{
+ const struct fsl_soc_pmux_mask *pmux;
+
+ if (!soc.data || !soc.data->pmux)
+ return NULL;
+
+ for (pmux = soc.data->pmux; pmux->rcwsr; pmux++) {
+ if (pmux->rcwsr == rcwsr)
+ return pmux;
+ }
+
+ return NULL;
+}
+
+/**
+ * fsl_guts_pmux_read() - read the pad-mux fields of a RCW status register
+ * @rcwsr: one-based index of the status register, as in RCWSR12
+ * @val: the pad-mux fields read, the other fields of the register are 0
+ *
+ * Return: 0 on success, -ENODEV before the DCFG block is mapped, -EINVAL
+ * when the register holds no pad-mux field on this SoC
+ */
+int fsl_guts_pmux_read(unsigned int rcwsr, u32 *val)
+{
+ const struct fsl_soc_pmux_mask *pmux;
+
+ if (!soc.dcfg_ccsr)
+ return -ENODEV;
+
+ pmux = fsl_guts_get_pmux_mask(rcwsr);
+ if (!pmux)
+ return -EINVAL;
+
+ *val = fsl_guts_read(&soc.dcfg_ccsr->rcwsr[rcwsr - 1]) & pmux->mask;
+
+ return 0;
+}
+EXPORT_SYMBOL_NS_GPL(fsl_guts_pmux_read, "FSL_GUTS");
+
+/**
+ * fsl_guts_pmux_override() - override pad-mux fields of the RCW
+ * @rcwsr: one-based index of the RCWSR and RCWCR pair, as in RCWSR12
+ * @val: the new value of the fields, in place
+ * @mask: the fields to change
+ *
+ * Only the pad-mux fields that the SoC lists can be changed: a SerDes
+ * protocol is changed with fsl_guts_lane_set_mode(), and the other fields
+ * of the RCW are refused.
+ *
+ * The fields outside @mask keep the value the status register shows. The
+ * override register is written and the status register polled until it
+ * shows the result, as fsl_guts_lane_set_mode() does for a SerDes lane.
+ *
+ * Context: takes rcwcr_lock, shared with fsl_guts_lane_set_mode(), and
+ * busy-polls the status register for up to RCW_TIMEOUT_US. Does not
+ * sleep; must not be called from interrupt context.
+ *
+ * Return: 0 on success, -ENODEV before the DCFG block is mapped,
+ * -EOPNOTSUPP without a DCSR mapping of DCFG, -EINVAL when @mask is not
+ * made of pad-mux fields of the register, negative error otherwise
+ */
+int fsl_guts_pmux_override(unsigned int rcwsr, u32 val, u32 mask)
+{
+ const struct fsl_soc_pmux_mask *pmux;
+ int err;
+
+ if (!soc.dcfg_ccsr)
+ return -ENODEV;
+ if (!soc.dcfg_dcsr)
+ return -EOPNOTSUPP;
+
+ pmux = fsl_guts_get_pmux_mask(rcwsr);
+ if (!pmux || !mask || (mask & ~pmux->mask))
+ return -EINVAL;
+
+ spin_lock(&soc.rcwcr_lock);
+ err = fsl_guts_rcw_rmw(rcwsr - 1, val & mask, mask);
+ spin_unlock(&soc.rcwcr_lock);
+ if (err)
+ pr_err("RCW override of RCWSR%u failed: %pe\n", rcwsr,
+ ERR_PTR(err));
+
+ return err;
+}
+EXPORT_SYMBOL_NS_GPL(fsl_guts_pmux_override, "FSL_GUTS");
+
+/**
+ * fsl_guts_pmux_override_supported() - can the pad muxes be overridden?
+ *
+ * Return: true when the SoC lists pad-mux fields and the DCFG block is
+ * mapped with its DCSR view, the second reg of the dcfg node, which holds
+ * the override registers
+ */
+bool fsl_guts_pmux_override_supported(void)
+{
+ return soc.dcfg_ccsr && soc.dcfg_dcsr && soc.data && soc.data->pmux;
+}
+EXPORT_SYMBOL_NS_GPL(fsl_guts_pmux_override_supported, "FSL_GUTS");
+
static u64 fsl_guts_get_soc_uid(const char *compat, unsigned int offset)
{
struct device_node *np;
@@ -579,6 +687,18 @@ static const struct fsl_soc_data ls1028a_data = {
.num_serdes_lanes = 4,
};
+static const struct fsl_soc_pmux_mask lx2160a_pmux[] = {
+ { 12, GENMASK(29, 0) }, /* IIC2..SDHC1_DIR */
+ { 13, GENMASK(29, 0) }, /* SDHC2_DAT74..EVT43 */
+ { 14, GENMASK(10, 0) }, /* EVT20..IIC1 */
+ { 27, GENMASK(7, 0) }, /* EC1, EC2, USB_EXT, GTX_CLK, SDHC1_DS */
+ {}
+};
+
+static const struct fsl_soc_data lx2160a_data = {
+ .pmux = lx2160a_pmux,
+};
+
/*
* Table for matching compatible strings, for device tree
* guts node, for Freescale QorIQ SOCs.
@@ -606,7 +726,7 @@ static const struct of_device_id fsl_guts_of_match[] = {
{ .compatible = "fsl,ls1088a-dcfg", .data = &ls1088a_data},
{ .compatible = "fsl,ls1012a-dcfg", },
{ .compatible = "fsl,ls1046a-dcfg", .data = &ls1046a_data},
- { .compatible = "fsl,lx2160a-dcfg", },
+ { .compatible = "fsl,lx2160a-dcfg", .data = &lx2160a_data},
{ .compatible = "fsl,ls1028a-dcfg", .data = &ls1028a_data},
{}
};
diff --git a/include/linux/fsl/guts.h b/include/linux/fsl/guts.h
index 8d5ffb985fee..ae245afeb7b9 100644
--- a/include/linux/fsl/guts.h
+++ b/include/linux/fsl/guts.h
@@ -142,6 +142,9 @@ int fsl_guts_lane_validate(int serdes_idx, int lane,
enum lynx_lane_mode lane_mode);
int fsl_guts_lane_set_mode(int serdes_idx, int lane,
enum lynx_lane_mode lane_mode);
+int fsl_guts_pmux_read(unsigned int rcwsr, u32 *val);
+int fsl_guts_pmux_override(unsigned int rcwsr, u32 val, u32 mask);
+bool fsl_guts_pmux_override_supported(void);
/* Alternate function signal multiplex control */
#define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x))
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v5 3/5] soc: fsl: guts: add the RCW override of the pad muxes
@ 2026-11-15 11:05 ` Vincent Jardin via B4 Relay
0 siblings, 0 replies; 14+ messages in thread
From: Vincent Jardin via B4 Relay @ 2026-11-15 11:05 UTC (permalink / raw)
To: Dong Aisheng, Fabio Estevam, Frank Li, Jacky Bai,
Pengutronix Kernel Team, NXP S32 Linux Team, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Christophe Leroy (CS GROUP), Shawn Guo, Sascha Hauer
Cc: linux-gpio, devicetree, linux-kernel, linuxppc-dev,
linux-arm-kernel, imx, Vladimir Oltean, Ioana Ciornei,
Vincent Jardin
From: Vincent Jardin <vjardin@free.fr>
fsl_guts_rcw_rmw() only serves the SerDes lane modes. Export it for
the pad-mux fields of the RCW, and for them only:
- fsl_guts_pmux_read() reads the pad-mux fields of a status register
- fsl_guts_pmux_override() changes pad-mux fields of one under
rcwcr_lock and waits for the status register to follow
- fsl_guts_pmux_override_supported() tells whether the SoC has pad-mux
fields and whether the DCSR view of DCFG, which holds the override
registers, is mapped
Each SoC lists in its fsl_soc_data the fields that can be overridden,
per RCWSR: a register or a field outside of this list is refused, so
the SerDes protocols stay with fsl_guts_lane_set_mode(). The LX2160A
lists the pad muxes of RCWSR12 to RCWSR14 and of RCWSR27.
Suggested-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Vincent Jardin <vjardin@free.fr>
---
drivers/soc/fsl/guts.c | 122 ++++++++++++++++++++++++++++++++++++++++++++++-
include/linux/fsl/guts.h | 3 ++
2 files changed, 124 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/fsl/guts.c b/drivers/soc/fsl/guts.c
index 28361c63e26c..d8b8de6fbe32 100644
--- a/drivers/soc/fsl/guts.c
+++ b/drivers/soc/fsl/guts.c
@@ -53,6 +53,12 @@ struct fsl_soc_serdes_rcw_override {
int val;
};
+/* Pad-mux fields of the one-based RCWSRn, the ones that may be overridden */
+struct fsl_soc_pmux_mask {
+ unsigned int rcwsr;
+ u32 mask;
+};
+
struct fsl_soc_data {
const char *sfp_compat;
u32 uid_offset;
@@ -62,6 +68,7 @@ struct fsl_soc_data {
int (*serdes_get_rcw_override)(int index, int lane,
enum lynx_lane_mode lane_mode,
struct fsl_soc_serdes_rcw_override *override);
+ const struct fsl_soc_pmux_mask *pmux;
};
enum qoriq_die {
@@ -369,6 +376,107 @@ int fsl_guts_lane_set_mode(int serdes_idx, int lane, enum lynx_lane_mode lane_mo
}
EXPORT_SYMBOL_NS_GPL(fsl_guts_lane_set_mode, "FSL_GUTS");
+static const struct fsl_soc_pmux_mask *
+fsl_guts_get_pmux_mask(unsigned int rcwsr)
+{
+ const struct fsl_soc_pmux_mask *pmux;
+
+ if (!soc.data || !soc.data->pmux)
+ return NULL;
+
+ for (pmux = soc.data->pmux; pmux->rcwsr; pmux++) {
+ if (pmux->rcwsr == rcwsr)
+ return pmux;
+ }
+
+ return NULL;
+}
+
+/**
+ * fsl_guts_pmux_read() - read the pad-mux fields of a RCW status register
+ * @rcwsr: one-based index of the status register, as in RCWSR12
+ * @val: the pad-mux fields read, the other fields of the register are 0
+ *
+ * Return: 0 on success, -ENODEV before the DCFG block is mapped, -EINVAL
+ * when the register holds no pad-mux field on this SoC
+ */
+int fsl_guts_pmux_read(unsigned int rcwsr, u32 *val)
+{
+ const struct fsl_soc_pmux_mask *pmux;
+
+ if (!soc.dcfg_ccsr)
+ return -ENODEV;
+
+ pmux = fsl_guts_get_pmux_mask(rcwsr);
+ if (!pmux)
+ return -EINVAL;
+
+ *val = fsl_guts_read(&soc.dcfg_ccsr->rcwsr[rcwsr - 1]) & pmux->mask;
+
+ return 0;
+}
+EXPORT_SYMBOL_NS_GPL(fsl_guts_pmux_read, "FSL_GUTS");
+
+/**
+ * fsl_guts_pmux_override() - override pad-mux fields of the RCW
+ * @rcwsr: one-based index of the RCWSR and RCWCR pair, as in RCWSR12
+ * @val: the new value of the fields, in place
+ * @mask: the fields to change
+ *
+ * Only the pad-mux fields that the SoC lists can be changed: a SerDes
+ * protocol is changed with fsl_guts_lane_set_mode(), and the other fields
+ * of the RCW are refused.
+ *
+ * The fields outside @mask keep the value the status register shows. The
+ * override register is written and the status register polled until it
+ * shows the result, as fsl_guts_lane_set_mode() does for a SerDes lane.
+ *
+ * Context: takes rcwcr_lock, shared with fsl_guts_lane_set_mode(), and
+ * busy-polls the status register for up to RCW_TIMEOUT_US. Does not
+ * sleep; must not be called from interrupt context.
+ *
+ * Return: 0 on success, -ENODEV before the DCFG block is mapped,
+ * -EOPNOTSUPP without a DCSR mapping of DCFG, -EINVAL when @mask is not
+ * made of pad-mux fields of the register, negative error otherwise
+ */
+int fsl_guts_pmux_override(unsigned int rcwsr, u32 val, u32 mask)
+{
+ const struct fsl_soc_pmux_mask *pmux;
+ int err;
+
+ if (!soc.dcfg_ccsr)
+ return -ENODEV;
+ if (!soc.dcfg_dcsr)
+ return -EOPNOTSUPP;
+
+ pmux = fsl_guts_get_pmux_mask(rcwsr);
+ if (!pmux || !mask || (mask & ~pmux->mask))
+ return -EINVAL;
+
+ spin_lock(&soc.rcwcr_lock);
+ err = fsl_guts_rcw_rmw(rcwsr - 1, val & mask, mask);
+ spin_unlock(&soc.rcwcr_lock);
+ if (err)
+ pr_err("RCW override of RCWSR%u failed: %pe\n", rcwsr,
+ ERR_PTR(err));
+
+ return err;
+}
+EXPORT_SYMBOL_NS_GPL(fsl_guts_pmux_override, "FSL_GUTS");
+
+/**
+ * fsl_guts_pmux_override_supported() - can the pad muxes be overridden?
+ *
+ * Return: true when the SoC lists pad-mux fields and the DCFG block is
+ * mapped with its DCSR view, the second reg of the dcfg node, which holds
+ * the override registers
+ */
+bool fsl_guts_pmux_override_supported(void)
+{
+ return soc.dcfg_ccsr && soc.dcfg_dcsr && soc.data && soc.data->pmux;
+}
+EXPORT_SYMBOL_NS_GPL(fsl_guts_pmux_override_supported, "FSL_GUTS");
+
static u64 fsl_guts_get_soc_uid(const char *compat, unsigned int offset)
{
struct device_node *np;
@@ -579,6 +687,18 @@ static const struct fsl_soc_data ls1028a_data = {
.num_serdes_lanes = 4,
};
+static const struct fsl_soc_pmux_mask lx2160a_pmux[] = {
+ { 12, GENMASK(29, 0) }, /* IIC2..SDHC1_DIR */
+ { 13, GENMASK(29, 0) }, /* SDHC2_DAT74..EVT43 */
+ { 14, GENMASK(10, 0) }, /* EVT20..IIC1 */
+ { 27, GENMASK(7, 0) }, /* EC1, EC2, USB_EXT, GTX_CLK, SDHC1_DS */
+ {}
+};
+
+static const struct fsl_soc_data lx2160a_data = {
+ .pmux = lx2160a_pmux,
+};
+
/*
* Table for matching compatible strings, for device tree
* guts node, for Freescale QorIQ SOCs.
@@ -606,7 +726,7 @@ static const struct of_device_id fsl_guts_of_match[] = {
{ .compatible = "fsl,ls1088a-dcfg", .data = &ls1088a_data},
{ .compatible = "fsl,ls1012a-dcfg", },
{ .compatible = "fsl,ls1046a-dcfg", .data = &ls1046a_data},
- { .compatible = "fsl,lx2160a-dcfg", },
+ { .compatible = "fsl,lx2160a-dcfg", .data = &lx2160a_data},
{ .compatible = "fsl,ls1028a-dcfg", .data = &ls1028a_data},
{}
};
diff --git a/include/linux/fsl/guts.h b/include/linux/fsl/guts.h
index 8d5ffb985fee..ae245afeb7b9 100644
--- a/include/linux/fsl/guts.h
+++ b/include/linux/fsl/guts.h
@@ -142,6 +142,9 @@ int fsl_guts_lane_validate(int serdes_idx, int lane,
enum lynx_lane_mode lane_mode);
int fsl_guts_lane_set_mode(int serdes_idx, int lane,
enum lynx_lane_mode lane_mode);
+int fsl_guts_pmux_read(unsigned int rcwsr, u32 *val);
+int fsl_guts_pmux_override(unsigned int rcwsr, u32 val, u32 mask);
+bool fsl_guts_pmux_override_supported(void);
/* Alternate function signal multiplex control */
#define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x))
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v5 4/5] pinctrl: freescale: add the LX2160A RCW pad-mux driver
2026-11-15 11:05 ` Vincent Jardin via B4 Relay
@ 2026-11-15 11:05 ` Vincent Jardin via B4 Relay
-1 siblings, 0 replies; 14+ messages in thread
From: Vincent Jardin @ 2026-11-15 11:05 UTC (permalink / raw)
To: Dong Aisheng, Fabio Estevam, Frank Li, Jacky Bai,
Pengutronix Kernel Team, NXP S32 Linux Team, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Christophe Leroy (CS GROUP), Shawn Guo, Sascha Hauer
Cc: linux-gpio, devicetree, linux-kernel, linuxppc-dev,
linux-arm-kernel, imx, Vladimir Oltean, Ioana Ciornei,
Vincent Jardin
The LX2160A muxes its IIC, XSPI, SDHC, UART, IRQ and EVT pads from
fields of the RCW, read-only in RCWSR12..14 of DCFG and changed at
runtime through the same fields of the override registers in its DCSR
view, which read 0 until written.
Since commit 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c
gpio to support bus recovery") Linux drives them with pinctrl-single on
the override registers, so its first pin state clears every other field
of the word: a board whose RCW programs a non-zero pad mux loses those
pads at the first I2C probe.
Add a driver for the pad mux as a child of the DCFG node: the fields
of RCWSR12..14, the EC1, EC2, USB_EXT, GTX_CLK and SDHC1_DS ones of
RCWSR27, and their encoding.
Then pin states select them with the generic function and groups
properties, and every change goes through the RCW override
of fsl-guts, which reads the status register, writes the override and
waits for the status register to follow.
Signed-off-by: Vincent Jardin <vjardin@free.fr>
---
MAINTAINERS | 8 +
drivers/pinctrl/freescale/Kconfig | 15 ++
drivers/pinctrl/freescale/Makefile | 1 +
drivers/pinctrl/freescale/pinctrl-lx2160a.c | 401 ++++++++++++++++++++++++++++
4 files changed, 425 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 93abbb315065..106a0cc7f25c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20207,6 +20207,14 @@ F: Documentation/devicetree/bindings/clock/*imx*
F: drivers/clk/imx/
F: include/dt-bindings/clock/*imx*
+NXP LX2160A RCW PAD-MUX DRIVER
+M: Vincent Jardin <vjardin@free.fr>
+L: linux-gpio@vger.kernel.org
+L: imx@lists.linux.dev
+S: Maintained
+F: Documentation/devicetree/bindings/pinctrl/fsl,lx2160a-rcw-pinmux.yaml
+F: drivers/pinctrl/freescale/pinctrl-lx2160a.c
+
NXP NETC ETHERNET SWITCH DRIVER
M: Wei Fang <wei.fang@nxp.com>
R: Clark Wang <xiaoning.wang@nxp.com>
diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig
index fd53cf5bb843..f22685f38257 100644
--- a/drivers/pinctrl/freescale/Kconfig
+++ b/drivers/pinctrl/freescale/Kconfig
@@ -283,3 +283,18 @@ config PINCTRL_IMXRT1170
select PINCTRL_IMX
help
Say Y here to enable the imxrt1170 pinctrl driver
+
+config PINCTRL_LX2160A
+ bool "NXP LX2160A RCW pad-mux driver"
+ depends on OF
+ depends on ARCH_LAYERSCAPE || COMPILE_TEST
+ default ARCH_LAYERSCAPE
+ select FSL_GUTS
+ select GENERIC_PINCTRL_GROUPS
+ select GENERIC_PINMUX_FUNCTIONS
+ select GENERIC_PINCONF
+ help
+ Say Y here to mux the IIC, XSPI, SDHC, UART, IRQ, EVT, EC and USB
+ pads of the LX2160A at runtime. The pads are muxed by fields of the
+ RCW: the driver changes it in the DCSR view of the DCFG that fsl-guts
+ drives, and is what the I2C bus recovery of the LX2160A needs.
diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile
index d27085c2b4c4..5ec0d1710ad5 100644
--- a/drivers/pinctrl/freescale/Makefile
+++ b/drivers/pinctrl/freescale/Makefile
@@ -35,3 +35,4 @@ obj-$(CONFIG_PINCTRL_IMX25) += pinctrl-imx25.o
obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o
obj-$(CONFIG_PINCTRL_IMXRT1050) += pinctrl-imxrt1050.o
obj-$(CONFIG_PINCTRL_IMXRT1170) += pinctrl-imxrt1170.o
+obj-$(CONFIG_PINCTRL_LX2160A) += pinctrl-lx2160a.o
diff --git a/drivers/pinctrl/freescale/pinctrl-lx2160a.c b/drivers/pinctrl/freescale/pinctrl-lx2160a.c
new file mode 100644
index 000000000000..0175ab62e143
--- /dev/null
+++ b/drivers/pinctrl/freescale/pinctrl-lx2160a.c
@@ -0,0 +1,401 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * LX2160A pad muxes: fields of the RCW, changed at
+ * runtime.
+ *
+ * Copyright 2026 Free Mobile - Vincent Jardin
+ */
+
+#include <linux/bits.h>
+#include <linux/fsl/guts.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/seq_file.h>
+
+#include "../core.h"
+#include "../pinmux.h"
+
+struct lx2160a_pmux_func {
+ const char *name;
+ u8 val;
+};
+
+struct lx2160a_pmux_group {
+ const char *name;
+ u8 rcwsr; /* 12..14, 27 */
+ u8 shift;
+ u8 width;
+ const struct lx2160a_pmux_func *funcs;
+ u8 nfuncs;
+};
+
+#define LX2160A_PMUX_FUNC(_name, _val) { .name = _name, .val = _val }
+#define LX2160A_PMUX_GROUP(_name, _rcwsr, _shift, _width, _funcs) \
+ { \
+ .name = _name, .rcwsr = _rcwsr, \
+ .shift = _shift, .width = _width, \
+ .funcs = _funcs, .nfuncs = ARRAY_SIZE(_funcs), \
+ }
+
+static const struct lx2160a_pmux_func iic2_funcs[] = {
+ LX2160A_PMUX_FUNC("i2c", 0), LX2160A_PMUX_FUNC("gpio", 1),
+ LX2160A_PMUX_FUNC("flextimer", 2), LX2160A_PMUX_FUNC("sdhc", 6),
+};
+
+static const struct lx2160a_pmux_func iic3_funcs[] = {
+ LX2160A_PMUX_FUNC("i2c", 0), LX2160A_PMUX_FUNC("gpio", 1),
+ LX2160A_PMUX_FUNC("can", 2), LX2160A_PMUX_FUNC("evt", 6),
+};
+
+static const struct lx2160a_pmux_func iic5_funcs[] = {
+ LX2160A_PMUX_FUNC("i2c", 0), LX2160A_PMUX_FUNC("gpio", 1),
+ LX2160A_PMUX_FUNC("sdhc-clk", 2), LX2160A_PMUX_FUNC("spi", 3),
+};
+
+static const struct lx2160a_pmux_func iic6_funcs[] = {
+ LX2160A_PMUX_FUNC("i2c", 0), LX2160A_PMUX_FUNC("gpio", 1),
+ LX2160A_PMUX_FUNC("sdhc-clk", 2),
+};
+
+static const struct lx2160a_pmux_func xspi1_funcs[] = {
+ LX2160A_PMUX_FUNC("flexspi", 0), LX2160A_PMUX_FUNC("gpio", 1),
+};
+
+static const struct lx2160a_pmux_func sdhc1_base_funcs[] = {
+ LX2160A_PMUX_FUNC("sdhc", 0), LX2160A_PMUX_FUNC("gpio", 1),
+ LX2160A_PMUX_FUNC("spi", 2), LX2160A_PMUX_FUNC("sdhc-spi", 3),
+ LX2160A_PMUX_FUNC("sdhc-data4", 4),
+};
+
+static const struct lx2160a_pmux_func sdhc1_dir_funcs[] = {
+ LX2160A_PMUX_FUNC("sdhc", 0), LX2160A_PMUX_FUNC("gpio", 1),
+ LX2160A_PMUX_FUNC("spi", 3), LX2160A_PMUX_FUNC("sdhc-data", 4),
+};
+
+static const struct lx2160a_pmux_func sdhc2_data74_funcs[] = {
+ LX2160A_PMUX_FUNC("sdhc", 0), LX2160A_PMUX_FUNC("gpio", 1),
+ LX2160A_PMUX_FUNC("i2c", 2), LX2160A_PMUX_FUNC("flexspi", 6),
+};
+
+static const struct lx2160a_pmux_func sdhc2_base_funcs[] = {
+ LX2160A_PMUX_FUNC("sdhc", 0), LX2160A_PMUX_FUNC("gpio", 1),
+ LX2160A_PMUX_FUNC("spi", 2), LX2160A_PMUX_FUNC("flexspi", 6),
+};
+
+static const struct lx2160a_pmux_func uart_funcs[] = {
+ LX2160A_PMUX_FUNC("uart", 0), LX2160A_PMUX_FUNC("gpio", 1),
+};
+
+static const struct lx2160a_pmux_func uart1_rtscts_funcs[] = {
+ LX2160A_PMUX_FUNC("uart", 0), LX2160A_PMUX_FUNC("gpio", 1),
+ LX2160A_PMUX_FUNC("uart3", 2),
+};
+
+static const struct lx2160a_pmux_func uart2_rtscts_funcs[] = {
+ LX2160A_PMUX_FUNC("uart", 0), LX2160A_PMUX_FUNC("gpio", 1),
+ LX2160A_PMUX_FUNC("uart4", 2),
+};
+
+static const struct lx2160a_pmux_func irq_funcs[] = {
+ LX2160A_PMUX_FUNC("irq", 0), LX2160A_PMUX_FUNC("gpio", 1),
+};
+
+static const struct lx2160a_pmux_func irq_flextimer_funcs[] = {
+ LX2160A_PMUX_FUNC("irq", 0), LX2160A_PMUX_FUNC("gpio", 1),
+ LX2160A_PMUX_FUNC("flextimer", 2),
+};
+
+static const struct lx2160a_pmux_func evt_funcs[] = {
+ LX2160A_PMUX_FUNC("evt", 0), LX2160A_PMUX_FUNC("gpio", 1),
+ LX2160A_PMUX_FUNC("flextimer", 2),
+};
+
+static const struct lx2160a_pmux_func clk_out_funcs[] = {
+ LX2160A_PMUX_FUNC("gpio", 1), LX2160A_PMUX_FUNC("flextimer", 2),
+};
+
+static const struct lx2160a_pmux_func asleep_funcs[] = {
+ LX2160A_PMUX_FUNC("asleep", 0), LX2160A_PMUX_FUNC("gpio", 1),
+ LX2160A_PMUX_FUNC("evt", 2),
+};
+
+static const struct lx2160a_pmux_func reset_req_funcs[] = {
+ LX2160A_PMUX_FUNC("reset-req", 0), LX2160A_PMUX_FUNC("gpio", 1),
+};
+
+static const struct lx2160a_pmux_func iic1_funcs[] = {
+ LX2160A_PMUX_FUNC("i2c", 0), LX2160A_PMUX_FUNC("gpio", 1),
+};
+
+static const struct lx2160a_pmux_func ec1_funcs[] = {
+ LX2160A_PMUX_FUNC("rgmii", 0), LX2160A_PMUX_FUNC("gpio", 1),
+};
+
+static const struct lx2160a_pmux_func ec2_funcs[] = {
+ LX2160A_PMUX_FUNC("rgmii", 0), LX2160A_PMUX_FUNC("gpio", 1),
+ LX2160A_PMUX_FUNC("tsec-1588", 2),
+};
+
+static const struct lx2160a_pmux_func usb_ext_funcs[] = {
+ LX2160A_PMUX_FUNC("usb", 0), LX2160A_PMUX_FUNC("gpio", 1),
+};
+
+static const struct lx2160a_pmux_func gtx_clk_funcs[] = {
+ LX2160A_PMUX_FUNC("gtx-clk", 0), LX2160A_PMUX_FUNC("gpio", 1),
+};
+
+static const struct lx2160a_pmux_func sdhc1_ds_funcs[] = {
+ LX2160A_PMUX_FUNC("sdhc", 0), LX2160A_PMUX_FUNC("gpio", 1),
+ LX2160A_PMUX_FUNC("spi", 2),
+};
+
+static const struct lx2160a_pmux_group lx2160a_pmux_groups[] = {
+ /* RCWSR12 */
+ LX2160A_PMUX_GROUP("iic2", 12, 0, 3, iic2_funcs),
+ LX2160A_PMUX_GROUP("iic3", 12, 3, 3, iic3_funcs),
+ LX2160A_PMUX_GROUP("iic4", 12, 6, 3, iic3_funcs),
+ LX2160A_PMUX_GROUP("iic5", 12, 9, 3, iic5_funcs),
+ LX2160A_PMUX_GROUP("iic6", 12, 12, 3, iic6_funcs),
+ LX2160A_PMUX_GROUP("xspi1-data74", 12, 15, 3, xspi1_funcs),
+ LX2160A_PMUX_GROUP("xspi1-data30", 12, 18, 3, xspi1_funcs),
+ LX2160A_PMUX_GROUP("xspi1-base", 12, 21, 3, xspi1_funcs),
+ LX2160A_PMUX_GROUP("sdhc1-base", 12, 24, 3, sdhc1_base_funcs),
+ LX2160A_PMUX_GROUP("sdhc1-dir", 12, 27, 3, sdhc1_dir_funcs),
+ /* RCWSR13 */
+ LX2160A_PMUX_GROUP("sdhc2-data74", 13, 0, 3, sdhc2_data74_funcs),
+ LX2160A_PMUX_GROUP("sdhc2-base", 13, 3, 3, sdhc2_base_funcs),
+ LX2160A_PMUX_GROUP("uart1-soutsin", 13, 6, 3, uart_funcs),
+ LX2160A_PMUX_GROUP("uart1-rtscts", 13, 9, 3, uart1_rtscts_funcs),
+ LX2160A_PMUX_GROUP("uart2-soutsin", 13, 12, 3, uart_funcs),
+ LX2160A_PMUX_GROUP("uart2-rtscts", 13, 15, 3, uart2_rtscts_funcs),
+ LX2160A_PMUX_GROUP("irq11-8", 13, 18, 3, irq_funcs),
+ LX2160A_PMUX_GROUP("irq7-4", 13, 21, 3, irq_flextimer_funcs),
+ LX2160A_PMUX_GROUP("irq3-0", 13, 24, 3, irq_flextimer_funcs),
+ LX2160A_PMUX_GROUP("evt4-3", 13, 27, 3, evt_funcs),
+ /* RCWSR14 */
+ LX2160A_PMUX_GROUP("evt2-0", 14, 0, 3, evt_funcs),
+ LX2160A_PMUX_GROUP("clk-out", 14, 3, 3, clk_out_funcs),
+ LX2160A_PMUX_GROUP("asleep", 14, 6, 3, asleep_funcs),
+ LX2160A_PMUX_GROUP("reset-req", 14, 9, 1, reset_req_funcs),
+ LX2160A_PMUX_GROUP("iic1", 14, 10, 1, iic1_funcs),
+ /* RCWSR27 */
+ LX2160A_PMUX_GROUP("ec1", 27, 0, 2, ec1_funcs),
+ LX2160A_PMUX_GROUP("ec2", 27, 2, 2, ec2_funcs),
+ LX2160A_PMUX_GROUP("usb-ext", 27, 4, 1, usb_ext_funcs),
+ LX2160A_PMUX_GROUP("gtx-clk", 27, 5, 1, gtx_clk_funcs),
+ LX2160A_PMUX_GROUP("sdhc1-ds", 27, 6, 2, sdhc1_ds_funcs),
+};
+
+struct lx2160a_pmux {
+ struct device *dev;
+ struct pinctrl_dev *pctl;
+ struct pinctrl_desc desc;
+ struct pinctrl_pin_desc pins[ARRAY_SIZE(lx2160a_pmux_groups)];
+};
+
+static u32 lx2160a_pmux_group_mask(const struct lx2160a_pmux_group *group)
+{
+ return GENMASK(group->shift + group->width - 1, group->shift);
+}
+
+static void lx2160a_pmux_pin_dbg_show(struct pinctrl_dev *pctldev,
+ struct seq_file *s, unsigned int pin)
+{
+ const struct lx2160a_pmux_group *group = &lx2160a_pmux_groups[pin];
+ unsigned int i;
+ u32 val;
+
+ if (fsl_guts_pmux_read(group->rcwsr, &val))
+ return;
+
+ val = (val & lx2160a_pmux_group_mask(group)) >> group->shift;
+ for (i = 0; i < group->nfuncs; i++) {
+ if (group->funcs[i].val == val) {
+ seq_puts(s, group->funcs[i].name);
+ return;
+ }
+ }
+ seq_printf(s, "0x%x", val);
+}
+
+static const struct pinctrl_ops lx2160a_pmux_pctlops = {
+ .get_groups_count = pinctrl_generic_get_group_count,
+ .get_group_name = pinctrl_generic_get_group_name,
+ .get_group_pins = pinctrl_generic_get_group_pins,
+ .pin_dbg_show = lx2160a_pmux_pin_dbg_show,
+ .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
+ .dt_free_map = pinconf_generic_dt_free_map,
+};
+
+static int lx2160a_pmux_set_mux(struct pinctrl_dev *pctldev,
+ unsigned int fsel, unsigned int gsel)
+{
+ struct lx2160a_pmux *pmux = pinctrl_dev_get_drvdata(pctldev);
+ const struct function_desc *func;
+ const struct lx2160a_pmux_group *group;
+ const struct group_desc *grp;
+ unsigned int i;
+
+ func = pinmux_generic_get_function(pctldev, fsel);
+ grp = pinctrl_generic_get_group(pctldev, gsel);
+ if (!func || !grp)
+ return -EINVAL;
+ group = grp->data;
+
+ for (i = 0; i < group->nfuncs; i++) {
+ if (!strcmp(group->funcs[i].name, func->func->name))
+ break;
+ }
+ if (i == group->nfuncs) {
+ dev_err(pmux->dev, "%s has no %s function\n",
+ group->name, func->func->name);
+ return -EINVAL;
+ }
+
+ return fsl_guts_pmux_override(group->rcwsr,
+ group->funcs[i].val << group->shift,
+ lx2160a_pmux_group_mask(group));
+}
+
+static const struct pinmux_ops lx2160a_pmux_pmxops = {
+ .get_functions_count = pinmux_generic_get_function_count,
+ .get_function_name = pinmux_generic_get_function_name,
+ .get_function_groups = pinmux_generic_get_function_groups,
+ .set_mux = lx2160a_pmux_set_mux,
+ .strict = true,
+};
+
+static int lx2160a_pmux_add_functions(struct lx2160a_pmux *pmux)
+{
+ const struct lx2160a_pmux_group *group;
+ const char **groups;
+ unsigned int i, j, k, n;
+ int ret;
+
+ for (i = 0; i < ARRAY_SIZE(lx2160a_pmux_groups); i++) {
+ group = &lx2160a_pmux_groups[i];
+ for (j = 0; j < group->nfuncs; j++) {
+ const char *name = group->funcs[j].name;
+ bool seen = false;
+
+ /* already added from an earlier group? */
+ for (k = 0; k < i && !seen; k++) {
+ const struct lx2160a_pmux_group *g =
+ &lx2160a_pmux_groups[k];
+ unsigned int l;
+
+ for (l = 0; l < g->nfuncs; l++)
+ if (!strcmp(g->funcs[l].name, name))
+ seen = true;
+ }
+ if (seen)
+ continue;
+
+ groups = devm_kcalloc(pmux->dev,
+ ARRAY_SIZE(lx2160a_pmux_groups),
+ sizeof(*groups), GFP_KERNEL);
+ if (!groups)
+ return -ENOMEM;
+ n = 0;
+ for (k = i; k < ARRAY_SIZE(lx2160a_pmux_groups); k++) {
+ const struct lx2160a_pmux_group *g =
+ &lx2160a_pmux_groups[k];
+ unsigned int l;
+
+ for (l = 0; l < g->nfuncs; l++)
+ if (!strcmp(g->funcs[l].name, name))
+ groups[n++] = g->name;
+ }
+ ret = pinmux_generic_add_function(pmux->pctl, name,
+ groups, n, NULL);
+ if (ret < 0)
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int lx2160a_pmux_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct lx2160a_pmux *pmux;
+ unsigned int i;
+ u32 val;
+ int ret;
+
+ /* The override needs the DCSR view of DCFG, mapped by fsl-guts */
+ if (!fsl_guts_pmux_override_supported())
+ return dev_err_probe(dev, -ENODEV,
+ "no RCW override through fsl-guts: the dcfg node needs its DCSR reg\n");
+
+ pmux = devm_kzalloc(dev, sizeof(*pmux), GFP_KERNEL);
+ if (!pmux)
+ return -ENOMEM;
+ pmux->dev = dev;
+
+ for (i = 0; i < ARRAY_SIZE(lx2160a_pmux_groups); i++) {
+ pmux->pins[i].number = i;
+ pmux->pins[i].name = lx2160a_pmux_groups[i].name;
+ }
+ pmux->desc.name = dev_name(dev);
+ pmux->desc.pins = pmux->pins;
+ pmux->desc.npins = ARRAY_SIZE(pmux->pins);
+ pmux->desc.pctlops = &lx2160a_pmux_pctlops;
+ pmux->desc.pmxops = &lx2160a_pmux_pmxops;
+ pmux->desc.owner = THIS_MODULE;
+
+ ret = devm_pinctrl_register_and_init(dev, &pmux->desc, pmux,
+ &pmux->pctl);
+ if (ret)
+ return dev_err_probe(dev, ret, "pinctrl registration failed\n");
+
+ for (i = 0; i < ARRAY_SIZE(lx2160a_pmux_groups); i++) {
+ ret = pinctrl_generic_add_group(pmux->pctl,
+ lx2160a_pmux_groups[i].name,
+ &pmux->pins[i].number, 1,
+ (void *)&lx2160a_pmux_groups[i]);
+ if (ret < 0)
+ return ret;
+ }
+
+ ret = lx2160a_pmux_add_functions(pmux);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < ARRAY_SIZE(lx2160a_pmux_groups); i++) {
+ u8 rcwsr = lx2160a_pmux_groups[i].rcwsr;
+
+ if (i && rcwsr == lx2160a_pmux_groups[i - 1].rcwsr)
+ continue;
+ if (!fsl_guts_pmux_read(rcwsr, &val))
+ dev_dbg(dev, "pad muxes of RCWSR%u = 0x%08x\n", rcwsr,
+ val);
+ }
+
+ return pinctrl_enable(pmux->pctl);
+}
+
+static const struct of_device_id lx2160a_pmux_of_match[] = {
+ { .compatible = "fsl,lx2160a-rcw-pinmux" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, lx2160a_pmux_of_match);
+
+static struct platform_driver lx2160a_pmux_driver = {
+ .driver = {
+ .name = "lx2160a-rcw-pinmux",
+ .of_match_table = lx2160a_pmux_of_match,
+ },
+ .probe = lx2160a_pmux_probe,
+};
+module_platform_driver(lx2160a_pmux_driver);
+
+MODULE_AUTHOR("Vincent Jardin <vjardin@free.fr>");
+MODULE_DESCRIPTION("NXP LX2160A RCW pad-mux driver");
+MODULE_LICENSE("GPL");
+MODULE_IMPORT_NS("FSL_GUTS");
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v5 4/5] pinctrl: freescale: add the LX2160A RCW pad-mux driver
@ 2026-11-15 11:05 ` Vincent Jardin via B4 Relay
0 siblings, 0 replies; 14+ messages in thread
From: Vincent Jardin via B4 Relay @ 2026-11-15 11:05 UTC (permalink / raw)
To: Dong Aisheng, Fabio Estevam, Frank Li, Jacky Bai,
Pengutronix Kernel Team, NXP S32 Linux Team, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Christophe Leroy (CS GROUP), Shawn Guo, Sascha Hauer
Cc: linux-gpio, devicetree, linux-kernel, linuxppc-dev,
linux-arm-kernel, imx, Vladimir Oltean, Ioana Ciornei,
Vincent Jardin
From: Vincent Jardin <vjardin@free.fr>
The LX2160A muxes its IIC, XSPI, SDHC, UART, IRQ and EVT pads from
fields of the RCW, read-only in RCWSR12..14 of DCFG and changed at
runtime through the same fields of the override registers in its DCSR
view, which read 0 until written.
Since commit 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c
gpio to support bus recovery") Linux drives them with pinctrl-single on
the override registers, so its first pin state clears every other field
of the word: a board whose RCW programs a non-zero pad mux loses those
pads at the first I2C probe.
Add a driver for the pad mux as a child of the DCFG node: the fields
of RCWSR12..14, the EC1, EC2, USB_EXT, GTX_CLK and SDHC1_DS ones of
RCWSR27, and their encoding.
Then pin states select them with the generic function and groups
properties, and every change goes through the RCW override
of fsl-guts, which reads the status register, writes the override and
waits for the status register to follow.
Signed-off-by: Vincent Jardin <vjardin@free.fr>
---
MAINTAINERS | 8 +
drivers/pinctrl/freescale/Kconfig | 15 ++
drivers/pinctrl/freescale/Makefile | 1 +
drivers/pinctrl/freescale/pinctrl-lx2160a.c | 401 ++++++++++++++++++++++++++++
4 files changed, 425 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 93abbb315065..106a0cc7f25c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20207,6 +20207,14 @@ F: Documentation/devicetree/bindings/clock/*imx*
F: drivers/clk/imx/
F: include/dt-bindings/clock/*imx*
+NXP LX2160A RCW PAD-MUX DRIVER
+M: Vincent Jardin <vjardin@free.fr>
+L: linux-gpio@vger.kernel.org
+L: imx@lists.linux.dev
+S: Maintained
+F: Documentation/devicetree/bindings/pinctrl/fsl,lx2160a-rcw-pinmux.yaml
+F: drivers/pinctrl/freescale/pinctrl-lx2160a.c
+
NXP NETC ETHERNET SWITCH DRIVER
M: Wei Fang <wei.fang@nxp.com>
R: Clark Wang <xiaoning.wang@nxp.com>
diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig
index fd53cf5bb843..f22685f38257 100644
--- a/drivers/pinctrl/freescale/Kconfig
+++ b/drivers/pinctrl/freescale/Kconfig
@@ -283,3 +283,18 @@ config PINCTRL_IMXRT1170
select PINCTRL_IMX
help
Say Y here to enable the imxrt1170 pinctrl driver
+
+config PINCTRL_LX2160A
+ bool "NXP LX2160A RCW pad-mux driver"
+ depends on OF
+ depends on ARCH_LAYERSCAPE || COMPILE_TEST
+ default ARCH_LAYERSCAPE
+ select FSL_GUTS
+ select GENERIC_PINCTRL_GROUPS
+ select GENERIC_PINMUX_FUNCTIONS
+ select GENERIC_PINCONF
+ help
+ Say Y here to mux the IIC, XSPI, SDHC, UART, IRQ, EVT, EC and USB
+ pads of the LX2160A at runtime. The pads are muxed by fields of the
+ RCW: the driver changes it in the DCSR view of the DCFG that fsl-guts
+ drives, and is what the I2C bus recovery of the LX2160A needs.
diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile
index d27085c2b4c4..5ec0d1710ad5 100644
--- a/drivers/pinctrl/freescale/Makefile
+++ b/drivers/pinctrl/freescale/Makefile
@@ -35,3 +35,4 @@ obj-$(CONFIG_PINCTRL_IMX25) += pinctrl-imx25.o
obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o
obj-$(CONFIG_PINCTRL_IMXRT1050) += pinctrl-imxrt1050.o
obj-$(CONFIG_PINCTRL_IMXRT1170) += pinctrl-imxrt1170.o
+obj-$(CONFIG_PINCTRL_LX2160A) += pinctrl-lx2160a.o
diff --git a/drivers/pinctrl/freescale/pinctrl-lx2160a.c b/drivers/pinctrl/freescale/pinctrl-lx2160a.c
new file mode 100644
index 000000000000..0175ab62e143
--- /dev/null
+++ b/drivers/pinctrl/freescale/pinctrl-lx2160a.c
@@ -0,0 +1,401 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * LX2160A pad muxes: fields of the RCW, changed at
+ * runtime.
+ *
+ * Copyright 2026 Free Mobile - Vincent Jardin
+ */
+
+#include <linux/bits.h>
+#include <linux/fsl/guts.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/seq_file.h>
+
+#include "../core.h"
+#include "../pinmux.h"
+
+struct lx2160a_pmux_func {
+ const char *name;
+ u8 val;
+};
+
+struct lx2160a_pmux_group {
+ const char *name;
+ u8 rcwsr; /* 12..14, 27 */
+ u8 shift;
+ u8 width;
+ const struct lx2160a_pmux_func *funcs;
+ u8 nfuncs;
+};
+
+#define LX2160A_PMUX_FUNC(_name, _val) { .name = _name, .val = _val }
+#define LX2160A_PMUX_GROUP(_name, _rcwsr, _shift, _width, _funcs) \
+ { \
+ .name = _name, .rcwsr = _rcwsr, \
+ .shift = _shift, .width = _width, \
+ .funcs = _funcs, .nfuncs = ARRAY_SIZE(_funcs), \
+ }
+
+static const struct lx2160a_pmux_func iic2_funcs[] = {
+ LX2160A_PMUX_FUNC("i2c", 0), LX2160A_PMUX_FUNC("gpio", 1),
+ LX2160A_PMUX_FUNC("flextimer", 2), LX2160A_PMUX_FUNC("sdhc", 6),
+};
+
+static const struct lx2160a_pmux_func iic3_funcs[] = {
+ LX2160A_PMUX_FUNC("i2c", 0), LX2160A_PMUX_FUNC("gpio", 1),
+ LX2160A_PMUX_FUNC("can", 2), LX2160A_PMUX_FUNC("evt", 6),
+};
+
+static const struct lx2160a_pmux_func iic5_funcs[] = {
+ LX2160A_PMUX_FUNC("i2c", 0), LX2160A_PMUX_FUNC("gpio", 1),
+ LX2160A_PMUX_FUNC("sdhc-clk", 2), LX2160A_PMUX_FUNC("spi", 3),
+};
+
+static const struct lx2160a_pmux_func iic6_funcs[] = {
+ LX2160A_PMUX_FUNC("i2c", 0), LX2160A_PMUX_FUNC("gpio", 1),
+ LX2160A_PMUX_FUNC("sdhc-clk", 2),
+};
+
+static const struct lx2160a_pmux_func xspi1_funcs[] = {
+ LX2160A_PMUX_FUNC("flexspi", 0), LX2160A_PMUX_FUNC("gpio", 1),
+};
+
+static const struct lx2160a_pmux_func sdhc1_base_funcs[] = {
+ LX2160A_PMUX_FUNC("sdhc", 0), LX2160A_PMUX_FUNC("gpio", 1),
+ LX2160A_PMUX_FUNC("spi", 2), LX2160A_PMUX_FUNC("sdhc-spi", 3),
+ LX2160A_PMUX_FUNC("sdhc-data4", 4),
+};
+
+static const struct lx2160a_pmux_func sdhc1_dir_funcs[] = {
+ LX2160A_PMUX_FUNC("sdhc", 0), LX2160A_PMUX_FUNC("gpio", 1),
+ LX2160A_PMUX_FUNC("spi", 3), LX2160A_PMUX_FUNC("sdhc-data", 4),
+};
+
+static const struct lx2160a_pmux_func sdhc2_data74_funcs[] = {
+ LX2160A_PMUX_FUNC("sdhc", 0), LX2160A_PMUX_FUNC("gpio", 1),
+ LX2160A_PMUX_FUNC("i2c", 2), LX2160A_PMUX_FUNC("flexspi", 6),
+};
+
+static const struct lx2160a_pmux_func sdhc2_base_funcs[] = {
+ LX2160A_PMUX_FUNC("sdhc", 0), LX2160A_PMUX_FUNC("gpio", 1),
+ LX2160A_PMUX_FUNC("spi", 2), LX2160A_PMUX_FUNC("flexspi", 6),
+};
+
+static const struct lx2160a_pmux_func uart_funcs[] = {
+ LX2160A_PMUX_FUNC("uart", 0), LX2160A_PMUX_FUNC("gpio", 1),
+};
+
+static const struct lx2160a_pmux_func uart1_rtscts_funcs[] = {
+ LX2160A_PMUX_FUNC("uart", 0), LX2160A_PMUX_FUNC("gpio", 1),
+ LX2160A_PMUX_FUNC("uart3", 2),
+};
+
+static const struct lx2160a_pmux_func uart2_rtscts_funcs[] = {
+ LX2160A_PMUX_FUNC("uart", 0), LX2160A_PMUX_FUNC("gpio", 1),
+ LX2160A_PMUX_FUNC("uart4", 2),
+};
+
+static const struct lx2160a_pmux_func irq_funcs[] = {
+ LX2160A_PMUX_FUNC("irq", 0), LX2160A_PMUX_FUNC("gpio", 1),
+};
+
+static const struct lx2160a_pmux_func irq_flextimer_funcs[] = {
+ LX2160A_PMUX_FUNC("irq", 0), LX2160A_PMUX_FUNC("gpio", 1),
+ LX2160A_PMUX_FUNC("flextimer", 2),
+};
+
+static const struct lx2160a_pmux_func evt_funcs[] = {
+ LX2160A_PMUX_FUNC("evt", 0), LX2160A_PMUX_FUNC("gpio", 1),
+ LX2160A_PMUX_FUNC("flextimer", 2),
+};
+
+static const struct lx2160a_pmux_func clk_out_funcs[] = {
+ LX2160A_PMUX_FUNC("gpio", 1), LX2160A_PMUX_FUNC("flextimer", 2),
+};
+
+static const struct lx2160a_pmux_func asleep_funcs[] = {
+ LX2160A_PMUX_FUNC("asleep", 0), LX2160A_PMUX_FUNC("gpio", 1),
+ LX2160A_PMUX_FUNC("evt", 2),
+};
+
+static const struct lx2160a_pmux_func reset_req_funcs[] = {
+ LX2160A_PMUX_FUNC("reset-req", 0), LX2160A_PMUX_FUNC("gpio", 1),
+};
+
+static const struct lx2160a_pmux_func iic1_funcs[] = {
+ LX2160A_PMUX_FUNC("i2c", 0), LX2160A_PMUX_FUNC("gpio", 1),
+};
+
+static const struct lx2160a_pmux_func ec1_funcs[] = {
+ LX2160A_PMUX_FUNC("rgmii", 0), LX2160A_PMUX_FUNC("gpio", 1),
+};
+
+static const struct lx2160a_pmux_func ec2_funcs[] = {
+ LX2160A_PMUX_FUNC("rgmii", 0), LX2160A_PMUX_FUNC("gpio", 1),
+ LX2160A_PMUX_FUNC("tsec-1588", 2),
+};
+
+static const struct lx2160a_pmux_func usb_ext_funcs[] = {
+ LX2160A_PMUX_FUNC("usb", 0), LX2160A_PMUX_FUNC("gpio", 1),
+};
+
+static const struct lx2160a_pmux_func gtx_clk_funcs[] = {
+ LX2160A_PMUX_FUNC("gtx-clk", 0), LX2160A_PMUX_FUNC("gpio", 1),
+};
+
+static const struct lx2160a_pmux_func sdhc1_ds_funcs[] = {
+ LX2160A_PMUX_FUNC("sdhc", 0), LX2160A_PMUX_FUNC("gpio", 1),
+ LX2160A_PMUX_FUNC("spi", 2),
+};
+
+static const struct lx2160a_pmux_group lx2160a_pmux_groups[] = {
+ /* RCWSR12 */
+ LX2160A_PMUX_GROUP("iic2", 12, 0, 3, iic2_funcs),
+ LX2160A_PMUX_GROUP("iic3", 12, 3, 3, iic3_funcs),
+ LX2160A_PMUX_GROUP("iic4", 12, 6, 3, iic3_funcs),
+ LX2160A_PMUX_GROUP("iic5", 12, 9, 3, iic5_funcs),
+ LX2160A_PMUX_GROUP("iic6", 12, 12, 3, iic6_funcs),
+ LX2160A_PMUX_GROUP("xspi1-data74", 12, 15, 3, xspi1_funcs),
+ LX2160A_PMUX_GROUP("xspi1-data30", 12, 18, 3, xspi1_funcs),
+ LX2160A_PMUX_GROUP("xspi1-base", 12, 21, 3, xspi1_funcs),
+ LX2160A_PMUX_GROUP("sdhc1-base", 12, 24, 3, sdhc1_base_funcs),
+ LX2160A_PMUX_GROUP("sdhc1-dir", 12, 27, 3, sdhc1_dir_funcs),
+ /* RCWSR13 */
+ LX2160A_PMUX_GROUP("sdhc2-data74", 13, 0, 3, sdhc2_data74_funcs),
+ LX2160A_PMUX_GROUP("sdhc2-base", 13, 3, 3, sdhc2_base_funcs),
+ LX2160A_PMUX_GROUP("uart1-soutsin", 13, 6, 3, uart_funcs),
+ LX2160A_PMUX_GROUP("uart1-rtscts", 13, 9, 3, uart1_rtscts_funcs),
+ LX2160A_PMUX_GROUP("uart2-soutsin", 13, 12, 3, uart_funcs),
+ LX2160A_PMUX_GROUP("uart2-rtscts", 13, 15, 3, uart2_rtscts_funcs),
+ LX2160A_PMUX_GROUP("irq11-8", 13, 18, 3, irq_funcs),
+ LX2160A_PMUX_GROUP("irq7-4", 13, 21, 3, irq_flextimer_funcs),
+ LX2160A_PMUX_GROUP("irq3-0", 13, 24, 3, irq_flextimer_funcs),
+ LX2160A_PMUX_GROUP("evt4-3", 13, 27, 3, evt_funcs),
+ /* RCWSR14 */
+ LX2160A_PMUX_GROUP("evt2-0", 14, 0, 3, evt_funcs),
+ LX2160A_PMUX_GROUP("clk-out", 14, 3, 3, clk_out_funcs),
+ LX2160A_PMUX_GROUP("asleep", 14, 6, 3, asleep_funcs),
+ LX2160A_PMUX_GROUP("reset-req", 14, 9, 1, reset_req_funcs),
+ LX2160A_PMUX_GROUP("iic1", 14, 10, 1, iic1_funcs),
+ /* RCWSR27 */
+ LX2160A_PMUX_GROUP("ec1", 27, 0, 2, ec1_funcs),
+ LX2160A_PMUX_GROUP("ec2", 27, 2, 2, ec2_funcs),
+ LX2160A_PMUX_GROUP("usb-ext", 27, 4, 1, usb_ext_funcs),
+ LX2160A_PMUX_GROUP("gtx-clk", 27, 5, 1, gtx_clk_funcs),
+ LX2160A_PMUX_GROUP("sdhc1-ds", 27, 6, 2, sdhc1_ds_funcs),
+};
+
+struct lx2160a_pmux {
+ struct device *dev;
+ struct pinctrl_dev *pctl;
+ struct pinctrl_desc desc;
+ struct pinctrl_pin_desc pins[ARRAY_SIZE(lx2160a_pmux_groups)];
+};
+
+static u32 lx2160a_pmux_group_mask(const struct lx2160a_pmux_group *group)
+{
+ return GENMASK(group->shift + group->width - 1, group->shift);
+}
+
+static void lx2160a_pmux_pin_dbg_show(struct pinctrl_dev *pctldev,
+ struct seq_file *s, unsigned int pin)
+{
+ const struct lx2160a_pmux_group *group = &lx2160a_pmux_groups[pin];
+ unsigned int i;
+ u32 val;
+
+ if (fsl_guts_pmux_read(group->rcwsr, &val))
+ return;
+
+ val = (val & lx2160a_pmux_group_mask(group)) >> group->shift;
+ for (i = 0; i < group->nfuncs; i++) {
+ if (group->funcs[i].val == val) {
+ seq_puts(s, group->funcs[i].name);
+ return;
+ }
+ }
+ seq_printf(s, "0x%x", val);
+}
+
+static const struct pinctrl_ops lx2160a_pmux_pctlops = {
+ .get_groups_count = pinctrl_generic_get_group_count,
+ .get_group_name = pinctrl_generic_get_group_name,
+ .get_group_pins = pinctrl_generic_get_group_pins,
+ .pin_dbg_show = lx2160a_pmux_pin_dbg_show,
+ .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
+ .dt_free_map = pinconf_generic_dt_free_map,
+};
+
+static int lx2160a_pmux_set_mux(struct pinctrl_dev *pctldev,
+ unsigned int fsel, unsigned int gsel)
+{
+ struct lx2160a_pmux *pmux = pinctrl_dev_get_drvdata(pctldev);
+ const struct function_desc *func;
+ const struct lx2160a_pmux_group *group;
+ const struct group_desc *grp;
+ unsigned int i;
+
+ func = pinmux_generic_get_function(pctldev, fsel);
+ grp = pinctrl_generic_get_group(pctldev, gsel);
+ if (!func || !grp)
+ return -EINVAL;
+ group = grp->data;
+
+ for (i = 0; i < group->nfuncs; i++) {
+ if (!strcmp(group->funcs[i].name, func->func->name))
+ break;
+ }
+ if (i == group->nfuncs) {
+ dev_err(pmux->dev, "%s has no %s function\n",
+ group->name, func->func->name);
+ return -EINVAL;
+ }
+
+ return fsl_guts_pmux_override(group->rcwsr,
+ group->funcs[i].val << group->shift,
+ lx2160a_pmux_group_mask(group));
+}
+
+static const struct pinmux_ops lx2160a_pmux_pmxops = {
+ .get_functions_count = pinmux_generic_get_function_count,
+ .get_function_name = pinmux_generic_get_function_name,
+ .get_function_groups = pinmux_generic_get_function_groups,
+ .set_mux = lx2160a_pmux_set_mux,
+ .strict = true,
+};
+
+static int lx2160a_pmux_add_functions(struct lx2160a_pmux *pmux)
+{
+ const struct lx2160a_pmux_group *group;
+ const char **groups;
+ unsigned int i, j, k, n;
+ int ret;
+
+ for (i = 0; i < ARRAY_SIZE(lx2160a_pmux_groups); i++) {
+ group = &lx2160a_pmux_groups[i];
+ for (j = 0; j < group->nfuncs; j++) {
+ const char *name = group->funcs[j].name;
+ bool seen = false;
+
+ /* already added from an earlier group? */
+ for (k = 0; k < i && !seen; k++) {
+ const struct lx2160a_pmux_group *g =
+ &lx2160a_pmux_groups[k];
+ unsigned int l;
+
+ for (l = 0; l < g->nfuncs; l++)
+ if (!strcmp(g->funcs[l].name, name))
+ seen = true;
+ }
+ if (seen)
+ continue;
+
+ groups = devm_kcalloc(pmux->dev,
+ ARRAY_SIZE(lx2160a_pmux_groups),
+ sizeof(*groups), GFP_KERNEL);
+ if (!groups)
+ return -ENOMEM;
+ n = 0;
+ for (k = i; k < ARRAY_SIZE(lx2160a_pmux_groups); k++) {
+ const struct lx2160a_pmux_group *g =
+ &lx2160a_pmux_groups[k];
+ unsigned int l;
+
+ for (l = 0; l < g->nfuncs; l++)
+ if (!strcmp(g->funcs[l].name, name))
+ groups[n++] = g->name;
+ }
+ ret = pinmux_generic_add_function(pmux->pctl, name,
+ groups, n, NULL);
+ if (ret < 0)
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int lx2160a_pmux_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct lx2160a_pmux *pmux;
+ unsigned int i;
+ u32 val;
+ int ret;
+
+ /* The override needs the DCSR view of DCFG, mapped by fsl-guts */
+ if (!fsl_guts_pmux_override_supported())
+ return dev_err_probe(dev, -ENODEV,
+ "no RCW override through fsl-guts: the dcfg node needs its DCSR reg\n");
+
+ pmux = devm_kzalloc(dev, sizeof(*pmux), GFP_KERNEL);
+ if (!pmux)
+ return -ENOMEM;
+ pmux->dev = dev;
+
+ for (i = 0; i < ARRAY_SIZE(lx2160a_pmux_groups); i++) {
+ pmux->pins[i].number = i;
+ pmux->pins[i].name = lx2160a_pmux_groups[i].name;
+ }
+ pmux->desc.name = dev_name(dev);
+ pmux->desc.pins = pmux->pins;
+ pmux->desc.npins = ARRAY_SIZE(pmux->pins);
+ pmux->desc.pctlops = &lx2160a_pmux_pctlops;
+ pmux->desc.pmxops = &lx2160a_pmux_pmxops;
+ pmux->desc.owner = THIS_MODULE;
+
+ ret = devm_pinctrl_register_and_init(dev, &pmux->desc, pmux,
+ &pmux->pctl);
+ if (ret)
+ return dev_err_probe(dev, ret, "pinctrl registration failed\n");
+
+ for (i = 0; i < ARRAY_SIZE(lx2160a_pmux_groups); i++) {
+ ret = pinctrl_generic_add_group(pmux->pctl,
+ lx2160a_pmux_groups[i].name,
+ &pmux->pins[i].number, 1,
+ (void *)&lx2160a_pmux_groups[i]);
+ if (ret < 0)
+ return ret;
+ }
+
+ ret = lx2160a_pmux_add_functions(pmux);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < ARRAY_SIZE(lx2160a_pmux_groups); i++) {
+ u8 rcwsr = lx2160a_pmux_groups[i].rcwsr;
+
+ if (i && rcwsr == lx2160a_pmux_groups[i - 1].rcwsr)
+ continue;
+ if (!fsl_guts_pmux_read(rcwsr, &val))
+ dev_dbg(dev, "pad muxes of RCWSR%u = 0x%08x\n", rcwsr,
+ val);
+ }
+
+ return pinctrl_enable(pmux->pctl);
+}
+
+static const struct of_device_id lx2160a_pmux_of_match[] = {
+ { .compatible = "fsl,lx2160a-rcw-pinmux" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, lx2160a_pmux_of_match);
+
+static struct platform_driver lx2160a_pmux_driver = {
+ .driver = {
+ .name = "lx2160a-rcw-pinmux",
+ .of_match_table = lx2160a_pmux_of_match,
+ },
+ .probe = lx2160a_pmux_probe,
+};
+module_platform_driver(lx2160a_pmux_driver);
+
+MODULE_AUTHOR("Vincent Jardin <vjardin@free.fr>");
+MODULE_DESCRIPTION("NXP LX2160A RCW pad-mux driver");
+MODULE_LICENSE("GPL");
+MODULE_IMPORT_NS("FSL_GUTS");
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v5 5/5] arm64: dts: lx2160a: describe the pad muxes as the DCFG RCW override
2026-11-15 11:05 ` Vincent Jardin via B4 Relay
@ 2026-11-15 11:05 ` Vincent Jardin via B4 Relay
-1 siblings, 0 replies; 14+ messages in thread
From: Vincent Jardin @ 2026-11-15 11:05 UTC (permalink / raw)
To: Dong Aisheng, Fabio Estevam, Frank Li, Jacky Bai,
Pengutronix Kernel Team, NXP S32 Linux Team, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Christophe Leroy (CS GROUP), Shawn Guo, Sascha Hauer
Cc: linux-gpio, devicetree, linux-kernel, linuxppc-dev,
linux-arm-kernel, imx, Vladimir Oltean, Ioana Ciornei,
Vincent Jardin
The pad muxes are fields of the RCW: read-only in RCWSR12..14, changed
at runtime through the override registers in the DCSR view of DCFG,
which read 0 until written.
pinctrl-single on those registers, since commit 8a1365c7bbc1
("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery"),
clears every other field of the word with its first pin state:
a board whose RCW programs a non-zero pad mux loses those pads at the
first I2C probe.
Describe the pad mux as a child of the dcfg node, which gains its DCSR
view and, as on the LS1028A, the addressing of its children:
the child is at its RCWSR12 to RCWSR14 and RCWSR27 windows, one group
per RCW field, one function per encoding, driven by
fsl,lx2160a-rcw-pinmux using fsl-guts. Labels and pin node names stay,
so no consumer changes.
The pinctrl-single node goes.
Signed-off-by: Vincent Jardin <vjardin@free.fr>
---
arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi | 377 ++++++++++++++------------
1 file changed, 202 insertions(+), 175 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi
index 2085362ab0ea..b0bb7bf94405 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi
@@ -669,9 +669,209 @@ clockgen: clock-controller@1300000 {
};
dcfg: syscon@1e00000 {
- compatible = "fsl,lx2160a-dcfg", "syscon";
- reg = <0x0 0x1e00000 0x0 0x10000>;
+ compatible = "fsl,lx2160a-dcfg", "syscon", "simple-mfd";
+ reg = <0x0 0x1e00000 0x0 0x10000>,
+ <0x7 0x00100000 0x0 0x10000>;
+ reg-names = "dcfg_ccsr", "dcfg_dcsr";
+ ranges = <0x0 0x0 0x1e00000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
little-endian;
+
+ pinmux_i2crv: pinctrl@12c {
+ compatible = "fsl,lx2160a-rcw-pinmux";
+ reg = <0x12c 0xc>, <0x168 0x4>;
+
+ i2c1_pins: iic2-i2c-pins {
+ function = "i2c";
+ groups = "iic2";
+ };
+
+ gpio0_31_30_pins: iic2-gpio-pins {
+ function = "gpio";
+ groups = "iic2";
+ };
+
+ ftm0_ch10_pins: iic2-ftm-pins {
+ function = "flextimer";
+ groups = "iic2";
+ };
+
+ esdhc0_cd_wp_pins: iic2-sdhc-pins {
+ function = "sdhc";
+ groups = "iic2";
+ };
+
+ i2c2_pins: iic3-i2c-pins {
+ function = "i2c";
+ groups = "iic3";
+ };
+
+ gpio0_29_28_pins: iic3-gpio-pins {
+ function = "gpio";
+ groups = "iic3";
+ };
+
+ can0_pins: iic3-can-pins {
+ function = "can";
+ groups = "iic3";
+ };
+
+ event65_pins: iic3-event-pins {
+ function = "evt";
+ groups = "iic3";
+ };
+
+ i2c3_pins: iic4-i2c-pins {
+ function = "i2c";
+ groups = "iic4";
+ };
+
+ gpio0_27_26_pins: iic4-gpio-pins {
+ function = "gpio";
+ groups = "iic4";
+ };
+
+ can1_pins: iic4-can-pins {
+ function = "can";
+ groups = "iic4";
+ };
+
+ event87_pins: iic4-event-pins {
+ function = "evt";
+ groups = "iic4";
+ };
+
+ i2c4_pins: iic5-i2c-pins {
+ function = "i2c";
+ groups = "iic5";
+ };
+
+ gpio0_25_24_pins: iic5-gpio-pins {
+ function = "gpio";
+ groups = "iic5";
+ };
+
+ esdhc0_clksync_pins: iic5-sdhc-clk-pins {
+ function = "sdhc-clk";
+ groups = "iic5";
+ };
+
+ dspi2_miso_mosi_pins: iic5-spi3-pins {
+ function = "spi";
+ groups = "iic5";
+ };
+
+ i2c5_pins: iic6-i2c-pins {
+ function = "i2c";
+ groups = "iic6";
+ };
+
+ gpio0_23_22_pins: iic6-gpio-pins {
+ function = "gpio";
+ groups = "iic6";
+ };
+
+ esdhc1_clksync_pins: iic6-sdhc-clk-pins {
+ function = "sdhc-clk";
+ groups = "iic6";
+ };
+
+ fspi_data74_pins: xspi1-data74-pins {
+ function = "flexspi";
+ groups = "xspi1-data74";
+ };
+
+ gpio1_31_28_pins: xspi1-data74-gpio-pins {
+ function = "gpio";
+ groups = "xspi1-data74";
+ };
+
+ fspi_data30_pins: xspi1-data30-pins {
+ function = "flexspi";
+ groups = "xspi1-data30";
+ };
+
+ gpio1_27_24_pins: xspi1-data30-gpio-pins {
+ function = "gpio";
+ groups = "xspi1-data30";
+ };
+
+ fspi_dqs_sck_cs10_pins: xspi1-base-pins {
+ function = "flexspi";
+ groups = "xspi1-base";
+ };
+
+ gpio1_23_20_pins: xspi1-base-gpio-pins {
+ function = "gpio";
+ groups = "xspi1-base";
+ };
+
+ esdhc0_cmd_data30_clk_vsel_pins: sdhc1-base-sdhc-vsel-pins {
+ function = "sdhc";
+ groups = "sdhc1-base";
+ };
+
+ gpio0_21_15_pins: sdhc1-base-gpio-pins {
+ function = "gpio";
+ groups = "sdhc1-base";
+ };
+
+ dspi0_pins: sdhc1-base-spi1-pins {
+ function = "spi";
+ groups = "sdhc1-base";
+ };
+
+ esdhc0_cmd_data30_clk_dspi2_cs0_pins: sdhc1-base-sdhc-spi3-pins {
+ function = "sdhc-spi";
+ groups = "sdhc1-base";
+ };
+
+ esdhc0_cmd_data30_clk_data4_pins: sdhc1-base-sdhc-data4-pins {
+ function = "sdhc-data4";
+ groups = "sdhc1-base";
+ };
+
+ esdhc0_dir_pins: sdhc1-dir-pins {
+ function = "sdhc";
+ groups = "sdhc1-dir";
+ };
+
+ gpio0_14_12_pins: sdhc1-dir-gpio-pins {
+ function = "gpio";
+ groups = "sdhc1-dir";
+ };
+
+ dspi2_cs31_pins: sdhc1-dir-spi3-pins {
+ function = "spi";
+ groups = "sdhc1-dir";
+ };
+
+ esdhc0_data75_pins: sdhc1-dir-sdhc-pins {
+ function = "sdhc-data";
+ groups = "sdhc1-dir";
+ };
+
+ gpio1_18_15_pins: iic8-iic7-gpio-pins {
+ function = "gpio";
+ groups = "sdhc2-data74";
+ };
+
+ i2c6_i2c7_pins: iic8-iic7-i2c-pins {
+ function = "i2c";
+ groups = "sdhc2-data74";
+ };
+
+ i2c0_pins: iic1-i2c-pins {
+ function = "i2c";
+ groups = "iic1";
+ };
+
+ gpio0_3_2_pins: iic1-gpio-pins {
+ function = "gpio";
+ groups = "iic1";
+ };
+ };
};
sfp: efuse@1e80000 {
@@ -1531,179 +1731,6 @@ pcs18: ethernet-phy@0 {
};
};
- pinmux_i2crv: pinmux@70010012c {
- compatible = "pinctrl-single";
- reg = <0x00000007 0x0010012c 0x0 0xc>;
- #address-cells = <1>;
- #size-cells = <0>;
- #pinctrl-cells = <2>;
- pinctrl-single,bit-per-mux;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x7>;
-
- /* RCWSR12 */
- i2c1_pins: iic2-i2c-pins {
- pinctrl-single,bits = <0x0 0x0 0x7>;
- };
-
- gpio0_31_30_pins: iic2-gpio-pins {
- pinctrl-single,bits = <0x0 0x1 0x7>;
- };
-
- ftm0_ch10_pins: iic2-ftm-pins {
- pinctrl-single,bits = <0x0 0x2 0x7>;
- };
-
- esdhc0_cd_wp_pins: iic2-sdhc-pins {
- pinctrl-single,bits = <0x0 0x6 0x7>;
- };
-
- i2c2_pins: iic3-i2c-pins {
- pinctrl-single,bits = <0x0 0x0 (0x7 << 3)>;
- };
-
- gpio0_29_28_pins: iic3-gpio-pins {
- pinctrl-single,bits = <0x0 (0x1 << 3) (0x7 << 3)>;
- };
-
- can0_pins: iic3-can-pins {
- pinctrl-single,bits = <0x0 (0x2 << 3) (0x7 << 3)>;
- };
-
- event65_pins: iic3-event-pins {
- pinctrl-single,bits = <0x0 (0x6 << 3) (0x7 << 3)>;
- };
-
- i2c3_pins: iic4-i2c-pins {
- pinctrl-single,bits = <0x0 0x0 (0x7 << 6)>;
- };
-
- gpio0_27_26_pins: iic4-gpio-pins {
- pinctrl-single,bits = <0x0 (0x1 << 6) (0x7 << 6)>;
- };
-
- can1_pins: iic4-can-pins {
- pinctrl-single,bits = <0x0 (0x2 << 6) (0x7 << 6)>;
- };
-
- event87_pins: iic4-event-pins {
- pinctrl-single,bits = <0x0 (0x6 << 6) (0x7 << 6)>;
- };
-
- i2c4_pins: iic5-i2c-pins {
- pinctrl-single,bits = <0x0 0x0 (0x7 << 9)>;
- };
-
- gpio0_25_24_pins: iic5-gpio-pins {
- pinctrl-single,bits = <0x0 (0x1 << 9) (0x7 << 9)>;
- };
-
- esdhc0_clksync_pins: iic5-sdhc-clk-pins {
- pinctrl-single,bits = <0x0 (0x2 << 9) (0x7 << 9)>;
- };
-
- dspi2_miso_mosi_pins: iic5-spi3-pins {
- pinctrl-single,bits = <0x0 (0x3 << 9) (0x7 << 9)>;
- };
-
- i2c5_pins: iic6-i2c-pins {
- pinctrl-single,bits = <0x0 0x0 (0x7 << 12)>;
- };
-
- gpio0_23_22_pins: iic6-gpio-pins {
- pinctrl-single,bits = <0x0 (0x1 << 12) (0x7 << 12)>;
- };
-
- esdhc1_clksync_pins: iic6-sdhc-clk-pins {
- pinctrl-single,bits = <0x0 (0x2 << 12) (0x7 << 12)>;
- };
-
- fspi_data74_pins: xspi1-data74-pins {
- pinctrl-single,bits = <0x0 0x0 (0x7 << 15)>;
- };
-
- gpio1_31_28_pins: xspi1-data74-gpio-pins {
- pinctrl-single,bits = <0x0 (0x1 << 15) (0x7 << 15)>;
- };
-
- fspi_data30_pins: xspi1-data30-pins {
- pinctrl-single,bits = <0x0 0x0 (0x7 << 18)>;
- };
-
- gpio1_27_24_pins: xspi1-data30-gpio-pins {
- pinctrl-single,bits = <0x0 (0x1 << 18) (0x7 << 18)>;
- };
-
- fspi_dqs_sck_cs10_pins: xspi1-base-pins {
- pinctrl-single,bits = <0x0 0x0 (0x7 << 21)>;
- };
-
- gpio1_23_20_pins: xspi1-base-gpio-pins {
- pinctrl-single,bits = <0x0 (0x1 << 21) (0x7 << 21)>;
- };
-
- esdhc0_cmd_data30_clk_vsel_pins: sdhc1-base-sdhc-vsel-pins {
- pinctrl-single,bits = <0x0 0x0 (0x7 << 24)>;
- };
-
- gpio0_21_15_pins: sdhc1-base-gpio-pins {
- pinctrl-single,bits = <0x0 (0x1 << 24) (0x7 << 24)>;
- };
-
- dspi0_pins: sdhc1-base-spi1-pins {
- pinctrl-single,bits = <0x0 (0x2 << 24) (0x7 << 24)>;
- };
-
- esdhc0_cmd_data30_clk_dspi2_cs0_pins: sdhc1-base-sdhc-spi3-pins {
- pinctrl-single,bits = <0x0 (0x3 << 24) (0x7 << 24)>;
- };
-
- esdhc0_cmd_data30_clk_data4_pins: sdhc1-base-sdhc-data4-pins {
- pinctrl-single,bits = <0x0 (0x4 << 24) (0x7 << 24)>;
- };
-
- esdhc0_dir_pins: sdhc1-dir-pins {
- pinctrl-single,bits = <0x0 0x0 (0x7 << 27)>;
- };
-
- gpio0_14_12_pins: sdhc1-dir-gpio-pins {
- pinctrl-single,bits = <0x0 (0x1 << 27) (0x7 << 27)>;
- };
-
- dspi2_cs31_pins: sdhc1-dir-spi3-pins {
- pinctrl-single,bits = <0x0 (0x3 << 27) (0x7 << 27)>;
- };
-
- esdhc0_data75_pins: sdhc1-dir-sdhc-pins {
- pinctrl-single,bits = <0x0 (0x4 << 27) (0x7 << 27)>;
- };
-
- /* RCWSR13 */
- gpio1_18_15_pins: iic8-iic7-gpio-pins {
- pinctrl-single,bits = <0x4 0x1 0x7>;
- };
-
- i2c6_i2c7_pins: iic8-iic7-i2c-pins {
- pinctrl-single,bits = <0x4 0x2 0x7>;
- };
-
- /* RCWSR14 */
- /*
- * IIC1_PMUX is a single bit at RCWSR14[10], but bit-per-mux
- * uses the mask for the field to clear before applying the
- * value.
- * So bits 11 and 12, which are reserved, are written as 0
- * on every mux switch, it is harmless.
- */
- i2c0_pins: iic1-i2c-pins {
- pinctrl-single,bits = <0x8 0x0 (0x7 << 10)>;
- };
-
- gpio0_3_2_pins: iic1-gpio-pins {
- pinctrl-single,bits = <0x8 (0x1 << 10) (0x7 << 10)>;
- };
- };
-
fsl_mc: fsl-mc@80c000000 {
compatible = "fsl,qoriq-mc";
reg = <0x00000008 0x0c000000 0 0x40>,
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v5 5/5] arm64: dts: lx2160a: describe the pad muxes as the DCFG RCW override
@ 2026-11-15 11:05 ` Vincent Jardin via B4 Relay
0 siblings, 0 replies; 14+ messages in thread
From: Vincent Jardin via B4 Relay @ 2026-11-15 11:05 UTC (permalink / raw)
To: Dong Aisheng, Fabio Estevam, Frank Li, Jacky Bai,
Pengutronix Kernel Team, NXP S32 Linux Team, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Christophe Leroy (CS GROUP), Shawn Guo, Sascha Hauer
Cc: linux-gpio, devicetree, linux-kernel, linuxppc-dev,
linux-arm-kernel, imx, Vladimir Oltean, Ioana Ciornei,
Vincent Jardin
From: Vincent Jardin <vjardin@free.fr>
The pad muxes are fields of the RCW: read-only in RCWSR12..14, changed
at runtime through the override registers in the DCSR view of DCFG,
which read 0 until written.
pinctrl-single on those registers, since commit 8a1365c7bbc1
("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery"),
clears every other field of the word with its first pin state:
a board whose RCW programs a non-zero pad mux loses those pads at the
first I2C probe.
Describe the pad mux as a child of the dcfg node, which gains its DCSR
view and, as on the LS1028A, the addressing of its children:
the child is at its RCWSR12 to RCWSR14 and RCWSR27 windows, one group
per RCW field, one function per encoding, driven by
fsl,lx2160a-rcw-pinmux using fsl-guts. Labels and pin node names stay,
so no consumer changes.
The pinctrl-single node goes.
Signed-off-by: Vincent Jardin <vjardin@free.fr>
---
arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi | 377 ++++++++++++++------------
1 file changed, 202 insertions(+), 175 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi
index 2085362ab0ea..b0bb7bf94405 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi
@@ -669,9 +669,209 @@ clockgen: clock-controller@1300000 {
};
dcfg: syscon@1e00000 {
- compatible = "fsl,lx2160a-dcfg", "syscon";
- reg = <0x0 0x1e00000 0x0 0x10000>;
+ compatible = "fsl,lx2160a-dcfg", "syscon", "simple-mfd";
+ reg = <0x0 0x1e00000 0x0 0x10000>,
+ <0x7 0x00100000 0x0 0x10000>;
+ reg-names = "dcfg_ccsr", "dcfg_dcsr";
+ ranges = <0x0 0x0 0x1e00000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
little-endian;
+
+ pinmux_i2crv: pinctrl@12c {
+ compatible = "fsl,lx2160a-rcw-pinmux";
+ reg = <0x12c 0xc>, <0x168 0x4>;
+
+ i2c1_pins: iic2-i2c-pins {
+ function = "i2c";
+ groups = "iic2";
+ };
+
+ gpio0_31_30_pins: iic2-gpio-pins {
+ function = "gpio";
+ groups = "iic2";
+ };
+
+ ftm0_ch10_pins: iic2-ftm-pins {
+ function = "flextimer";
+ groups = "iic2";
+ };
+
+ esdhc0_cd_wp_pins: iic2-sdhc-pins {
+ function = "sdhc";
+ groups = "iic2";
+ };
+
+ i2c2_pins: iic3-i2c-pins {
+ function = "i2c";
+ groups = "iic3";
+ };
+
+ gpio0_29_28_pins: iic3-gpio-pins {
+ function = "gpio";
+ groups = "iic3";
+ };
+
+ can0_pins: iic3-can-pins {
+ function = "can";
+ groups = "iic3";
+ };
+
+ event65_pins: iic3-event-pins {
+ function = "evt";
+ groups = "iic3";
+ };
+
+ i2c3_pins: iic4-i2c-pins {
+ function = "i2c";
+ groups = "iic4";
+ };
+
+ gpio0_27_26_pins: iic4-gpio-pins {
+ function = "gpio";
+ groups = "iic4";
+ };
+
+ can1_pins: iic4-can-pins {
+ function = "can";
+ groups = "iic4";
+ };
+
+ event87_pins: iic4-event-pins {
+ function = "evt";
+ groups = "iic4";
+ };
+
+ i2c4_pins: iic5-i2c-pins {
+ function = "i2c";
+ groups = "iic5";
+ };
+
+ gpio0_25_24_pins: iic5-gpio-pins {
+ function = "gpio";
+ groups = "iic5";
+ };
+
+ esdhc0_clksync_pins: iic5-sdhc-clk-pins {
+ function = "sdhc-clk";
+ groups = "iic5";
+ };
+
+ dspi2_miso_mosi_pins: iic5-spi3-pins {
+ function = "spi";
+ groups = "iic5";
+ };
+
+ i2c5_pins: iic6-i2c-pins {
+ function = "i2c";
+ groups = "iic6";
+ };
+
+ gpio0_23_22_pins: iic6-gpio-pins {
+ function = "gpio";
+ groups = "iic6";
+ };
+
+ esdhc1_clksync_pins: iic6-sdhc-clk-pins {
+ function = "sdhc-clk";
+ groups = "iic6";
+ };
+
+ fspi_data74_pins: xspi1-data74-pins {
+ function = "flexspi";
+ groups = "xspi1-data74";
+ };
+
+ gpio1_31_28_pins: xspi1-data74-gpio-pins {
+ function = "gpio";
+ groups = "xspi1-data74";
+ };
+
+ fspi_data30_pins: xspi1-data30-pins {
+ function = "flexspi";
+ groups = "xspi1-data30";
+ };
+
+ gpio1_27_24_pins: xspi1-data30-gpio-pins {
+ function = "gpio";
+ groups = "xspi1-data30";
+ };
+
+ fspi_dqs_sck_cs10_pins: xspi1-base-pins {
+ function = "flexspi";
+ groups = "xspi1-base";
+ };
+
+ gpio1_23_20_pins: xspi1-base-gpio-pins {
+ function = "gpio";
+ groups = "xspi1-base";
+ };
+
+ esdhc0_cmd_data30_clk_vsel_pins: sdhc1-base-sdhc-vsel-pins {
+ function = "sdhc";
+ groups = "sdhc1-base";
+ };
+
+ gpio0_21_15_pins: sdhc1-base-gpio-pins {
+ function = "gpio";
+ groups = "sdhc1-base";
+ };
+
+ dspi0_pins: sdhc1-base-spi1-pins {
+ function = "spi";
+ groups = "sdhc1-base";
+ };
+
+ esdhc0_cmd_data30_clk_dspi2_cs0_pins: sdhc1-base-sdhc-spi3-pins {
+ function = "sdhc-spi";
+ groups = "sdhc1-base";
+ };
+
+ esdhc0_cmd_data30_clk_data4_pins: sdhc1-base-sdhc-data4-pins {
+ function = "sdhc-data4";
+ groups = "sdhc1-base";
+ };
+
+ esdhc0_dir_pins: sdhc1-dir-pins {
+ function = "sdhc";
+ groups = "sdhc1-dir";
+ };
+
+ gpio0_14_12_pins: sdhc1-dir-gpio-pins {
+ function = "gpio";
+ groups = "sdhc1-dir";
+ };
+
+ dspi2_cs31_pins: sdhc1-dir-spi3-pins {
+ function = "spi";
+ groups = "sdhc1-dir";
+ };
+
+ esdhc0_data75_pins: sdhc1-dir-sdhc-pins {
+ function = "sdhc-data";
+ groups = "sdhc1-dir";
+ };
+
+ gpio1_18_15_pins: iic8-iic7-gpio-pins {
+ function = "gpio";
+ groups = "sdhc2-data74";
+ };
+
+ i2c6_i2c7_pins: iic8-iic7-i2c-pins {
+ function = "i2c";
+ groups = "sdhc2-data74";
+ };
+
+ i2c0_pins: iic1-i2c-pins {
+ function = "i2c";
+ groups = "iic1";
+ };
+
+ gpio0_3_2_pins: iic1-gpio-pins {
+ function = "gpio";
+ groups = "iic1";
+ };
+ };
};
sfp: efuse@1e80000 {
@@ -1531,179 +1731,6 @@ pcs18: ethernet-phy@0 {
};
};
- pinmux_i2crv: pinmux@70010012c {
- compatible = "pinctrl-single";
- reg = <0x00000007 0x0010012c 0x0 0xc>;
- #address-cells = <1>;
- #size-cells = <0>;
- #pinctrl-cells = <2>;
- pinctrl-single,bit-per-mux;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x7>;
-
- /* RCWSR12 */
- i2c1_pins: iic2-i2c-pins {
- pinctrl-single,bits = <0x0 0x0 0x7>;
- };
-
- gpio0_31_30_pins: iic2-gpio-pins {
- pinctrl-single,bits = <0x0 0x1 0x7>;
- };
-
- ftm0_ch10_pins: iic2-ftm-pins {
- pinctrl-single,bits = <0x0 0x2 0x7>;
- };
-
- esdhc0_cd_wp_pins: iic2-sdhc-pins {
- pinctrl-single,bits = <0x0 0x6 0x7>;
- };
-
- i2c2_pins: iic3-i2c-pins {
- pinctrl-single,bits = <0x0 0x0 (0x7 << 3)>;
- };
-
- gpio0_29_28_pins: iic3-gpio-pins {
- pinctrl-single,bits = <0x0 (0x1 << 3) (0x7 << 3)>;
- };
-
- can0_pins: iic3-can-pins {
- pinctrl-single,bits = <0x0 (0x2 << 3) (0x7 << 3)>;
- };
-
- event65_pins: iic3-event-pins {
- pinctrl-single,bits = <0x0 (0x6 << 3) (0x7 << 3)>;
- };
-
- i2c3_pins: iic4-i2c-pins {
- pinctrl-single,bits = <0x0 0x0 (0x7 << 6)>;
- };
-
- gpio0_27_26_pins: iic4-gpio-pins {
- pinctrl-single,bits = <0x0 (0x1 << 6) (0x7 << 6)>;
- };
-
- can1_pins: iic4-can-pins {
- pinctrl-single,bits = <0x0 (0x2 << 6) (0x7 << 6)>;
- };
-
- event87_pins: iic4-event-pins {
- pinctrl-single,bits = <0x0 (0x6 << 6) (0x7 << 6)>;
- };
-
- i2c4_pins: iic5-i2c-pins {
- pinctrl-single,bits = <0x0 0x0 (0x7 << 9)>;
- };
-
- gpio0_25_24_pins: iic5-gpio-pins {
- pinctrl-single,bits = <0x0 (0x1 << 9) (0x7 << 9)>;
- };
-
- esdhc0_clksync_pins: iic5-sdhc-clk-pins {
- pinctrl-single,bits = <0x0 (0x2 << 9) (0x7 << 9)>;
- };
-
- dspi2_miso_mosi_pins: iic5-spi3-pins {
- pinctrl-single,bits = <0x0 (0x3 << 9) (0x7 << 9)>;
- };
-
- i2c5_pins: iic6-i2c-pins {
- pinctrl-single,bits = <0x0 0x0 (0x7 << 12)>;
- };
-
- gpio0_23_22_pins: iic6-gpio-pins {
- pinctrl-single,bits = <0x0 (0x1 << 12) (0x7 << 12)>;
- };
-
- esdhc1_clksync_pins: iic6-sdhc-clk-pins {
- pinctrl-single,bits = <0x0 (0x2 << 12) (0x7 << 12)>;
- };
-
- fspi_data74_pins: xspi1-data74-pins {
- pinctrl-single,bits = <0x0 0x0 (0x7 << 15)>;
- };
-
- gpio1_31_28_pins: xspi1-data74-gpio-pins {
- pinctrl-single,bits = <0x0 (0x1 << 15) (0x7 << 15)>;
- };
-
- fspi_data30_pins: xspi1-data30-pins {
- pinctrl-single,bits = <0x0 0x0 (0x7 << 18)>;
- };
-
- gpio1_27_24_pins: xspi1-data30-gpio-pins {
- pinctrl-single,bits = <0x0 (0x1 << 18) (0x7 << 18)>;
- };
-
- fspi_dqs_sck_cs10_pins: xspi1-base-pins {
- pinctrl-single,bits = <0x0 0x0 (0x7 << 21)>;
- };
-
- gpio1_23_20_pins: xspi1-base-gpio-pins {
- pinctrl-single,bits = <0x0 (0x1 << 21) (0x7 << 21)>;
- };
-
- esdhc0_cmd_data30_clk_vsel_pins: sdhc1-base-sdhc-vsel-pins {
- pinctrl-single,bits = <0x0 0x0 (0x7 << 24)>;
- };
-
- gpio0_21_15_pins: sdhc1-base-gpio-pins {
- pinctrl-single,bits = <0x0 (0x1 << 24) (0x7 << 24)>;
- };
-
- dspi0_pins: sdhc1-base-spi1-pins {
- pinctrl-single,bits = <0x0 (0x2 << 24) (0x7 << 24)>;
- };
-
- esdhc0_cmd_data30_clk_dspi2_cs0_pins: sdhc1-base-sdhc-spi3-pins {
- pinctrl-single,bits = <0x0 (0x3 << 24) (0x7 << 24)>;
- };
-
- esdhc0_cmd_data30_clk_data4_pins: sdhc1-base-sdhc-data4-pins {
- pinctrl-single,bits = <0x0 (0x4 << 24) (0x7 << 24)>;
- };
-
- esdhc0_dir_pins: sdhc1-dir-pins {
- pinctrl-single,bits = <0x0 0x0 (0x7 << 27)>;
- };
-
- gpio0_14_12_pins: sdhc1-dir-gpio-pins {
- pinctrl-single,bits = <0x0 (0x1 << 27) (0x7 << 27)>;
- };
-
- dspi2_cs31_pins: sdhc1-dir-spi3-pins {
- pinctrl-single,bits = <0x0 (0x3 << 27) (0x7 << 27)>;
- };
-
- esdhc0_data75_pins: sdhc1-dir-sdhc-pins {
- pinctrl-single,bits = <0x0 (0x4 << 27) (0x7 << 27)>;
- };
-
- /* RCWSR13 */
- gpio1_18_15_pins: iic8-iic7-gpio-pins {
- pinctrl-single,bits = <0x4 0x1 0x7>;
- };
-
- i2c6_i2c7_pins: iic8-iic7-i2c-pins {
- pinctrl-single,bits = <0x4 0x2 0x7>;
- };
-
- /* RCWSR14 */
- /*
- * IIC1_PMUX is a single bit at RCWSR14[10], but bit-per-mux
- * uses the mask for the field to clear before applying the
- * value.
- * So bits 11 and 12, which are reserved, are written as 0
- * on every mux switch, it is harmless.
- */
- i2c0_pins: iic1-i2c-pins {
- pinctrl-single,bits = <0x8 0x0 (0x7 << 10)>;
- };
-
- gpio0_3_2_pins: iic1-gpio-pins {
- pinctrl-single,bits = <0x8 (0x1 << 10) (0x7 << 10)>;
- };
- };
-
fsl_mc: fsl-mc@80c000000 {
compatible = "fsl,qoriq-mc";
reg = <0x00000008 0x0c000000 0 0x40>,
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v5 4/5] pinctrl: freescale: add the LX2160A RCW pad-mux driver
2026-11-15 11:05 ` Vincent Jardin via B4 Relay
(?)
@ 2026-11-15 11:31 ` Vladimir Oltean
2026-11-15 11:45 ` Vincent Jardin
-1 siblings, 1 reply; 14+ messages in thread
From: Vladimir Oltean @ 2026-11-15 11:31 UTC (permalink / raw)
To: vjardin
Cc: Dong Aisheng, Fabio Estevam, Frank Li, Jacky Bai,
Pengutronix Kernel Team, NXP S32 Linux Team, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Christophe Leroy (CS GROUP), Shawn Guo, Sascha Hauer, linux-gpio,
devicetree, linux-kernel, linuxppc-dev, linux-arm-kernel, imx,
Ioana Ciornei
Hi Vincent,
On Sun, Nov 15, 2026 at 12:05:40PM +0100, Vincent Jardin via B4 Relay wrote:
> From: Vincent Jardin <vjardin@free.fr>
>
> The LX2160A muxes its IIC, XSPI, SDHC, UART, IRQ and EVT pads from
> fields of the RCW, read-only in RCWSR12..14 of DCFG and changed at
> runtime through the same fields of the override registers in its DCSR
> view, which read 0 until written.
>
> Since commit 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c
> gpio to support bus recovery") Linux drives them with pinctrl-single on
> the override registers, so its first pin state clears every other field
> of the word: a board whose RCW programs a non-zero pad mux loses those
> pads at the first I2C probe.
>
> Add a driver for the pad mux as a child of the DCFG node: the fields
> of RCWSR12..14, the EC1, EC2, USB_EXT, GTX_CLK and SDHC1_DS ones of
> RCWSR27, and their encoding.
> Then pin states select them with the generic function and groups
> properties, and every change goes through the RCW override
> of fsl-guts, which reads the status register, writes the override and
> waits for the status register to follow.
>
> Signed-off-by: Vincent Jardin <vjardin@free.fr>
> ---
Did you see my feedback on this patch for v4? Comments?
https://lore.kernel.org/lkml/avjaK3cOj3iQ6G6w@skbuf/
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v5 4/5] pinctrl: freescale: add the LX2160A RCW pad-mux driver
2026-11-15 11:31 ` Vladimir Oltean
@ 2026-11-15 11:45 ` Vincent Jardin
0 siblings, 0 replies; 14+ messages in thread
From: Vincent Jardin @ 2026-11-15 11:45 UTC (permalink / raw)
To: Vladimir Oltean
Cc: Dong Aisheng, Fabio Estevam, Frank Li, Jacky Bai,
Pengutronix Kernel Team, NXP S32 Linux Team, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Christophe Leroy (CS GROUP), Shawn Guo, Sascha Hauer, linux-gpio,
devicetree, linux-kernel, linuxppc-dev, linux-arm-kernel, imx,
Ioana Ciornei
Hi Vladimir,
> Did you see my feedback on this patch for v4? Comments?
> https://lore.kernel.org/lkml/avjaK3cOj3iQ6G6w@skbuf/
No !, for some reasons, I did miss it..., thanks.
I can prepare a new serie to make it a bit more generic,
but I'd need NXP/your reviews for those CPUs, since I
cannot test.
It seems to be quite easy to update, I'll just
run some basic checks.
best regards,
Vincent
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2026-11-15 11:45 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-11-15 11:05 [PATCH v5 0/5] lx2160a: change the pad muxes through the RCW override Vincent Jardin
2026-11-15 11:05 ` Vincent Jardin via B4 Relay
2026-11-15 11:05 ` [PATCH v5 1/5] dt-bindings: pinctrl: add the NXP LX2160A RCW pad mux Vincent Jardin
2026-11-15 11:05 ` Vincent Jardin via B4 Relay
2026-11-15 11:05 ` [PATCH v5 2/5] dt-bindings: soc: fsl: layerscape-dcfg: add the LX2160A pad-mux child Vincent Jardin
2026-11-15 11:05 ` Vincent Jardin via B4 Relay
2026-11-15 11:05 ` [PATCH v5 3/5] soc: fsl: guts: add the RCW override of the pad muxes Vincent Jardin
2026-11-15 11:05 ` Vincent Jardin via B4 Relay
2026-11-15 11:05 ` [PATCH v5 4/5] pinctrl: freescale: add the LX2160A RCW pad-mux driver Vincent Jardin
2026-11-15 11:05 ` Vincent Jardin via B4 Relay
2026-11-15 11:31 ` Vladimir Oltean
2026-11-15 11:45 ` Vincent Jardin
2026-11-15 11:05 ` [PATCH v5 5/5] arm64: dts: lx2160a: describe the pad muxes as the DCFG RCW override Vincent Jardin
2026-11-15 11:05 ` Vincent Jardin via B4 Relay
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.