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From: Krzysztof Kozlowski <krzk@kernel.org>
To: Michal Simek <michal.simek@amd.com>,
	linux-kernel@vger.kernel.org, monstr@monstr.eu,
	michal.simek@xilinx.com, git@xilinx.com
Cc: Conor Dooley <conor+dt@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Rob Herring <robh@kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
	<devicetree@vger.kernel.org>
Subject: Re: [PATCH] dt-bindings: interrupt-controller: Add Xilinx INTC binding
Date: Tue, 22 Jul 2025 09:17:35 +0200	[thread overview]
Message-ID: <b30f00c3-9062-4d19-8088-5fc5e951eb5d@kernel.org> (raw)
In-Reply-To: <6ddaf6f1e3748cdeda2e2e32ee69343a06c60dcb.1753166980.git.michal.simek@amd.com>

On 22/07/2025 08:49, Michal Simek wrote:
> Add description for AMD/Xilinx interrupt controller.
> IP acts as primary interrupt controller on Microblaze systems or can be
> used as secondary interrupt controller on ARM based systems like Zynq,
> ZynqMP, Versal or Versal Gen 2. Also as secondary interrupt controller on
> Microblaze-V (Risc-V) systems.
> 
> Over the years IP exists in multiple variants based on attached bus as OPB,
> PLB or AXI that's why generic filename is used.
> 
> Signed-off-by: Michal Simek <michal.simek@amd.com>
> ---
> 
> https://docs.amd.com/v/u/en-US/pg099-axi-intc


We usually do not take bindings without users, that's why bindings patch
is always part of some other patchset. Commit msg also did not clarify
the usecase here (or exception).

Best regards,
Krzysztof

  reply	other threads:[~2025-07-22  7:17 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-22  6:49 [PATCH] dt-bindings: interrupt-controller: Add Xilinx INTC binding Michal Simek
2025-07-22  7:17 ` Krzysztof Kozlowski [this message]
2025-07-22  7:32   ` Michal Simek
2025-07-22  7:37     ` Krzysztof Kozlowski
2025-07-22  7:40 ` Krzysztof Kozlowski
2025-07-22  8:12   ` Michal Simek

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