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From: Jiri Slaby <jirislaby@kernel.org>
To: Bin Meng <bmeng@tinylab.org>,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-serial@vger.kernel.org
Cc: Albert Ou <aou@eecs.berkeley.edu>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>
Subject: Re: [PATCH 1/2] serial: Adapt Arm semihosting earlycon driver to RISC-V
Date: Tue, 6 Dec 2022 07:35:03 +0100	[thread overview]
Message-ID: <b3aff238-c473-e587-dd04-cc5ef4517722@kernel.org> (raw)
In-Reply-To: <20221205050038.195746-1-bmeng@tinylab.org>

On 05. 12. 22, 6:00, Bin Meng wrote:
...
> --- a/drivers/tty/serial/earlycon-arm-semihost.c
> +++ b/drivers/tty/serial/earlycon-arm-semihost.c
...
> @@ -23,7 +27,18 @@
>    */
>   static void smh_putc(struct uart_port *port, unsigned char c)
>   {
> -#ifdef CONFIG_ARM64
> +#if defined(CONFIG_RISCV)
> +	asm volatile("addi    a1, %0, 0\n"
> +		     "addi    a0, zero, 3\n"
> +		     ".balign 16\n"
> +		     ".option push\n"
> +		     ".option norvc\n"
> +		     "slli    zero, zero, 0x1f\n"
> +		     "ebreak\n"
> +		     "srai    zero, zero, 0x7\n"
> +		     ".option pop\n"
> +		     : : "r" (&c) : "a0", "a1", "memory");
> +#elif defined(CONFIG_ARM64)
>   	asm volatile("mov  x1, %0\n"
>   		     "mov  x0, #3\n"
>   		     "hlt  0xf000\n"

Hmm, can we implement all those smh_putc() variants in respective 
arch/*/include/semihost.h instead?

thanks,
-- 
js
suse labs


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WARNING: multiple messages have this Message-ID (diff)
From: Jiri Slaby <jirislaby@kernel.org>
To: Bin Meng <bmeng@tinylab.org>,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-serial@vger.kernel.org
Cc: Albert Ou <aou@eecs.berkeley.edu>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>
Subject: Re: [PATCH 1/2] serial: Adapt Arm semihosting earlycon driver to RISC-V
Date: Tue, 6 Dec 2022 07:35:03 +0100	[thread overview]
Message-ID: <b3aff238-c473-e587-dd04-cc5ef4517722@kernel.org> (raw)
In-Reply-To: <20221205050038.195746-1-bmeng@tinylab.org>

On 05. 12. 22, 6:00, Bin Meng wrote:
...
> --- a/drivers/tty/serial/earlycon-arm-semihost.c
> +++ b/drivers/tty/serial/earlycon-arm-semihost.c
...
> @@ -23,7 +27,18 @@
>    */
>   static void smh_putc(struct uart_port *port, unsigned char c)
>   {
> -#ifdef CONFIG_ARM64
> +#if defined(CONFIG_RISCV)
> +	asm volatile("addi    a1, %0, 0\n"
> +		     "addi    a0, zero, 3\n"
> +		     ".balign 16\n"
> +		     ".option push\n"
> +		     ".option norvc\n"
> +		     "slli    zero, zero, 0x1f\n"
> +		     "ebreak\n"
> +		     "srai    zero, zero, 0x7\n"
> +		     ".option pop\n"
> +		     : : "r" (&c) : "a0", "a1", "memory");
> +#elif defined(CONFIG_ARM64)
>   	asm volatile("mov  x1, %0\n"
>   		     "mov  x0, #3\n"
>   		     "hlt  0xf000\n"

Hmm, can we implement all those smh_putc() variants in respective 
arch/*/include/semihost.h instead?

thanks,
-- 
js
suse labs


  parent reply	other threads:[~2022-12-06  6:35 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-05  5:00 [PATCH 1/2] serial: Adapt Arm semihosting earlycon driver to RISC-V Bin Meng
2022-12-05  5:00 ` Bin Meng
2022-12-05  5:00 ` [PATCH 2/2] serial: Rename earlycon semihost driver Bin Meng
2022-12-05  5:00   ` Bin Meng
2022-12-06  6:35 ` Jiri Slaby [this message]
2022-12-06  6:35   ` [PATCH 1/2] serial: Adapt Arm semihosting earlycon driver to RISC-V Jiri Slaby
2022-12-06 14:23   ` Bin Meng
2022-12-06 14:23     ` Bin Meng

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