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From: David Laight <David.Laight@ACULAB.COM>
To: 'Arnd Bergmann' <arnd@arndb.de>,
	Jisheng Zhang <jszhang@kernel.org>,
	Andreas Schwab <schwab@suse.de>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	"linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH 2/4] riscv: uaccess: use input constraints for ptr of __put_user
Date: Fri, 28 Jun 2024 15:36:17 +0000	[thread overview]
Message-ID: <b4d15c17ed684f5ab3cf89fda9f73618@AcuMS.aculab.com> (raw)
In-Reply-To: <dcf9574a-0f1b-4131-befd-39f47d4f9002@app.fastmail.com>

From: Arnd Bergmann
> Sent: 26 June 2024 15:25
...
> If you just copy from the arm64 version that uses an
> "r"(address) constraint instead of the "m"(*address)
> version, it should be fine for any user space access.

Arm certainly has 'reg+offset' addressing and I'd have thought
the RISC-V would have it as well.

I'd guess that the compiler also knows when the offset is too big.

Probably noticeable when code is accessing structures in user memory.

OTOH I can't remember if "m" implies a memory clobber?
For user copies the memory clobber isn't needed and not having it
may well allow better instruction scheduling.

	David

-
Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK
Registration No: 1397386 (Wales)


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WARNING: multiple messages have this Message-ID (diff)
From: David Laight <David.Laight@ACULAB.COM>
To: 'Arnd Bergmann' <arnd@arndb.de>,
	Jisheng Zhang <jszhang@kernel.org>,
	Andreas Schwab <schwab@suse.de>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	"linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH 2/4] riscv: uaccess: use input constraints for ptr of __put_user
Date: Fri, 28 Jun 2024 15:36:17 +0000	[thread overview]
Message-ID: <b4d15c17ed684f5ab3cf89fda9f73618@AcuMS.aculab.com> (raw)
In-Reply-To: <dcf9574a-0f1b-4131-befd-39f47d4f9002@app.fastmail.com>

From: Arnd Bergmann
> Sent: 26 June 2024 15:25
...
> If you just copy from the arm64 version that uses an
> "r"(address) constraint instead of the "m"(*address)
> version, it should be fine for any user space access.

Arm certainly has 'reg+offset' addressing and I'd have thought
the RISC-V would have it as well.

I'd guess that the compiler also knows when the offset is too big.

Probably noticeable when code is accessing structures in user memory.

OTOH I can't remember if "m" implies a memory clobber?
For user copies the memory clobber isn't needed and not having it
may well allow better instruction scheduling.

	David

-
Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK
Registration No: 1397386 (Wales)


  parent reply	other threads:[~2024-06-28 15:37 UTC|newest]

Thread overview: 64+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-25  4:04 [PATCH 0/4] riscv: uaccess: optimizations Jisheng Zhang
2024-06-25  4:04 ` Jisheng Zhang
2024-06-25  4:04 ` [PATCH 1/4] riscv: implement user_access_begin and families Jisheng Zhang
2024-06-25  4:04   ` Jisheng Zhang
2024-06-26 23:38   ` Cyril Bur
2024-06-26 23:38     ` Cyril Bur
2024-06-25  4:04 ` [PATCH 2/4] riscv: uaccess: use input constraints for ptr of __put_user Jisheng Zhang
2024-06-25  4:04   ` Jisheng Zhang
2024-06-25  5:54   ` Arnd Bergmann
2024-06-25  5:54     ` Arnd Bergmann
2024-06-26 12:32     ` Jisheng Zhang
2024-06-26 12:32       ` Jisheng Zhang
2024-06-26 12:49       ` Jisheng Zhang
2024-06-26 12:49         ` Jisheng Zhang
2024-06-26 13:18         ` Jisheng Zhang
2024-06-26 13:18           ` Jisheng Zhang
2024-06-26 13:35         ` Andreas Schwab
2024-06-26 13:35           ` Andreas Schwab
2024-06-26 13:54           ` Jisheng Zhang
2024-06-26 13:54             ` Jisheng Zhang
2024-06-26 13:12   ` Andreas Schwab
2024-06-26 13:12     ` Andreas Schwab
2024-06-26 13:12     ` Jisheng Zhang
2024-06-26 13:12       ` Jisheng Zhang
2024-06-26 14:25       ` Arnd Bergmann
2024-06-26 14:25         ` Arnd Bergmann
2024-06-26 16:02         ` Jisheng Zhang
2024-06-26 16:02           ` Jisheng Zhang
2024-06-27  6:46           ` Arnd Bergmann
2024-06-27  6:46             ` Arnd Bergmann
2024-06-28 15:36         ` David Laight [this message]
2024-06-28 15:36           ` David Laight
2024-06-25  4:04 ` [PATCH 3/4] riscv: uaccess: use 'asm goto' for put_user() Jisheng Zhang
2024-06-25  4:04   ` Jisheng Zhang
2024-07-05  2:22   ` kernel test robot
2024-07-05  2:22     ` kernel test robot
2024-07-06  0:02   ` kernel test robot
2024-07-06  0:02     ` kernel test robot
2024-06-25  4:05 ` [PATCH 4/4] riscv: uaccess: use 'asm goto output' for get_user Jisheng Zhang
2024-06-25  4:05   ` Jisheng Zhang
2024-07-05  4:13   ` kernel test robot
2024-07-05  4:13     ` kernel test robot
2024-06-25  7:21 ` [PATCH 0/4] riscv: uaccess: optimizations Arnd Bergmann
2024-06-25  7:21   ` Arnd Bergmann
2024-06-25 18:12   ` Linus Torvalds
2024-06-25 18:12     ` Linus Torvalds
2024-06-26 13:04     ` Jisheng Zhang
2024-06-26 13:04       ` Jisheng Zhang
2024-06-30 16:59     ` Linus Torvalds
2024-06-30 16:59       ` Linus Torvalds
2024-07-05 11:25       ` Will Deacon
2024-07-05 11:25         ` Will Deacon
2024-07-05 17:58         ` Linus Torvalds
2024-07-05 17:58           ` Linus Torvalds
2024-07-08 13:52           ` Will Deacon
2024-07-08 13:52             ` Will Deacon
2024-07-08 15:30             ` Mark Rutland
2024-07-08 15:30               ` Mark Rutland
2024-07-23 14:16               ` Will Deacon
2024-07-23 14:16                 ` Will Deacon
2024-07-08 15:21           ` Mark Rutland
2024-07-08 15:21             ` Mark Rutland
2024-07-24 22:57 ` Palmer Dabbelt
2024-07-24 22:57   ` Palmer Dabbelt

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