From: Jan Beulich <jbeulich@suse.com>
To: Roger Pau Monne <roger.pau@citrix.com>
Cc: xen-devel@lists.xenproject.org, Wei Liu <wl@xen.org>,
Andrew Cooper <andrew.cooper3@citrix.com>
Subject: Re: [PATCH v4] x86/idle: prevent entering C6 with in service interrupts on Intel
Date: Fri, 22 May 2020 15:42:10 +0200 [thread overview]
Message-ID: <b59a2d2e-e66d-f3a1-dd85-fd7c7eccc98a@suse.com> (raw)
In-Reply-To: <20200521092258.82503-1-roger.pau@citrix.com>
On 21.05.2020 11:22, Roger Pau Monne wrote:
> Apply a workaround for Intel errata BDX99, CLX30, SKX100, CFW125,
> BDF104, BDH85, BDM135, KWB131: "A Pending Fixed Interrupt May Be
> Dispatched Before an Interrupt of The Same Priority Completes".
While the change looks good to me as far as Broadwell goes, I
think it was before this posting that Andrew also pointed at
a specific Haswell erratum instance, still on the v3 thread.
Am I to imply a v5 will follow adding affected Haswell models
to the table?
Jan
next prev parent reply other threads:[~2020-05-22 14:10 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-21 9:22 [PATCH v4] x86/idle: prevent entering C6 with in service interrupts on Intel Roger Pau Monne
2020-05-22 13:42 ` Jan Beulich [this message]
2020-05-22 13:54 ` Roger Pau Monné
2020-05-22 14:05 ` Jan Beulich
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