From: Andre Przywara <andre.przywara@arm.com>
To: Vinicius Pedrosa <vinicius.eduardo.pedrosa@gmail.com>,
Junhui Liu <junhui.liu@pigmoral.tech>
Cc: Chen-Yu Tsai <wens@kernel.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>,
Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney+clk@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Enzo Adriano <enzo.adriano.code@gmail.com>,
linux-clk@vger.kernel.org, linux-sunxi@lists.linux.dev,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v6 6/8] clk: sunxi-ng: a733: Add mod clocks support
Date: Mon, 2 Nov 2026 16:43:24 +0100 [thread overview]
Message-ID: <b63fb278-6d75-4bcb-a23f-abe80edf2837@arm.com> (raw)
In-Reply-To: <20261028180913.2829389-1-vinicius.eduardo.pedrosa@gmail.com>
Hi Vinicius,
On 10/28/26 19:09, Vinicius Pedrosa wrote:
> Hi Junhui,
>
> In patch 6/8, usb2-u2-ref is declared as a plain mux, but the manual
can you please reply inline? Copy the original email, then reply after
the code that you have a comment on? See the other replies on this
series for examples.
After all this is the reason we do this patch-inline-in-email approach
for review, so that the context is clear, and makes it easier for the
author, other reviewers and maintainers to follow the review comments.
Subscribing to the linux-sunxi list is probably the easiest to get the
emails, or use lore to fetch the respective emails. For one-offs you can
also download the mbox file from lore, then import them in your email
application.
Cheers,
Andre
P.S. This applies in general to your email replies, I see them as
completely from scratch text, just with the right In-reply-to header,
but without any context.
> has a gate at bit 31 of 0x1348, and its reset value is 0. So the CCU
> driver can't enable it.
>
> -static SUNXI_CCU_MUX_DATA(usb2_u2_ref_clk, "usb2-u2-ref", usb01_ref_parents, 0x1348, 24, 3, 0);
> +static SUNXI_CCU_MUX_DATA_WITH_GATE(usb2_u2_ref_clk, "usb2-u2-ref", usb01_ref_parents,
> + 0x1348, 24, 3, BIT(31), 0);
>
> I hit this on my Cubie A7Z with a USB stick on the DWC3 port (the DT
> and the USB2 PHY driver for that port are local, not posted):
>
> - v6 as posted: 0x02003348 stays 0 and the DWC3 soft reset times out
> (-110), 4/4 boots, one of them cold.
> - same kernel, only bit 31 set from U-Boot: the host works, 3/3.
> - with the change above: works, 3/3.
>
> Same DTB and initramfs in every run. The SerDes gates were also the
> same, so I haven't checked whether they matter on their own.
>
> My boot chain (U-Boot SPL, TF-A, U-Boot) leaves bit 31 clear. I don't
> know what the vendor one does.
>
> Thanks,
> Vinicius
next prev parent reply other threads:[~2026-11-02 15:43 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-09 15:52 [PATCH v6 0/8] clk: sunxi-ng: Add support for Allwinner A733 CCU and PRCM Junhui Liu
2026-10-09 15:52 ` Junhui Liu
2026-10-09 15:52 ` [PATCH v6 1/8] dt-bindings: clk: sun60i-a733-ccu: Add Allwinner A733 support Junhui Liu
2026-10-09 15:52 ` Junhui Liu
2026-10-09 15:52 ` [PATCH v6 2/8] clk: sunxi-ng: sdm: Add dual patterns support Junhui Liu
2026-10-09 15:52 ` Junhui Liu
2026-10-09 15:52 ` [PATCH v6 3/8] clk: sunxi-ng: a733: Add PRCM CCU Junhui Liu
2026-10-09 15:52 ` Junhui Liu
2026-11-03 1:33 ` Enzo Adriano
2026-11-03 1:33 ` Enzo Adriano
2026-11-09 4:55 ` Junhui Liu
2026-11-09 4:55 ` Junhui Liu
2026-11-11 12:09 ` Enzo Adriano
2026-11-11 12:09 ` Enzo Adriano
2026-10-09 15:52 ` [PATCH v6 4/8] clk: sunxi-ng: a733: Add PLL clocks support Junhui Liu
2026-10-09 15:52 ` Junhui Liu
2026-11-09 16:14 ` Chen-Yu Tsai
2026-11-09 16:14 ` Chen-Yu Tsai
2026-10-09 15:52 ` [PATCH v6 5/8] clk: sunxi-ng: a733: Add bus " Junhui Liu
2026-10-09 15:52 ` Junhui Liu
2026-11-09 15:59 ` Chen-Yu Tsai
2026-11-09 15:59 ` Chen-Yu Tsai
2026-10-09 15:52 ` [PATCH v6 6/8] clk: sunxi-ng: a733: Add mod " Junhui Liu
2026-10-09 15:52 ` Junhui Liu
2026-10-28 18:09 ` Vinicius Pedrosa
2026-11-02 15:43 ` Andre Przywara [this message]
2026-11-09 3:27 ` Junhui Liu
2026-11-02 15:32 ` Andre Przywara
2026-11-02 15:32 ` Andre Przywara
2026-11-03 12:11 ` Vinicius Pedrosa
2026-11-03 12:11 ` Vinicius Pedrosa
2026-11-09 3:16 ` Junhui Liu
2026-11-09 3:16 ` Junhui Liu
2026-11-09 16:07 ` Chen-Yu Tsai
2026-11-09 16:07 ` Chen-Yu Tsai
2026-10-09 15:52 ` [PATCH v6 7/8] clk: sunxi-ng: a733: Add bus clock gates Junhui Liu
2026-10-09 15:52 ` Junhui Liu
2026-10-10 15:54 ` sashiko-bot
2026-10-10 17:09 ` Junhui Liu
2026-10-09 15:52 ` [PATCH v6 8/8] clk: sunxi-ng: a733: Add reset lines Junhui Liu
2026-10-09 15:52 ` Junhui Liu
2026-10-11 20:01 ` [PATCH v6 0/8] clk: sunxi-ng: Add support for Allwinner A733 CCU and PRCM Vinicius Pedrosa
2026-10-12 15:41 ` Enzo Adriano
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