From: Harsh Prateek Bora <harshpb@linux.ibm.com>
To: Nicholas Piggin <npiggin@gmail.com>, qemu-ppc@nongnu.org
Cc: qemu-devel@nongnu.org,
Daniel Henrique Barboza <danielhb413@gmail.com>,
David Gibson <david@gibson.dropbear.id.au>
Subject: Re: [PATCH v2 08/10] ppc/pnv: Set POWER9, POWER10 ibm,pa-features bits
Date: Tue, 12 Mar 2024 19:14:17 +0530 [thread overview]
Message-ID: <b6d04ed3-efc7-4882-8bf7-e0829a07b3ce@linux.ibm.com> (raw)
In-Reply-To: <20240312131419.2196845-9-npiggin@gmail.com>
On 3/12/24 18:44, Nicholas Piggin wrote:
> Copy the pa-features arrays from spapr, adjusting slightly as
> described in comments.
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Although future re-org is expected per discussion on v1, but for now:
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
> ---
> hw/ppc/pnv.c | 67 ++++++++++++++++++++++++++++++++++++++++++++++++--
> hw/ppc/spapr.c | 1 +
> 2 files changed, 66 insertions(+), 2 deletions(-)
>
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 52d964f77a..8a502dea90 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -332,6 +332,35 @@ static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
> }
> }
>
> +/*
> + * Same as spapr pa_features_300 except pnv always enables CI largepages bit.
> + */
> +static const uint8_t pa_features_300[] = { 66, 0,
> + /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
> + /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */
> + 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */
> + /* 6: DS207 */
> + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
> + /* 16: Vector */
> + 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
> + /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
> + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */
> + /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
> + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
> + /* 32: LE atomic, 34: EBB + ext EBB */
> + 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
> + /* 40: Radix MMU */
> + 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */
> + /* 42: PM, 44: PC RA, 46: SC vec'd */
> + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
> + /* 48: SIMD, 50: QP BFP, 52: String */
> + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
> + /* 54: DecFP, 56: DecI, 58: SHA */
> + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
> + /* 60: NM atomic, 62: RNG */
> + 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
> +};
> +
> static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
> {
> static const char compat[] = "ibm,power9-xscom\0ibm,xscom";
> @@ -349,7 +378,7 @@ static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
> offset = pnv_dt_core(chip, pnv_core, fdt);
>
> _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
> - pa_features_207, sizeof(pa_features_207))));
> + pa_features_300, sizeof(pa_features_300))));
> }
>
> if (chip->ram_size) {
> @@ -359,6 +388,40 @@ static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
> pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE);
> }
>
> +/*
> + * Same as spapr pa_features_31 except pnv always enables CI largepages bit,
> + * always disables copy/paste.
> + */
> +static const uint8_t pa_features_31[] = { 74, 0,
> + /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
> + /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */
> + 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */
> + /* 6: DS207 */
> + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
> + /* 16: Vector */
> + 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
> + /* 18: Vec. Scalar, 20: Vec. XOR */
> + 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
> + /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
> + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
> + /* 32: LE atomic, 34: EBB + ext EBB */
> + 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
> + /* 40: Radix MMU */
> + 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */
> + /* 42: PM, 44: PC RA, 46: SC vec'd */
> + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
> + /* 48: SIMD, 50: QP BFP, 52: String */
> + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
> + /* 54: DecFP, 56: DecI, 58: SHA */
> + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
> + /* 60: NM atomic, 62: RNG */
> + 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
> + /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */
> + 0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */
> + /* 72: [P]HASHST/[P]HASHCHK */
> + 0x80, 0x00, /* 72 - 73 */
> +};
> +
> static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
> {
> static const char compat[] = "ibm,power10-xscom\0ibm,xscom";
> @@ -376,7 +439,7 @@ static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
> offset = pnv_dt_core(chip, pnv_core, fdt);
>
> _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
> - pa_features_207, sizeof(pa_features_207))));
> + pa_features_31, sizeof(pa_features_31))));
> }
>
> if (chip->ram_size) {
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index a684e0d9dc..abd484023a 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -243,6 +243,7 @@ static void spapr_dt_pa_features(SpaprMachineState *spapr,
> * so there isn't much need for it anyway.
> */
>
> + /* These should be kept in sync with pnv */
> uint8_t pa_features_206[] = { 6, 0,
> 0xf6, 0x1f, 0xc7, 0x00, 0x00, 0xc0 };
> uint8_t pa_features_207[] = { 24, 0,
next prev parent reply other threads:[~2024-03-12 13:45 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-12 13:14 [PATCH v2 00/10] misc ppc patches Nicholas Piggin
2024-03-12 13:14 ` [PATCH v2 01/10] ppc: Drop support for POWER9 and POWER10 DD1 chips Nicholas Piggin
2024-03-12 13:14 ` [PATCH v2 02/10] target/ppc: POWER10 does not have transactional memory Nicholas Piggin
2024-03-12 13:14 ` [PATCH v2 03/10] ppc/spapr|pnv: Remove SAO from pa-features Nicholas Piggin
2024-03-14 2:34 ` David Gibson
2024-03-14 4:49 ` Nicholas Piggin
2024-03-12 13:14 ` [PATCH v2 04/10] ppc/spapr: Remove copy-paste " Nicholas Piggin
2024-03-14 2:35 ` David Gibson
2024-03-12 13:14 ` [PATCH v2 05/10] ppc/spapr: Adjust ibm,pa-features for POWER9 Nicholas Piggin
2024-03-12 13:14 ` [PATCH v2 06/10] ppc/spapr: Add pa-features for POWER10 machines Nicholas Piggin
2024-03-12 13:14 ` [PATCH v2 07/10] ppc/pnv: Permit ibm, pa-features set per machine variant Nicholas Piggin
2024-03-12 13:39 ` Harsh Prateek Bora
2024-03-12 13:14 ` [PATCH v2 08/10] ppc/pnv: Set POWER9, POWER10 ibm,pa-features bits Nicholas Piggin
2024-03-12 13:44 ` Harsh Prateek Bora [this message]
2024-03-12 13:14 ` [PATCH v2 09/10] target/ppc: Prevent supervisor from modifying MSR[ME] Nicholas Piggin
2024-03-12 13:14 ` [PATCH v2 10/10] spapr: set MSR[ME] and MSR[FP] on client entry Nicholas Piggin
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