From: Lu Baolu <baolu.lu@linux.intel.com>
To: "Liu, Yi L" <yi.l.liu@intel.com>, Joerg Roedel <joro@8bytes.org>,
David Woodhouse <dwmw2@infradead.org>,
Alex Williamson <alex.williamson@redhat.com>
Cc: "Tian, Kevin" <kevin.tian@intel.com>,
"Raj, Ashok" <ashok.raj@intel.com>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
"Kumar, Sanjay K" <sanjay.k.kumar@intel.com>,
"iommu@lists.linux-foundation.org"
<iommu@lists.linux-foundation.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"Sun, Yi Y" <yi.y.sun@intel.com>
Subject: Re: [PATCH v3 4/6] iommu/vt-d: Setup pasid entries for iova over first level
Date: Tue, 17 Dec 2019 10:03:41 +0800 [thread overview]
Message-ID: <b883602c-ecdf-11ea-c26c-4b221bf7634d@linux.intel.com> (raw)
In-Reply-To: <A2975661238FB949B60364EF0F2C25743A132C9A@SHSMSX104.ccr.corp.intel.com>
Hi Yi,
On 12/15/19 5:37 PM, Liu, Yi L wrote:
>> XD (bit 63) is only for the first level, and SNP (bit 11) is only for second level, right? I
>> think we need to always set XD bit for IOVA over FL case. thoughts?
> Oops, I made a mistake here. Please forget SNP bit, there is no way to control SNP
> with first level page table.:-)
>
> Actually, it is execute (bit 1) of second level page table which I wanted to say.
> If software sets R/W/X permission to an IOVA, with IOVA over second level
> page table, it will set bit 1. However, if IOVA is over first level page table, it
> may need to clear XD bit. This is what I want to say here. If IOVA doesn’t allow
> execute permission, it's ok to always set XD bit for IOVA over FL case. But I
> would like to do it just as what we did for R/W permission. R/W permission
> relies on the permission configured by the page map caller. right?
Got your point.
Current driver always cleard X (bit 2) in the second level page table.
So we will always set XD bit (bit 63) in the first level page table.
If we decide to use the X permission, we need a separated patch, right?
Best regards,
baolu
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WARNING: multiple messages have this Message-ID (diff)
From: Lu Baolu <baolu.lu@linux.intel.com>
To: "Liu, Yi L" <yi.l.liu@intel.com>, Joerg Roedel <joro@8bytes.org>,
David Woodhouse <dwmw2@infradead.org>,
Alex Williamson <alex.williamson@redhat.com>
Cc: baolu.lu@linux.intel.com, "Raj, Ashok" <ashok.raj@intel.com>,
"Kumar, Sanjay K" <sanjay.k.kumar@intel.com>,
"jacob.jun.pan@linux.intel.com" <jacob.jun.pan@linux.intel.com>,
"Tian, Kevin" <kevin.tian@intel.com>,
"Sun, Yi Y" <yi.y.sun@intel.com>, Peter Xu <peterx@redhat.com>,
"iommu@lists.linux-foundation.org"
<iommu@lists.linux-foundation.org>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v3 4/6] iommu/vt-d: Setup pasid entries for iova over first level
Date: Tue, 17 Dec 2019 10:03:41 +0800 [thread overview]
Message-ID: <b883602c-ecdf-11ea-c26c-4b221bf7634d@linux.intel.com> (raw)
In-Reply-To: <A2975661238FB949B60364EF0F2C25743A132C9A@SHSMSX104.ccr.corp.intel.com>
Hi Yi,
On 12/15/19 5:37 PM, Liu, Yi L wrote:
>> XD (bit 63) is only for the first level, and SNP (bit 11) is only for second level, right? I
>> think we need to always set XD bit for IOVA over FL case. thoughts?
> Oops, I made a mistake here. Please forget SNP bit, there is no way to control SNP
> with first level page table.:-)
>
> Actually, it is execute (bit 1) of second level page table which I wanted to say.
> If software sets R/W/X permission to an IOVA, with IOVA over second level
> page table, it will set bit 1. However, if IOVA is over first level page table, it
> may need to clear XD bit. This is what I want to say here. If IOVA doesn’t allow
> execute permission, it's ok to always set XD bit for IOVA over FL case. But I
> would like to do it just as what we did for R/W permission. R/W permission
> relies on the permission configured by the page map caller. right?
Got your point.
Current driver always cleard X (bit 2) in the second level page table.
So we will always set XD bit (bit 63) in the first level page table.
If we decide to use the X permission, we need a separated patch, right?
Best regards,
baolu
next prev parent reply other threads:[~2019-12-17 2:04 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-11 2:12 [PATCH v3 0/6] Use 1st-level for IOVA translation Lu Baolu
2019-12-11 2:12 ` Lu Baolu
2019-12-11 2:12 ` [PATCH v3 1/6] iommu/vt-d: Identify domains using first level page table Lu Baolu
2019-12-11 2:12 ` Lu Baolu
2019-12-11 2:12 ` [PATCH v3 2/6] iommu/vt-d: Add set domain DOMAIN_ATTR_NESTING attr Lu Baolu
2019-12-11 2:12 ` Lu Baolu
2019-12-11 2:12 ` [PATCH v3 3/6] iommu/vt-d: Add PASID_FLAG_FL5LP for first-level pasid setup Lu Baolu
2019-12-11 2:12 ` Lu Baolu
2019-12-11 2:12 ` [PATCH v3 4/6] iommu/vt-d: Setup pasid entries for iova over first level Lu Baolu
2019-12-11 2:12 ` Lu Baolu
2019-12-13 9:23 ` Liu, Yi L
2019-12-13 9:23 ` Liu, Yi L
2019-12-14 3:03 ` Lu Baolu
2019-12-14 3:03 ` Lu Baolu
2019-12-15 9:37 ` Liu, Yi L
2019-12-15 9:37 ` Liu, Yi L
2019-12-17 2:03 ` Lu Baolu [this message]
2019-12-17 2:03 ` Lu Baolu
2019-12-17 2:33 ` Liu, Yi L
2019-12-17 2:33 ` Liu, Yi L
2019-12-11 2:12 ` [PATCH v3 5/6] iommu/vt-d: Flush PASID-based iotlb " Lu Baolu
2019-12-11 2:12 ` Lu Baolu
2019-12-13 11:42 ` Liu, Yi L
2019-12-13 11:42 ` Liu, Yi L
2019-12-14 3:24 ` Lu Baolu
2019-12-14 3:24 ` Lu Baolu
2019-12-15 9:22 ` Liu, Yi L
2019-12-15 9:22 ` Liu, Yi L
2019-12-17 1:19 ` Lu Baolu
2019-12-17 1:19 ` Lu Baolu
2019-12-17 1:37 ` Lu Baolu
2019-12-17 1:37 ` Lu Baolu
2019-12-17 1:39 ` Lu Baolu
2019-12-17 1:39 ` Lu Baolu
2019-12-17 2:44 ` Liu, Yi L
2019-12-17 2:44 ` Liu, Yi L
2019-12-17 2:26 ` Liu, Yi L
2019-12-17 2:26 ` Liu, Yi L
2019-12-17 2:36 ` Liu, Yi L
2019-12-17 2:36 ` Liu, Yi L
2019-12-17 4:13 ` Lu Baolu
2019-12-17 4:13 ` Lu Baolu
2019-12-11 2:12 ` [PATCH v3 6/6] iommu/vt-d: Use " Lu Baolu
2019-12-11 2:12 ` Lu Baolu
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