RE: [PATCH v3 8/8] ARM: realtek: Enable RTD1195 arch timer

["James Tai [戴志峰]" <james.tai@realtek.com>]

Hi Andreas,

> >>>>  What is the name of the register 0xff018000?
> >>>>  Is 0x1 a BIT(0) write, or how are the register bits defined?
> >>>>  Is this a reset or a clock gate? How should we model it in DT?
> 
> No, I was pointing out that I myself had already asked pretty much the same
> questions you just asked me. How did you expect me to have answers to your
> "Shouldn't this be a read/modify/write sequence?" then? It seemed like you
> missed my questions up there:
> 
> Without knowing how the register is structured, I can't implement a
> read/modify/write sequence - for that we'd need to know whether it's a single
> bit we can just set or a field that we would need to mask first before writing
> into it.

This register is counter control register of CoreSight timestamp generator. [1][2].
The CPU timer count input signal is inherited from the timestamp generator, so it must be enabled before CPU timer initial.

This register setting can move into boot code.

[1] https://developer.arm.com/docs/100806/0200/9-programmers-model/css600_tsgen/control-interface-register-descriptions
[2] https://developer.arm.com/docs/100806/0200/5-timestamp-components-functional-description/timestamp-generator


Thanks.

Regards,
James


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