Re: [PATCH 2/7] x86/xstate: Cross-check dynamic XSTATE sizes at boot

[Jan Beulich <jbeulich@suse.com>]

On 14.06.2024 15:56, Andrew Cooper wrote:
> On 23/05/2024 4:34 pm, Jan Beulich wrote:
>> On 23.05.2024 13:16, Andrew Cooper wrote:
>>> Right now, xstate_ctxt_size() performs a cross-check of size with CPUID in for
>>> every call.  This is expensive, being used for domain create/migrate, as well
>>> as to service certain guest CPUID instructions.
>>>
>>> Instead, arrange to check the sizes once at boot.  See the code comments for
>>> details.  Right now, it just checks hardware against the algorithm
>>> expectations.  Later patches will add further cross-checking.
>>>
>>> Introduce the missing X86_XCR0_* and X86_XSS_* constants, and a couple of
>>> missing CPUID bits.  This is to maximise coverage in the sanity check, even if
>>> we don't expect to use/virtualise some of these features any time soon.  Leave
>>> HDC and HWP alone for now.  We don't have CPUID bits from them stored nicely.
>> Since you say "the missing", ...
>>
>>> --- a/xen/arch/x86/include/asm/x86-defns.h
>>> +++ b/xen/arch/x86/include/asm/x86-defns.h
>>> @@ -77,7 +77,7 @@
>>>  #define X86_CR4_PKS        0x01000000 /* Protection Key Supervisor */
>>>  
>>>  /*
>>> - * XSTATE component flags in XCR0
>>> + * XSTATE component flags in XCR0 | MSR_XSS
>>>   */
>>>  #define X86_XCR0_FP_POS           0
>>>  #define X86_XCR0_FP               (1ULL << X86_XCR0_FP_POS)
>>> @@ -95,11 +95,34 @@
>>>  #define X86_XCR0_ZMM              (1ULL << X86_XCR0_ZMM_POS)
>>>  #define X86_XCR0_HI_ZMM_POS       7
>>>  #define X86_XCR0_HI_ZMM           (1ULL << X86_XCR0_HI_ZMM_POS)
>>> +#define X86_XSS_PROC_TRACE        (_AC(1, ULL) <<  8)
>>>  #define X86_XCR0_PKRU_POS         9
>>>  #define X86_XCR0_PKRU             (1ULL << X86_XCR0_PKRU_POS)
>>> +#define X86_XSS_PASID             (_AC(1, ULL) << 10)
>>> +#define X86_XSS_CET_U             (_AC(1, ULL) << 11)
>>> +#define X86_XSS_CET_S             (_AC(1, ULL) << 12)
>>> +#define X86_XSS_HDC               (_AC(1, ULL) << 13)
>>> +#define X86_XSS_UINTR             (_AC(1, ULL) << 14)
>>> +#define X86_XSS_LBR               (_AC(1, ULL) << 15)
>>> +#define X86_XSS_HWP               (_AC(1, ULL) << 16)
>>> +#define X86_XCR0_TILE_CFG         (_AC(1, ULL) << 17)
>>> +#define X86_XCR0_TILE_DATA        (_AC(1, ULL) << 18)
>> ... I'm wondering if you deliberately left out APX (bit 19).
> 
> It was deliberate.  APX isn't in the SDM yet, so in principle is still
> subject to change.
> 
> I've tweaked the commit message to avoid using the word 'missing'.

Thanks.

>> Since you're re-doing some of what I have long had in patches already,
>> I'd also like to ask whether the last underscores each in the two AMX
>> names really are useful in your opinion. While rebasing isn't going
>> to be difficult either way, it would be yet simpler with
>> X86_XCR0_TILECFG and X86_XCR0_TILEDATA, as I've had it in my patches
>> for over 3 years.
> 
> I'm torn here.  I don't want to deliberately make things harder for you,
> but I would really prefer that we use the more legible form...

Well, okay, so be it then.

Jan