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From: "Mi, Dapeng" <dapeng1.mi@linux.intel.com>
To: sashiko-reviews@lists.linux.dev
Cc: linux-perf-users@vger.kernel.org
Subject: Re: [RESEND Patch v10 23/23] perf/x86/intel: Add sanity check for PEBS record/fragment size
Date: Tue, 25 Aug 2026 09:39:08 +0800	[thread overview]
Message-ID: <be04bda2-91d4-4af4-8d54-982480eea814@linux.intel.com> (raw)
In-Reply-To: <20260824090815.AD6A41F000E9@smtp.kernel.org>


On 8/24/2026 5:08 PM, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
>
> Pre-existing issues:
> - [High] setup_arch_pebs_sample_data() parses PEBS fragment payloads based on the presence of bit flags without verifying that the implied payload size fits within header->size or the buffer boundary.
> --
>
> --- Patch [23]: [RESEND Patch v10 23/23] perf/x86/intel: Add sanity check for PEBS record/fragment size ---
> commit 573a2a9becb54c34e2eef68662afc34b55c514f9
> Author: Dapeng Mi <dapeng1.mi@linux.intel.com>
>
> perf/x86/intel: Add sanity check for PEBS record/fragment size
>
> This patch adds sanity checks for corrupted PEBS records or fragment
> sizes to prevent potential infinite loops. If a corrupted fragment is
> detected, the entire PEBS record and all subsequent records are dropped.
>
>> diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
>> index 39028de75e4f6..4448144387158 100644
>> --- a/arch/x86/events/intel/ds.c
>> +++ b/arch/x86/events/intel/ds.c
>> @@ -2657,6 +2657,9 @@ static void setup_arch_pebs_sample_data(struct perf_event *event,
>>  
>>  again:
>>  	header = at;
>> +	if (!header->size)
>> +		return;
>> +
>>  	next_record = at + sizeof(struct arch_pebs_header);
>>  	if (header->basic) {
> [Severity: High]
> This is a pre-existing issue, but since this patch explicitly aims to safely
> handle corrupted PEBS records, could a corrupted record have a small
> header->size but multiple structural flags set?
>
> In setup_arch_pebs_sample_data(), next_record is advanced based on the
> presence of bit flags without checking against header->size or the buffer
> boundary:
>
>     if (header->gpr) {
>         gprs = next_record;
>         next_record = gprs + 1;
>         __setup_pebs_gpr_group(event, regs, ...);
>
> Would this lead to out-of-bounds memory reads if the hardware generates a
> corrupted record where the implied payload exceeds header->size? While
> intel_pmu_drain_arch_pebs() checks that header->size fits in the buffer,
> it doesn't seem to verify if the payload itself fits within header->size.

Yes, this concern could happen in theory. This patch mainly focus on the 0
size issue, the issue could be addressed by another patch if necessary. Thanks.


>

  reply	other threads:[~2026-08-25  1:39 UTC|newest]

Thread overview: 57+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-24  8:27 [RESEND Patch v10 00/23] Support SIMD/eGPRs/SSP registers sampling for perf Dapeng Mi
2026-08-24  8:27 ` [RESEND Patch v10 01/23] perf/x86: Move hybrid PMU initialization before x86_pmu_starting_cpu() Dapeng Mi
2026-08-24  8:44   ` sashiko-bot
2026-08-24  8:27 ` [RESEND Patch v10 02/23] perf/x86/intel: Enable large PEBS sampling for XMMs Dapeng Mi
2026-08-24  8:52   ` sashiko-bot
2026-08-24  8:27 ` [RESEND Patch v10 03/23] perf/x86/intel: Convert x86_perf_regs to per-cpu variables Dapeng Mi
2026-08-24  8:46   ` sashiko-bot
2026-08-24  8:27 ` [RESEND Patch v10 04/23] perf: Eliminate duplicate arch-specific function definitions Dapeng Mi
2026-08-24  8:44   ` sashiko-bot
2026-08-24  8:27 ` [RESEND Patch v10 05/23] perf/x86: Use x86_perf_regs in NMI handlers Dapeng Mi
2026-08-24  8:54   ` sashiko-bot
2026-08-24  8:27 ` [RESEND Patch v10 06/23] x86/fpu/xstate: Add xsaves_nmi() helper Dapeng Mi
2026-08-24  8:54   ` sashiko-bot
2026-08-25  1:03     ` Mi, Dapeng
2026-08-24  8:27 ` [RESEND Patch v10 07/23] x86/fpu: Add update_fpu_state_and_flag() helper Dapeng Mi
2026-08-24  8:47   ` sashiko-bot
2026-08-24  8:27 ` [RESEND Patch v10 08/23] perf: Move and enhance has_extended_regs() for arch-specific use Dapeng Mi
2026-08-24  8:47   ` sashiko-bot
2026-08-24  8:27 ` [RESEND Patch v10 09/23] perf/x86/intel: Centralize PERF_PMU_CAP_EXTENDED_REGS updates Dapeng Mi
2026-08-24  8:46   ` sashiko-bot
2026-08-24  8:27 ` [RESEND Patch v10 10/23] perf/x86: Enable XMM register sampling for non-PEBS events Dapeng Mi
2026-08-24  8:53   ` sashiko-bot
2026-08-24  8:27 ` [RESEND Patch v10 11/23] perf/x86: Enable XMM register sampling for REGS_USER case Dapeng Mi
2026-08-24 10:16   ` sashiko-bot
2026-08-25  1:13     ` Mi, Dapeng
2026-08-24  8:27 ` [RESEND Patch v10 12/23] perf: Add sampling support for SIMD registers Dapeng Mi
2026-08-24  8:54   ` sashiko-bot
2026-08-25  1:19     ` Mi, Dapeng
2026-08-24  8:27 ` [RESEND Patch v10 13/23] perf/x86: Support XMM sampling using sample_simd_vec_reg_* fields Dapeng Mi
2026-08-24  9:12   ` sashiko-bot
2026-08-25  1:28     ` Mi, Dapeng
2026-08-24  8:27 ` [RESEND Patch v10 14/23] perf/x86: Support YMM " Dapeng Mi
2026-08-24  8:55   ` sashiko-bot
2026-08-24  8:27 ` [RESEND Patch v10 15/23] perf/x86: Support ZMM " Dapeng Mi
2026-08-24  8:58   ` sashiko-bot
2026-08-25  1:30     ` Mi, Dapeng
2026-08-24  8:27 ` [RESEND Patch v10 16/23] perf/x86: Support OPMASK sampling using sample_simd_pred_reg_* fields Dapeng Mi
2026-08-24  8:54   ` sashiko-bot
2026-08-24  8:27 ` [RESEND Patch v10 17/23] perf: Enhance perf_reg_validate() with simd_enabled argument Dapeng Mi
2026-08-24  8:56   ` sashiko-bot
2026-08-24  8:27 ` [RESEND Patch v10 18/23] perf/x86: Support eGPRs sampling using sample_regs_* fields Dapeng Mi
2026-08-24  8:59   ` sashiko-bot
2026-08-24  8:27 ` [RESEND Patch v10 19/23] perf/x86: Support SSP " Dapeng Mi
2026-08-24  9:39   ` sashiko-bot
2026-08-25  1:34     ` Mi, Dapeng
2026-08-24  8:27 ` [RESEND Patch v10 20/23] perf/x86/intel: Support arch-PEBS based SIMD/eGPRs sampling Dapeng Mi
2026-08-24  9:09   ` sashiko-bot
2026-08-24  8:27 ` [RESEND Patch v10 21/23] perf/x86/intel: Advertise PERF_PMU_CAP_SIMD_REGS capability Dapeng Mi
2026-08-24  9:25   ` sashiko-bot
2026-08-24  8:27 ` [RESEND Patch v10 22/23] perf/x86: Activate back-to-back NMI detection for arch-PEBS induced NMIs Dapeng Mi
2026-08-24  9:06   ` sashiko-bot
2026-08-24  8:27 ` [RESEND Patch v10 23/23] perf/x86/intel: Add sanity check for PEBS record/fragment size Dapeng Mi
2026-08-24  9:08   ` sashiko-bot
2026-08-25  1:39     ` Mi, Dapeng [this message]
2026-09-01  8:55 ` [RESEND Patch v10 00/23] Support SIMD/eGPRs/SSP registers sampling for perf Mi, Dapeng
2026-09-02 11:56   ` Peter Zijlstra
2026-09-02 12:13     ` Mi, Dapeng

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