[PATCH 0/2] SPI/NOR Flash Fixes

[PATCH 0/2] SPI/NOR Flash Fixes

[Anirudh Srinivasan via U-Boot]

Adds a new Micron NOR Flash Device ID and a fix to the Designware SPI
driver to not try dual/quad/octal modes.

Signed-off-by: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>
---
Anirudh Srinivasan (2):
      mtd: spi-nor-ids: Add variant of mt25qu256a chip
      spi: dw: Add supports_op function to reject unsupported transfer modes

 drivers/mtd/spi/spi-nor-ids.c |  2 ++
 drivers/spi/designware_spi.c  | 14 ++++++++++++++
 2 files changed, 16 insertions(+)
---
base-commit: 5c215cb75c3723cbf77c36cbac3e60b001721c79
change-id: 20260803-spi_fixes-586ef497b80a

Best regards,
--  
Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>

[PATCH 1/2] mtd: spi-nor-ids: Add variant of mt25qu256a chip

[Anirudh Srinivasan via U-Boot]

The current mt25qu256a entry has a JEDEC ID with an extended device ID
byte of 0x44. A variant of this chip this (model mt25qu256aba1ew9), has
an extended device ID byte of 0x40. The current JEDEC ID parsing code
incorrectly detects this as an n25q256ax1, which results in 4 byte
read/write opcodes not being used for this chip even though it supports
it.

According to Page 34 in the datasheet [1], the differences in the JEDEC
ID (Bit 3 in the Extended Device ID Data) correspond to whether Pin 1
functions as a Hold or Reset pin. This shouldn't affect any
functionality in U-Boot's communication with the chip.

Document this chip and it's JEDEC ID so that U-Boot uses 4 byte opcodes
for this chip.

[1] https://www.mouser.com/catalog/specsheets/micron%20technology_mict-s-a0001400588-1.pdf

Signed-off-by: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>

---
The differences in the functionality of Pin 1 (Hold/Reset) also reflect
in the model number of the flash chip, as per Page 2 of the datasheet.
The existing entry in U-Boot (0x44, Pin 1 reset), should have a model
number mt25qu256aba3xxx, whereas the chip I'm trying to document (0x40,
Pin 1 hold) should have a model number mt25qu256aba1xxx. I didn't want
to change the name of the existing entry in U-Boot, so I've left it as
is.
---
 drivers/mtd/spi/spi-nor-ids.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 31a2ba49a87..ed43104bf53 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -416,6 +416,8 @@ const struct flash_info spi_nor_ids[] = {
 	{ INFO6("mt25ql256a",    0x20ba19, 0x104400, 64 * 1024,  512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) },
 	{ INFO("n25q256a",    0x20ba19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_FSR) },
 	{ INFO6("mt25qu256a",  0x20bb19, 0x104400, 64 * 1024,  512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) },
+	{ INFO6("mt25qu256aba1",  0x20bb19, 0x104000, 64 * 1024,  512,
+	  SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) },
 	{ INFO("n25q256ax1",  0x20bb19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_QUAD_READ | USE_FSR) },
 	{ INFO("mt25qu128ab", 0x20bb18, 0, 64 * 1024,  256, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
 	{ INFO6("mt25qu512a",  0x20bb20, 0x104400, 64 * 1024, 1024,

-- 
2.43.0

[PATCH 2/2] spi: dw: Add supports_op function to reject unsupported transfer modes

[Anirudh Srinivasan via U-Boot]

The designware spi driver doesn't support dual/quad/octal modes, but
the driver still tries using these modes when it sees a capable flash
chip in the devicetree. Add a supports_op function to this driver to
prevent this from happening and force single lane operation.

Signed-off-by: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>
---
 drivers/spi/designware_spi.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 0df9a4f5abd..2f6dbeb1d94 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -694,8 +694,22 @@ static int dw_spi_adjust_op_size(struct spi_slave *slave, struct spi_mem_op *op)
 	return 0;
 }
 
+/*
+ * This driver only supports 1-1-1 transfers. Reject all other modes.
+ */
+static bool dw_spi_supports_op(struct spi_slave *slave,
+			       const struct spi_mem_op *op)
+{
+	if (op->cmd.buswidth > 1 || op->addr.buswidth > 1 ||
+	    op->dummy.buswidth > 1 || op->data.buswidth > 1)
+		return false;
+
+	return spi_mem_default_supports_op(slave, op);
+}
+
 static const struct spi_controller_mem_ops dw_spi_mem_ops = {
 	.exec_op = dw_spi_exec_op,
+	.supports_op = dw_spi_supports_op,
 	.adjust_op_size = dw_spi_adjust_op_size,
 };
 

-- 
2.43.0

RE: [PATCH 1/2] mtd: spi-nor-ids: Add variant of mt25qu256a chip

[Takahiro.Kuwano]

Hi,

> The current mt25qu256a entry has a JEDEC ID with an extended device ID
> byte of 0x44. A variant of this chip this (model mt25qu256aba1ew9), has
> an extended device ID byte of 0x40. The current JEDEC ID parsing code
> incorrectly detects this as an n25q256ax1, which results in 4 byte
> read/write opcodes not being used for this chip even though it supports
> it.
> 
> According to Page 34 in the datasheet [1], the differences in the JEDEC
> ID (Bit 3 in the Extended Device ID Data) correspond to whether Pin 1
> functions as a Hold or Reset pin. This shouldn't affect any
> functionality in U-Boot's communication with the chip.
> 
> Document this chip and it's JEDEC ID so that U-Boot uses 4 byte opcodes
> for this chip.
> 
> [1] https://www.mouser.com/catalog/specsheets/micron%20technology_mict-s-a0001400588-1.pdf

I would prefer to use Link: tag.

> 
> Signed-off-by: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>
> 
> ---
> The differences in the functionality of Pin 1 (Hold/Reset) also reflect
> in the model number of the flash chip, as per Page 2 of the datasheet.
> The existing entry in U-Boot (0x44, Pin 1 reset), should have a model
> number mt25qu256aba3xxx, whereas the chip I'm trying to document (0x40,
> Pin 1 hold) should have a model number mt25qu256aba1xxx. I didn't want
> to change the name of the existing entry in U-Boot, so I've left it as
> is.
> ---

Thanks for the detailed explanation!

Reviewed-by: Takahiro Kuwano <takahiro.kuwano@infineon.com>

>  drivers/mtd/spi/spi-nor-ids.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
> index 31a2ba49a87..ed43104bf53 100644
> --- a/drivers/mtd/spi/spi-nor-ids.c
> +++ b/drivers/mtd/spi/spi-nor-ids.c
> @@ -416,6 +416,8 @@ const struct flash_info spi_nor_ids[] = {
>         { INFO6("mt25ql256a",    0x20ba19, 0x104400, 64 * 1024,  512, SECT_4K | SPI_NOR_DUAL_READ |
> SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) },
>         { INFO("n25q256a",    0x20ba19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> USE_FSR) },
>         { INFO6("mt25qu256a",  0x20bb19, 0x104400, 64 * 1024,  512, SECT_4K | SPI_NOR_QUAD_READ |
> SPI_NOR_4B_OPCODES | USE_FSR) },
> +       { INFO6("mt25qu256aba1",  0x20bb19, 0x104000, 64 * 1024,  512,
> +         SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) },
>         { INFO("n25q256ax1",  0x20bb19, 0, 64 * 1024,  512, SECT_4K | SPI_NOR_QUAD_READ | USE_FSR) },
>         { INFO("mt25qu128ab", 0x20bb18, 0, 64 * 1024,  256, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
>         { INFO6("mt25qu512a",  0x20bb20, 0x104400, 64 * 1024, 1024,
> 
> --
> 2.43.0