From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: Tao Zhang <quic_taozha@quicinc.com>,
Mathieu Poirier <mathieu.poirier@linaro.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Konrad Dybcio <konradybcio@gmail.com>,
Mike Leach <mike.leach@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Jinlong Mao <quic_jinlmao@quicinc.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
Tingwei Zhang <quic_tingweiz@quicinc.com>,
Yuanfang Zhang <quic_yuanfang@quicinc.com>,
Trilok Soni <quic_tsoni@quicinc.com>,
Song Chai <quic_songchai@quicinc.com>,
linux-arm-msm@vger.kernel.org, andersson@kernel.org
Subject: Re: [PATCH v3 8/8] coresight-tpdm: Add msr register support for CMB
Date: Fri, 12 Jan 2024 09:43:42 +0000 [thread overview]
Message-ID: <bfc274b8-8b60-4d7d-a8bf-467bc8ebbf1c@arm.com> (raw)
In-Reply-To: <94f504c4-76dd-4139-a8e0-c2858b7937bb@quicinc.com>
On 12/01/2024 09:12, Tao Zhang wrote:
>
> On 12/20/2023 5:06 PM, Tao Zhang wrote:
>>
>> On 12/19/2023 10:09 PM, Suzuki K Poulose wrote:
>>> On 19/12/2023 06:58, Tao Zhang wrote:
>>>>
>>>> On 12/18/2023 7:02 PM, Suzuki K Poulose wrote:
>>>>> On 21/11/2023 02:24, Tao Zhang wrote:
>>>>>> Add the nodes for CMB subunit MSR(mux select register) support.
>>>>>> CMB MSRs(mux select registers) is to separate mux,arbitration,
>>>>>> ,interleaving,data packing control from stream filtering control.
>>>>>>
>>>>>> Reviewed-by: James Clark <james.clark@arm.com>
>>>>>> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
>>>>>> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
>>>>>> ---
>>>>>> .../testing/sysfs-bus-coresight-devices-tpdm | 8 ++
>>>>>> drivers/hwtracing/coresight/coresight-tpdm.c | 86
>>>>>> +++++++++++++++++++
>>>>>> drivers/hwtracing/coresight/coresight-tpdm.h | 16 +++-
>>>>>> 3 files changed, 109 insertions(+), 1 deletion(-)
>>>>>>
>>>>>> diff --git
>>>>>> a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
>>>>>> b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
>>>>>> index e0b77107be13..914f3fd81525 100644
>>>>>> --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
>>>>>> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
>>>>>> @@ -249,3 +249,11 @@ Description:
>>>>>> Accepts only one of the 2 values - 0 or 1.
>>>>>> 0 : Disable the timestamp of all trace packets.
>>>>>> 1 : Enable the timestamp of all trace packets.
>>>>>> +
>>>>>> +What: /sys/bus/coresight/devices/<tpdm-name>/cmb_msr/msr[0:31]
>>>>>> +Date: September 2023
>>>>>> +KernelVersion 6.7
>>>>>> +Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao
>>>>>> Zhang (QUIC) <quic_taozha@quicinc.com>
>>>>>> +Description:
>>>>>> + (RW) Set/Get the MSR(mux select register) for the CMB
>>>>>> subunit
>>>>>> + TPDM.
>>>>>> diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c
>>>>>> b/drivers/hwtracing/coresight/coresight-tpdm.c
>>>>>> index f6cda5616e84..7e331ea436cc 100644
>>>>>> --- a/drivers/hwtracing/coresight/coresight-tpdm.c
>>>>>> +++ b/drivers/hwtracing/coresight/coresight-tpdm.c
>>>>>> @@ -86,6 +86,11 @@ static ssize_t tpdm_simple_dataset_show(struct
>>>>>> device *dev,
>>>>>> return -EINVAL;
>>>>>> return sysfs_emit(buf, "0x%x\n",
>>>>>> drvdata->cmb->patt_mask[tpdm_attr->idx]);
>>>>>> + case CMB_MSR:
>>>>>> + if (tpdm_attr->idx >= drvdata->cmb_msr_num)
>>>>>> + return -EINVAL;
>>>>>> + return sysfs_emit(buf, "0x%x\n",
>>>>>> + drvdata->cmb->msr[tpdm_attr->idx]);
>>>>>> }
>>>>>> return -EINVAL;
>>>>>> }
>>>>>> @@ -162,6 +167,12 @@ static ssize_t
>>>>>> tpdm_simple_dataset_store(struct device *dev,
>>>>>> else
>>>>>> ret = -EINVAL;
>>>>>> break;
>>>>>> + case CMB_MSR:
>>>>>> + if (tpdm_attr->idx < drvdata->cmb_msr_num)
>>>>>> + drvdata->cmb->msr[tpdm_attr->idx] = val;
>>>>>> + else
>>>>>> + ret = -EINVAL;
>>>>>
>>>>>
>>>>> minor nit: Could we not break from here instead of adding return
>>>>> -EINVAL
>>>>> for each case ? (I understand it has been done for the existing cases.
>>>>> But I think we should clean up all of that, including the ones you
>>>>> added
>>>>> in Patch 5. Similarly for the dataset_show()
>>>>
>>>> Sure, do I also need to change the DSB corresponding code? If so,
>>>> how about
>>>>
>>>> if I add a new patch to the next patch series to change the previous
>>>> existing cases?
>>>
>>> You could fix the existing cases as a preparatory patch of the next
>>> version of this series. I can pick it up and push it to next as I see
>>> fit.
>>
>> Got it. I will update this to the next patch series.
>
> Hi Suzuki,
>
>
> Since the dataset data is configured with spin lock protection, it needs
> to be unlock before return.
>
> List my modification below. Would you mind help review to see if it is
> good for you.
>
> static ssize_t tpdm_simple_dataset_store(struct device *dev,
> struct device_attribute *attr,
> const char *buf,
> size_t size)
> {
> unsigned long val;
>
> struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
> struct tpdm_dataset_attribute *tpdm_attr =
> container_of(attr, struct tpdm_dataset_attribute, attr);
>
> if (kstrtoul(buf, 0, &val))
> return -EINVAL;
>
> spin_lock(&drvdata->spinlock);
Use guard() to avoid explicit unlock on return and then you don't need
the spin_unlock() everywhere. It would be done on return from the
function implicitly.
> switch (tpdm_attr->mem) {
> case DSB_TRIG_PATT:
With guard() in place:
ret = -EINVAL;
switch () {
case XXX:
if (tpdm_attr->idx < TPDM_XXXX_IDX) {
drvdata->dsb->trig_patt[tpdm_attr->idx] = val;
ret = size;
}
break;
case ...
...
}
return ret;
Suzuki
WARNING: multiple messages have this Message-ID (diff)
From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: Tao Zhang <quic_taozha@quicinc.com>,
Mathieu Poirier <mathieu.poirier@linaro.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Konrad Dybcio <konradybcio@gmail.com>,
Mike Leach <mike.leach@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Jinlong Mao <quic_jinlmao@quicinc.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
Tingwei Zhang <quic_tingweiz@quicinc.com>,
Yuanfang Zhang <quic_yuanfang@quicinc.com>,
Trilok Soni <quic_tsoni@quicinc.com>,
Song Chai <quic_songchai@quicinc.com>,
linux-arm-msm@vger.kernel.org, andersson@kernel.org
Subject: Re: [PATCH v3 8/8] coresight-tpdm: Add msr register support for CMB
Date: Fri, 12 Jan 2024 09:43:42 +0000 [thread overview]
Message-ID: <bfc274b8-8b60-4d7d-a8bf-467bc8ebbf1c@arm.com> (raw)
In-Reply-To: <94f504c4-76dd-4139-a8e0-c2858b7937bb@quicinc.com>
On 12/01/2024 09:12, Tao Zhang wrote:
>
> On 12/20/2023 5:06 PM, Tao Zhang wrote:
>>
>> On 12/19/2023 10:09 PM, Suzuki K Poulose wrote:
>>> On 19/12/2023 06:58, Tao Zhang wrote:
>>>>
>>>> On 12/18/2023 7:02 PM, Suzuki K Poulose wrote:
>>>>> On 21/11/2023 02:24, Tao Zhang wrote:
>>>>>> Add the nodes for CMB subunit MSR(mux select register) support.
>>>>>> CMB MSRs(mux select registers) is to separate mux,arbitration,
>>>>>> ,interleaving,data packing control from stream filtering control.
>>>>>>
>>>>>> Reviewed-by: James Clark <james.clark@arm.com>
>>>>>> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
>>>>>> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
>>>>>> ---
>>>>>> .../testing/sysfs-bus-coresight-devices-tpdm | 8 ++
>>>>>> drivers/hwtracing/coresight/coresight-tpdm.c | 86
>>>>>> +++++++++++++++++++
>>>>>> drivers/hwtracing/coresight/coresight-tpdm.h | 16 +++-
>>>>>> 3 files changed, 109 insertions(+), 1 deletion(-)
>>>>>>
>>>>>> diff --git
>>>>>> a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
>>>>>> b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
>>>>>> index e0b77107be13..914f3fd81525 100644
>>>>>> --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
>>>>>> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
>>>>>> @@ -249,3 +249,11 @@ Description:
>>>>>> Accepts only one of the 2 values - 0 or 1.
>>>>>> 0 : Disable the timestamp of all trace packets.
>>>>>> 1 : Enable the timestamp of all trace packets.
>>>>>> +
>>>>>> +What: /sys/bus/coresight/devices/<tpdm-name>/cmb_msr/msr[0:31]
>>>>>> +Date: September 2023
>>>>>> +KernelVersion 6.7
>>>>>> +Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao
>>>>>> Zhang (QUIC) <quic_taozha@quicinc.com>
>>>>>> +Description:
>>>>>> + (RW) Set/Get the MSR(mux select register) for the CMB
>>>>>> subunit
>>>>>> + TPDM.
>>>>>> diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c
>>>>>> b/drivers/hwtracing/coresight/coresight-tpdm.c
>>>>>> index f6cda5616e84..7e331ea436cc 100644
>>>>>> --- a/drivers/hwtracing/coresight/coresight-tpdm.c
>>>>>> +++ b/drivers/hwtracing/coresight/coresight-tpdm.c
>>>>>> @@ -86,6 +86,11 @@ static ssize_t tpdm_simple_dataset_show(struct
>>>>>> device *dev,
>>>>>> return -EINVAL;
>>>>>> return sysfs_emit(buf, "0x%x\n",
>>>>>> drvdata->cmb->patt_mask[tpdm_attr->idx]);
>>>>>> + case CMB_MSR:
>>>>>> + if (tpdm_attr->idx >= drvdata->cmb_msr_num)
>>>>>> + return -EINVAL;
>>>>>> + return sysfs_emit(buf, "0x%x\n",
>>>>>> + drvdata->cmb->msr[tpdm_attr->idx]);
>>>>>> }
>>>>>> return -EINVAL;
>>>>>> }
>>>>>> @@ -162,6 +167,12 @@ static ssize_t
>>>>>> tpdm_simple_dataset_store(struct device *dev,
>>>>>> else
>>>>>> ret = -EINVAL;
>>>>>> break;
>>>>>> + case CMB_MSR:
>>>>>> + if (tpdm_attr->idx < drvdata->cmb_msr_num)
>>>>>> + drvdata->cmb->msr[tpdm_attr->idx] = val;
>>>>>> + else
>>>>>> + ret = -EINVAL;
>>>>>
>>>>>
>>>>> minor nit: Could we not break from here instead of adding return
>>>>> -EINVAL
>>>>> for each case ? (I understand it has been done for the existing cases.
>>>>> But I think we should clean up all of that, including the ones you
>>>>> added
>>>>> in Patch 5. Similarly for the dataset_show()
>>>>
>>>> Sure, do I also need to change the DSB corresponding code? If so,
>>>> how about
>>>>
>>>> if I add a new patch to the next patch series to change the previous
>>>> existing cases?
>>>
>>> You could fix the existing cases as a preparatory patch of the next
>>> version of this series. I can pick it up and push it to next as I see
>>> fit.
>>
>> Got it. I will update this to the next patch series.
>
> Hi Suzuki,
>
>
> Since the dataset data is configured with spin lock protection, it needs
> to be unlock before return.
>
> List my modification below. Would you mind help review to see if it is
> good for you.
>
> static ssize_t tpdm_simple_dataset_store(struct device *dev,
> struct device_attribute *attr,
> const char *buf,
> size_t size)
> {
> unsigned long val;
>
> struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
> struct tpdm_dataset_attribute *tpdm_attr =
> container_of(attr, struct tpdm_dataset_attribute, attr);
>
> if (kstrtoul(buf, 0, &val))
> return -EINVAL;
>
> spin_lock(&drvdata->spinlock);
Use guard() to avoid explicit unlock on return and then you don't need
the spin_unlock() everywhere. It would be done on return from the
function implicitly.
> switch (tpdm_attr->mem) {
> case DSB_TRIG_PATT:
With guard() in place:
ret = -EINVAL;
switch () {
case XXX:
if (tpdm_attr->idx < TPDM_XXXX_IDX) {
drvdata->dsb->trig_patt[tpdm_attr->idx] = val;
ret = size;
}
break;
case ...
...
}
return ret;
Suzuki
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2024-01-12 9:43 UTC|newest]
Thread overview: 108+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-21 2:24 [PATCH v3 0/8] Add support to configure TPDM CMB subunit Tao Zhang
2023-11-21 2:24 ` Tao Zhang
2023-11-21 2:24 ` [PATCH v3 1/8] dt-bindings: arm: Add support for CMB element size Tao Zhang
2023-11-21 2:24 ` Tao Zhang
2023-11-21 7:24 ` Krzysztof Kozlowski
2023-11-21 7:24 ` Krzysztof Kozlowski
2023-12-19 0:14 ` Tao Zhang
2023-12-19 0:14 ` Tao Zhang
2023-12-15 11:19 ` James Clark
2023-12-15 11:19 ` James Clark
2023-12-18 9:21 ` Tao Zhang
2023-12-18 9:21 ` Tao Zhang
2023-11-21 2:24 ` [PATCH v3 2/8] coresight-tpda: Add support to configure CMB element Tao Zhang
2023-11-21 2:24 ` Tao Zhang
2023-12-15 11:20 ` James Clark
2023-12-15 11:20 ` James Clark
2023-12-18 10:27 ` Suzuki K Poulose
2023-12-18 10:27 ` Suzuki K Poulose
2023-12-19 2:13 ` Tao Zhang
2023-12-19 2:13 ` Tao Zhang
2023-12-19 13:54 ` Suzuki K Poulose
2023-12-19 13:54 ` Suzuki K Poulose
2023-12-20 0:27 ` Tao Zhang
2023-12-20 0:27 ` Tao Zhang
2023-12-19 13:59 ` Suzuki K Poulose
2023-12-19 13:59 ` Suzuki K Poulose
2023-12-20 8:55 ` Tao Zhang
2023-12-20 8:55 ` Tao Zhang
2023-11-21 2:24 ` [PATCH v3 3/8] coresight-tpdm: Add CMB dataset support Tao Zhang
2023-11-21 2:24 ` Tao Zhang
2023-12-18 10:34 ` Suzuki K Poulose
2023-12-18 10:34 ` Suzuki K Poulose
2023-12-19 9:22 ` Tao Zhang
2023-12-19 9:22 ` Tao Zhang
2023-12-19 13:56 ` Suzuki K Poulose
2023-12-19 13:56 ` Suzuki K Poulose
2023-12-20 8:56 ` Tao Zhang
2023-12-20 8:56 ` Tao Zhang
2023-11-21 2:24 ` [PATCH v3 4/8] coresight-tpdm: Add support to configure CMB Tao Zhang
2023-11-21 2:24 ` Tao Zhang
2023-11-21 2:24 ` [PATCH v3 5/8] coresight-tpdm: Add pattern registers support for CMB Tao Zhang
2023-11-21 2:24 ` Tao Zhang
2023-11-21 2:24 ` [PATCH v3 6/8] coresight-tpdm: Add timestamp control register support for the CMB Tao Zhang
2023-11-21 2:24 ` Tao Zhang
2023-12-18 10:46 ` Suzuki K Poulose
2023-12-18 10:46 ` Suzuki K Poulose
2023-12-19 2:43 ` Tao Zhang
2023-12-19 2:43 ` Tao Zhang
2023-12-19 13:51 ` Suzuki K Poulose
2023-12-19 13:51 ` Suzuki K Poulose
2023-12-20 9:51 ` Tao Zhang
2023-12-20 9:51 ` Tao Zhang
2023-12-20 11:07 ` Suzuki K Poulose
2023-12-20 11:07 ` Suzuki K Poulose
2023-12-25 1:55 ` Tao Zhang
2023-12-25 1:55 ` Tao Zhang
2023-12-30 9:39 ` Suzuki K Poulose
2023-12-30 9:39 ` Suzuki K Poulose
2024-01-05 7:49 ` Tao Zhang
2024-01-05 7:49 ` Tao Zhang
2024-01-08 10:42 ` Suzuki K Poulose
2024-01-08 10:42 ` Suzuki K Poulose
2024-01-12 2:42 ` Tao Zhang
2024-01-12 2:42 ` Tao Zhang
2024-01-12 9:29 ` Suzuki K Poulose
2024-01-12 9:29 ` Suzuki K Poulose
2023-11-21 2:24 ` [PATCH v3 7/8] dt-bindings: arm: Add support for TPDM CMB MSR register Tao Zhang
2023-11-21 2:24 ` Tao Zhang
2023-11-21 7:24 ` Krzysztof Kozlowski
2023-11-21 7:24 ` Krzysztof Kozlowski
2023-12-18 10:47 ` Suzuki K Poulose
2023-12-18 10:47 ` Suzuki K Poulose
2023-12-18 11:23 ` Tingwei Zhang
2023-12-18 11:23 ` Tingwei Zhang
2023-12-18 11:56 ` Suzuki K Poulose
2023-12-18 11:56 ` Suzuki K Poulose
2023-12-18 12:17 ` Jinlong Mao
2023-12-18 12:17 ` Jinlong Mao
2023-12-19 10:27 ` Jinlong Mao
2023-12-19 10:27 ` Jinlong Mao
2023-11-21 2:24 ` [PATCH v3 8/8] coresight-tpdm: Add msr register support for CMB Tao Zhang
2023-11-21 2:24 ` Tao Zhang
2023-12-15 11:24 ` James Clark
2023-12-15 11:24 ` James Clark
2023-12-18 11:02 ` Suzuki K Poulose
2023-12-18 11:02 ` Suzuki K Poulose
2023-12-19 6:58 ` Tao Zhang
2023-12-19 6:58 ` Tao Zhang
2023-12-19 14:09 ` Suzuki K Poulose
2023-12-19 14:09 ` Suzuki K Poulose
2023-12-20 9:06 ` Tao Zhang
2023-12-20 9:06 ` Tao Zhang
2024-01-12 9:12 ` Tao Zhang
2024-01-12 9:12 ` Tao Zhang
2024-01-12 9:43 ` Suzuki K Poulose [this message]
2024-01-12 9:43 ` Suzuki K Poulose
2024-01-15 6:20 ` Tao Zhang
2024-01-15 6:20 ` Tao Zhang
2024-01-15 9:20 ` Suzuki K Poulose
2024-01-15 9:20 ` Suzuki K Poulose
2024-01-15 14:15 ` Tao Zhang
2024-01-15 14:15 ` Tao Zhang
2024-01-15 9:55 ` James Clark
2024-01-15 9:55 ` James Clark
2024-01-15 9:57 ` James Clark
2024-01-15 9:57 ` James Clark
2024-01-12 11:57 ` [PATCH v3 0/8] Add support to configure TPDM CMB subunit Suzuki K Poulose
2024-01-12 11:57 ` Suzuki K Poulose
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