[Bug 34110] New: 'high' profile does not set the engine and the memory clocks to the max value

[Bug 34110] New: 'high' profile does not set the engine and the memory clocks to the max value

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=34110

           Summary: 'high' profile does not set the engine and the memory
                    clocks to the max value
           Product: DRI
           Version: XOrg CVS
          Platform: Other
        OS/Version: All
            Status: NEW
          Severity: normal
          Priority: medium
         Component: DRM/Radeon
        AssignedTo: dri-devel@lists.freedesktop.org
        ReportedBy: darkbasic4@gmail.com


gentoo ~ # power-profile high
Power profile set to HIGH!
gentoo ~ # power-profile status
profile
default
default engine clock: 776000 kHz
current engine clock: 769500 kHz
default memory clock: 1126000 kHz
current memory clock: 1125000 kHz
voltage: 1300 mV
PCIE lanes: 16
gentoo ~ # power-profile low
Power profile set to LOW!
gentoo ~ # power-profile status
profile
low
default engine clock: 776000 kHz
current engine clock: 297000 kHz
default memory clock: 1126000 kHz
current memory clock: 1125000 kHz
voltage: 1258 mV
PCIE lanes: 16

Shouldn't it set the engine to 776000 and the memory to 1126000?

RV670 with R600g, 2.6.38-rc4, xorg-server-1.9.4, mesa git, libdrm git,
xf86-video-ati git, pageflipping on, colortiling on, swapbufferwaits off.

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[Bug 34110] 'high' profile does not set the engine and the memory clocks to the max value

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=34110

Alex Deucher <agd5f@yahoo.com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |RESOLVED
         Resolution|                            |NOTABUG

--- Comment #1 from Alex Deucher <agd5f@yahoo.com> 2011-02-09 14:13:53 PST ---
The values set are not always exactly the the same as the values in the table,
they are as close a possible within the constraints of the pll dividers.

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