From: Andrew Cooper <andrew.cooper3@citrix.com>
To: dave.hansen@intel.com
Cc: Andrew Cooper <andrew.cooper3@citrix.com>,
bp@alien8.de, dave.hansen@linux.intel.com, kernel-team@meta.com,
linux-kernel@vger.kernel.org, luto@kernel.org, mingo@redhat.com,
riel@surriel.com, tglx@kernel.org, x86@kernel.org, xin@zytor.com
Subject: Re: [PATCH] x86/entry: Read CR2 in asm entry stub to redcue NMI clobbering window
Date: Thu, 14 May 2026 20:49:41 +0100 [thread overview]
Message-ID: <c1a61b27-8f33-44b4-84f6-e7256c1b5bdc@citrix.com> (raw)
In-Reply-To: <669f925a-df4f-4497-ae41-46b08b6abce6@intel.com>
> I don't think there's a concrete enough problem being solved here to
> justify adding complexity to the entry code. Especially since it's not
> even a robust solution for the problem.
Well, corrupting CR2 is a real problem.
The very best case is that fixing the pagefault at the wrong CR2 is
benign, then rerun the faulting instruction having not fixed it up, and
get a repeat fault which this time wins the race with the NMI and
doesn't corrupt CR2, and gets fixed up properly.
It's not just CR2 which is a problem; DR6 and XFD_ERR. (the other
registers which have automatic side effects from exception delivery).
Really, the NMI handler needs to preserve the registers it potentially
clobbers, and that still requires the NMI handler doing it in assembly
before entering C.
~Andrew
next prev parent reply other threads:[~2026-05-14 19:49 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-13 16:12 [PATCH] x86/entry: Read CR2 in asm entry stub to redcue NMI clobbering window Rik van Riel
2026-05-13 16:31 ` Dave Hansen
2026-05-13 16:43 ` Rik van Riel
2026-05-13 17:12 ` Dave Hansen
2026-05-14 19:49 ` Andrew Cooper [this message]
2026-05-14 19:55 ` Dave Hansen
2026-05-14 18:09 ` kernel test robot
2026-05-14 22:54 ` kernel test robot
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