* [PATCH] irqchip/gic-v4.1: Wait for completion of redistributor's INVALL operation
@ 2020-03-02 9:21 ` Zenghui Yu
0 siblings, 0 replies; 7+ messages in thread
From: Zenghui Yu @ 2020-03-02 9:21 UTC (permalink / raw)
To: linux-kernel, maz
Cc: kvmarm, tglx, jason, wanghaibin.wang, linux-arm-kernel,
Zenghui Yu
In GICv4.1, we emulate a guest-issued INVALL command by a direct write
to GICR_INVALLR. Before we finish the emulation and go back to guest,
let's make sure the physical invalidate operation is actually completed
and no stale data will be left in redistributor. Per the specification,
this can be achieved by polling the GICR_SYNCR.Busy bit (to zero).
Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
---
drivers/irqchip/irq-gic-v3-its.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 83b1186ffcad..fc8c2970cee4 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -3784,6 +3784,8 @@ static void its_vpe_4_1_invall(struct its_vpe *vpe)
/* Target the redistributor this vPE is currently known on */
rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
gic_write_lpir(val, rdbase + GICR_INVALLR);
+
+ wait_for_syncr(rdbase);
}
static int its_vpe_4_1_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
--
2.19.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH] irqchip/gic-v4.1: Wait for completion of redistributor's INVALL operation
@ 2020-03-02 9:21 ` Zenghui Yu
0 siblings, 0 replies; 7+ messages in thread
From: Zenghui Yu @ 2020-03-02 9:21 UTC (permalink / raw)
To: linux-kernel, maz
Cc: jason, Zenghui Yu, wanghaibin.wang, tglx, kvmarm,
linux-arm-kernel
In GICv4.1, we emulate a guest-issued INVALL command by a direct write
to GICR_INVALLR. Before we finish the emulation and go back to guest,
let's make sure the physical invalidate operation is actually completed
and no stale data will be left in redistributor. Per the specification,
this can be achieved by polling the GICR_SYNCR.Busy bit (to zero).
Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
---
drivers/irqchip/irq-gic-v3-its.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 83b1186ffcad..fc8c2970cee4 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -3784,6 +3784,8 @@ static void its_vpe_4_1_invall(struct its_vpe *vpe)
/* Target the redistributor this vPE is currently known on */
rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
gic_write_lpir(val, rdbase + GICR_INVALLR);
+
+ wait_for_syncr(rdbase);
}
static int its_vpe_4_1_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
--
2.19.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH] irqchip/gic-v4.1: Wait for completion of redistributor's INVALL operation
2020-03-02 9:21 ` Zenghui Yu
(?)
@ 2020-03-02 12:12 ` Marc Zyngier
-1 siblings, 0 replies; 7+ messages in thread
From: Marc Zyngier @ 2020-03-02 12:12 UTC (permalink / raw)
To: Zenghui Yu; +Cc: jason, linux-kernel, tglx, kvmarm, linux-arm-kernel
On 2020-03-02 09:21, Zenghui Yu wrote:
> In GICv4.1, we emulate a guest-issued INVALL command by a direct write
> to GICR_INVALLR. Before we finish the emulation and go back to guest,
> let's make sure the physical invalidate operation is actually completed
> and no stale data will be left in redistributor. Per the specification,
> this can be achieved by polling the GICR_SYNCR.Busy bit (to zero).
>
> Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
> ---
> drivers/irqchip/irq-gic-v3-its.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/irqchip/irq-gic-v3-its.c
> b/drivers/irqchip/irq-gic-v3-its.c
> index 83b1186ffcad..fc8c2970cee4 100644
> --- a/drivers/irqchip/irq-gic-v3-its.c
> +++ b/drivers/irqchip/irq-gic-v3-its.c
> @@ -3784,6 +3784,8 @@ static void its_vpe_4_1_invall(struct its_vpe
> *vpe)
> /* Target the redistributor this vPE is currently known on */
> rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
> gic_write_lpir(val, rdbase + GICR_INVALLR);
> +
> + wait_for_syncr(rdbase);
> }
>
> static int its_vpe_4_1_set_vcpu_affinity(struct irq_data *d, void
> *vcpu_info)
Yup, well spotted. I'll add that to the series.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
_______________________________________________
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kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH] irqchip/gic-v4.1: Wait for completion of redistributor's INVALL operation
@ 2020-03-02 12:12 ` Marc Zyngier
0 siblings, 0 replies; 7+ messages in thread
From: Marc Zyngier @ 2020-03-02 12:12 UTC (permalink / raw)
To: Zenghui Yu
Cc: linux-kernel, kvmarm, tglx, jason, wanghaibin.wang,
linux-arm-kernel
On 2020-03-02 09:21, Zenghui Yu wrote:
> In GICv4.1, we emulate a guest-issued INVALL command by a direct write
> to GICR_INVALLR. Before we finish the emulation and go back to guest,
> let's make sure the physical invalidate operation is actually completed
> and no stale data will be left in redistributor. Per the specification,
> this can be achieved by polling the GICR_SYNCR.Busy bit (to zero).
>
> Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
> ---
> drivers/irqchip/irq-gic-v3-its.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/irqchip/irq-gic-v3-its.c
> b/drivers/irqchip/irq-gic-v3-its.c
> index 83b1186ffcad..fc8c2970cee4 100644
> --- a/drivers/irqchip/irq-gic-v3-its.c
> +++ b/drivers/irqchip/irq-gic-v3-its.c
> @@ -3784,6 +3784,8 @@ static void its_vpe_4_1_invall(struct its_vpe
> *vpe)
> /* Target the redistributor this vPE is currently known on */
> rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
> gic_write_lpir(val, rdbase + GICR_INVALLR);
> +
> + wait_for_syncr(rdbase);
> }
>
> static int its_vpe_4_1_set_vcpu_affinity(struct irq_data *d, void
> *vcpu_info)
Yup, well spotted. I'll add that to the series.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH] irqchip/gic-v4.1: Wait for completion of redistributor's INVALL operation
@ 2020-03-02 12:12 ` Marc Zyngier
0 siblings, 0 replies; 7+ messages in thread
From: Marc Zyngier @ 2020-03-02 12:12 UTC (permalink / raw)
To: Zenghui Yu
Cc: jason, linux-kernel, wanghaibin.wang, tglx, kvmarm,
linux-arm-kernel
On 2020-03-02 09:21, Zenghui Yu wrote:
> In GICv4.1, we emulate a guest-issued INVALL command by a direct write
> to GICR_INVALLR. Before we finish the emulation and go back to guest,
> let's make sure the physical invalidate operation is actually completed
> and no stale data will be left in redistributor. Per the specification,
> this can be achieved by polling the GICR_SYNCR.Busy bit (to zero).
>
> Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
> ---
> drivers/irqchip/irq-gic-v3-its.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/irqchip/irq-gic-v3-its.c
> b/drivers/irqchip/irq-gic-v3-its.c
> index 83b1186ffcad..fc8c2970cee4 100644
> --- a/drivers/irqchip/irq-gic-v3-its.c
> +++ b/drivers/irqchip/irq-gic-v3-its.c
> @@ -3784,6 +3784,8 @@ static void its_vpe_4_1_invall(struct its_vpe
> *vpe)
> /* Target the redistributor this vPE is currently known on */
> rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
> gic_write_lpir(val, rdbase + GICR_INVALLR);
> +
> + wait_for_syncr(rdbase);
> }
>
> static int its_vpe_4_1_set_vcpu_affinity(struct irq_data *d, void
> *vcpu_info)
Yup, well spotted. I'll add that to the series.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 7+ messages in thread
* [tip: irq/core] irqchip/gic-v4.1: Wait for completion of redistributor's INVALL operation
2020-03-02 9:21 ` Zenghui Yu
` (2 preceding siblings ...)
(?)
@ 2020-03-29 20:26 ` tip-bot2 for Zenghui Yu
-1 siblings, 0 replies; 7+ messages in thread
From: tip-bot2 for Zenghui Yu @ 2020-03-29 20:26 UTC (permalink / raw)
To: linux-tip-commits; +Cc: Zenghui Yu, Marc Zyngier, Eric Auger, x86, LKML
The following commit has been merged into the irq/core branch of tip:
Commit-ID: b978c25f6ee7d4c79cbe918eed684e53887ec001
Gitweb: https://git.kernel.org/tip/b978c25f6ee7d4c79cbe918eed684e53887ec001
Author: Zenghui Yu <yuzenghui@huawei.com>
AuthorDate: Wed, 04 Mar 2020 20:33:11
Committer: Marc Zyngier <maz@kernel.org>
CommitterDate: Fri, 20 Mar 2020 17:48:09
irqchip/gic-v4.1: Wait for completion of redistributor's INVALL operation
In GICv4.1, we emulate a guest-issued INVALL command by a direct write
to GICR_INVALLR. Before we finish the emulation and go back to guest,
let's make sure the physical invalidate operation is actually completed
and no stale data will be left in redistributor. Per the specification,
this can be achieved by polling the GICR_SYNCR.Busy bit (to zero).
Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Link: https://lore.kernel.org/r/20200302092145.899-1-yuzenghui@huawei.com
Link: https://lore.kernel.org/r/20200304203330.4967-5-maz@kernel.org
---
drivers/irqchip/irq-gic-v3-its.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 1af7139..c843702 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -3827,6 +3827,8 @@ static void its_vpe_4_1_invall(struct its_vpe *vpe)
/* Target the redistributor this vPE is currently known on */
rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
gic_write_lpir(val, rdbase + GICR_INVALLR);
+
+ wait_for_syncr(rdbase);
}
static int its_vpe_4_1_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
^ permalink raw reply related [flat|nested] 7+ messages in thread