[PATCH 1/5] instdone: Fix fallthroughs to invalid instdone bits on newer hardware.

[PATCH 1/5] instdone: Fix fallthroughs to invalid instdone bits on newer hardware.

[Eric Anholt]

---
 lib/instdone.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/lib/instdone.c b/lib/instdone.c
index 3e4d895..e12982c 100644
--- a/lib/instdone.c
+++ b/lib/instdone.c
@@ -25,6 +25,7 @@
  *
  */
 
+#include <assert.h>
 #include "instdone.h"
 
 #include "intel_chipset.h"
@@ -239,7 +240,7 @@ init_instdone_definitions(uint32_t devid)
 		gen4_instdone_bit(ILK_AM_DONE, "AM");
 
 		init_g4x_instdone1();
-	} else if (IS_965(devid)) {
+	} else if (IS_GEN4(devid)) {
 		gen4_instdone_bit(I965_ROW_0_EU_0_DONE, "Row 0, EU 0");
 		gen4_instdone_bit(I965_ROW_0_EU_1_DONE, "Row 0, EU 1");
 		gen4_instdone_bit(I965_ROW_0_EU_2_DONE, "Row 0, EU 2");
@@ -301,6 +302,7 @@ init_instdone_definitions(uint32_t devid)
 		gen3_instdone_bit(MAP_FILTER_DONE, "Map filter");
 		gen3_instdone_bit(MAP_L2_IDLE, "Map L2");
 	} else {
+		assert(IS_GEN2(devid));
 		gen3_instdone_bit(I830_GMBUS_DONE, "GMBUS");
 		gen3_instdone_bit(I830_FBC_DONE, "FBC");
 		gen3_instdone_bit(I830_BINNER_DONE, "BINNER");
-- 
1.7.9

[PATCH 2/5] instdone: Add support for one of the IVB instdone regs.

[Eric Anholt]

---
 lib/instdone.c |   24 +++++++++++++++++++++++-
 1 files changed, 23 insertions(+), 1 deletions(-)

diff --git a/lib/instdone.c b/lib/instdone.c
index e12982c..fe001ca 100644
--- a/lib/instdone.c
+++ b/lib/instdone.c
@@ -135,10 +135,32 @@ init_g4x_instdone1(void)
 	gen4_instdone1_bit(G4X_VF_DONE, "VF");
 }
 
+static void
+init_gen7_instdone(void)
+{
+	gen6_instdone1_bit(1 << 17, "TSG");
+	gen6_instdone1_bit(1 << 16, "VFE");
+	gen6_instdone1_bit(1 << 15, "GAFS");
+	gen6_instdone1_bit(1 << 14, "SVG");
+	gen6_instdone1_bit(1 << 13, "URBM");
+	gen6_instdone1_bit(1 << 12, "TDG");
+	gen6_instdone1_bit(1 << 9, "SF");
+	gen6_instdone1_bit(1 << 8, "CL");
+	gen6_instdone1_bit(1 << 7, "SOL");
+	gen6_instdone1_bit(1 << 6, "GS");
+	gen6_instdone1_bit(1 << 5, "DS");
+	gen6_instdone1_bit(1 << 4, "TE");
+	gen6_instdone1_bit(1 << 3, "HS");
+	gen6_instdone1_bit(1 << 2, "VS");
+	gen6_instdone1_bit(1 << 1, "VF");
+}
+
 void
 init_instdone_definitions(uint32_t devid)
 {
-	if (IS_GEN6(devid)) {
+	if (IS_GEN7(devid)) {
+		init_gen7_instdone();
+	} else if (IS_GEN6(devid)) {
 		/* Now called INSTDONE_1 in the docs. */
 		gen6_instdone1_bit(GEN6_MA_3_DONE, "Message Arbiter 3");
 		gen6_instdone1_bit(GEN6_EU_32_DONE, "EU 32");
-- 
1.7.9

[PATCH 3/5] reg_dumper: Refactor duplicated reg-dumping code.

[Eric Anholt]

---
 tools/intel_reg_dumper.c |   73 +++++++++++-----------------------------------
 1 files changed, 17 insertions(+), 56 deletions(-)

diff --git a/tools/intel_reg_dumper.c b/tools/intel_reg_dumper.c
index ee0ca75..c5249cb 100644
--- a/tools/intel_reg_dumper.c
+++ b/tools/intel_reg_dumper.c
@@ -1803,58 +1803,32 @@ static struct reg_debug i945gm_mi_regs[] = {
 	DEFINEREG(ECOSKPD),
 };
 
-static void
-i945_dump_mi_regs(void)
-{
-	char debug[1024];
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(i945gm_mi_regs); i++) {
-		uint32_t val = INREG(i945gm_mi_regs[i].reg);
-
-		if (i945gm_mi_regs[i].debug_output != NULL) {
-			i945gm_mi_regs[i].debug_output(debug, sizeof(debug),
-						       i945gm_mi_regs
-						       [i].reg,
-						       val);
-			printf("%30.30s: 0x%08x (%s)\n",
-			       i945gm_mi_regs[i].name,
-			       (unsigned int)val, debug);
-		} else {
-			printf("%30.30s: 0x%08x\n", i945gm_mi_regs[i].name,
-			       (unsigned int)val);
-		}
-	}
-}
+#define intel_dump_regs(regs) _intel_dump_regs(regs, ARRAY_SIZE(regs))
 
 static void
-ironlake_dump_regs(void)
+_intel_dump_regs(struct reg_debug *regs, int count)
 {
 	char debug[1024];
 	int i;
 
-	for (i = 0; i < ARRAY_SIZE(ironlake_debug_regs); i++) {
-		uint32_t val = INREG(ironlake_debug_regs[i].reg);
+	for (i = 0; i < count; i++) {
+		uint32_t val = INREG(regs[i].reg);
 
-		if (ironlake_debug_regs[i].debug_output != NULL) {
-			ironlake_debug_regs[i].debug_output(debug, sizeof(debug),
-							    ironlake_debug_regs
-							    [i].reg,
-							    val);
+		if (regs[i].debug_output != NULL) {
+			regs[i].debug_output(debug, sizeof(debug), regs[i].reg, val);
 			printf("%30.30s: 0x%08x (%s)\n",
-			       ironlake_debug_regs[i].name,
+			       regs[i].name,
 			       (unsigned int)val, debug);
 		} else {
-			printf("%30.30s: 0x%08x\n", ironlake_debug_regs[i].name,
+			printf("%30.30s: 0x%08x\n", regs[i].name,
 			       (unsigned int)val);
 		}
 	}
 }
 
 static void
-intel_dump_regs(void)
+intel_dump_other_regs(void)
 {
-	char debug[1024];
 	int i;
 	int fp, dpll;
 	int disp_pipe;
@@ -1867,22 +1841,6 @@ intel_dump_regs(void)
 	int crt;
 #endif
 
-	for (i = 0; i < ARRAY_SIZE(intel_debug_regs); i++) {
-		uint32_t val = INREG(intel_debug_regs[i].reg);
-
-		if (intel_debug_regs[i].debug_output != NULL) {
-			intel_debug_regs[i].debug_output(debug, sizeof(debug),
-							 intel_debug_regs[i].reg,
-							 val);
-			printf("%20.20s: 0x%08x (%s)\n",
-			       intel_debug_regs[i].name,
-			       (unsigned int)val, debug);
-		} else {
-			printf("%20.20s: 0x%08x\n",
-			       intel_debug_regs[i].name,
-			       (unsigned int)val);
-		}
-	}
 #if 0
 	i830DumpIndexed(pScrn, "SR", 0x3c4, 0x3c5, 0, 7);
 	msr = INREG8(0x3cc);
@@ -2128,13 +2086,16 @@ int main(int argc, char** argv)
 	}
 
 	if (HAS_PCH_SPLIT(devid)) {
-		ironlake_dump_regs();
+		intel_dump_regs(ironlake_debug_regs);
 	}
 	else if (IS_945GM(devid)) {
-		i945_dump_mi_regs();
-		intel_dump_regs();
-	} else
-		intel_dump_regs();
+		intel_dump_regs(i945gm_mi_regs);
+		intel_dump_regs(intel_debug_regs);
+		intel_dump_other_regs();
+	} else {
+		intel_dump_regs(intel_debug_regs);
+		intel_dump_other_regs();
+	}
 
 	return 0;
 }
-- 
1.7.9

[PATCH 4/5] intel_reg_dumper: Add dumping of GPU turbo regs.

[Eric Anholt]

I was interested in finding why my IVB system is not getting GPU turbo
after suspend/resume.  The piece that looks weird to me is that
INTERRUPT_THRESHOLD is sitting at 0, whereas pre-suspend it's
0x12000000.
---
 lib/intel_reg.h          |   31 +++++++++++++++++++++++++++++++
 tools/intel_reg_dumper.c |   20 ++++++++++++++++++++
 2 files changed, 51 insertions(+), 0 deletions(-)

diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index c7cd857..427efee 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -3511,4 +3511,35 @@ typedef enum {
 #define RC6p_RESIDENCY_TIME         0x13810C
 #define RC6pp_RESIDENCY_TIME        0x138110
 
+#define GEN6_RPNSWREQ				0xA008
+#define GEN6_RC_VIDEO_FREQ			0xA00C
+#define GEN6_RC_CONTROL				0xA090
+#define GEN6_RP_DOWN_TIMEOUT			0xA010
+#define GEN6_RP_INTERRUPT_LIMITS		0xA014
+#define GEN6_RPSTAT1				0xA01C
+#define GEN6_RP_CONTROL				0xA024
+#define GEN6_RP_UP_THRESHOLD			0xA02C
+#define GEN6_RP_DOWN_THRESHOLD			0xA030
+#define GEN6_RP_CUR_UP_EI			0xA050
+#define GEN6_RP_CUR_UP				0xA054
+#define GEN6_RP_PREV_UP				0xA058
+#define GEN6_RP_CUR_DOWN_EI			0xA05C
+#define GEN6_RP_CUR_DOWN			0xA060
+#define GEN6_RP_PREV_DOWN			0xA064
+#define GEN6_RP_UP_EI				0xA068
+#define GEN6_RP_DOWN_EI				0xA06C
+#define GEN6_RP_IDLE_HYSTERSIS			0xA070
+#define GEN6_RC_STATE				0xA094
+#define GEN6_RC1_WAKE_RATE_LIMIT		0xA098
+#define GEN6_RC6_WAKE_RATE_LIMIT		0xA09C
+#define GEN6_RC6pp_WAKE_RATE_LIMIT		0xA0A0
+#define GEN6_RC_EVALUATION_INTERVAL		0xA0A8
+#define GEN6_RC_IDLE_HYSTERSIS			0xA0AC
+#define GEN6_RC_SLEEP				0xA0B0
+#define GEN6_RC1e_THRESHOLD			0xA0B4
+#define GEN6_RC6_THRESHOLD			0xA0B8
+#define GEN6_RC6p_THRESHOLD			0xA0BC
+#define GEN6_RC6pp_THRESHOLD			0xA0C0
+#define GEN6_PMINTRMSK				0xA168
+
 #endif /* _I810_REG_H */
diff --git a/tools/intel_reg_dumper.c b/tools/intel_reg_dumper.c
index c5249cb..9f281eb 100644
--- a/tools/intel_reg_dumper.c
+++ b/tools/intel_reg_dumper.c
@@ -1826,6 +1826,23 @@ _intel_dump_regs(struct reg_debug *regs, int count)
 	}
 }
 
+DEBUGSTRING(gen6_rp_control)
+{
+	snprintf(result, len, "%s",
+		 (val & (1 << 7)) ? "enabled" : "disabled");
+}
+
+static struct reg_debug gen6_rp_debug_regs[] = {
+	DEFINEREG2(GEN6_RP_CONTROL, gen6_rp_control),
+	DEFINEREG(GEN6_RPNSWREQ),
+	DEFINEREG(GEN6_RP_DOWN_TIMEOUT),
+	DEFINEREG(GEN6_RP_INTERRUPT_LIMITS),
+	DEFINEREG(GEN6_RP_UP_THRESHOLD),
+	DEFINEREG(GEN6_RP_UP_EI),
+	DEFINEREG(GEN6_RP_DOWN_EI),
+	DEFINEREG(GEN6_RP_IDLE_HYSTERSIS),
+};
+
 static void
 intel_dump_other_regs(void)
 {
@@ -2097,5 +2114,8 @@ int main(int argc, char** argv)
 		intel_dump_other_regs();
 	}
 
+	if (IS_GEN6(devid) || IS_GEN7(devid))
+		intel_dump_regs(gen6_rp_debug_regs);
+
 	return 0;
 }
-- 
1.7.9

Re: [PATCH 4/5] intel_reg_dumper: Add dumping of GPU turbo regs.

[Paul Menzel]

[-- Attachment #1.1: Type: text/plain, Size: 3280 bytes --]

Dear Eric,


Am Montag, den 20.02.2012, 10:04 -0800 schrieb Eric Anholt:
> I was interested in finding why my IVB system is not getting GPU turbo
> after suspend/resume.  The piece that looks weird to me is that
> INTERRUPT_THRESHOLD is sitting at 0, whereas pre-suspend it's
> 0x12000000.

are all of your patches in this series missing the Signed-off-by line?

> ---
>  lib/intel_reg.h          |   31 +++++++++++++++++++++++++++++++
>  tools/intel_reg_dumper.c |   20 ++++++++++++++++++++
>  2 files changed, 51 insertions(+), 0 deletions(-)
> 
> diff --git a/lib/intel_reg.h b/lib/intel_reg.h
> index c7cd857..427efee 100644
> --- a/lib/intel_reg.h
> +++ b/lib/intel_reg.h
> @@ -3511,4 +3511,35 @@ typedef enum {
>  #define RC6p_RESIDENCY_TIME         0x13810C
>  #define RC6pp_RESIDENCY_TIME        0x138110
>  
> +#define GEN6_RPNSWREQ				0xA008
> +#define GEN6_RC_VIDEO_FREQ			0xA00C
> +#define GEN6_RC_CONTROL				0xA090

Looking at this patch in Evolution the indentation looks off for some
entries. Like the one above.

> +#define GEN6_RP_DOWN_TIMEOUT			0xA010
> +#define GEN6_RP_INTERRUPT_LIMITS		0xA014
> +#define GEN6_RPSTAT1				0xA01C
> +#define GEN6_RP_CONTROL				0xA024

Dito.

> +#define GEN6_RP_UP_THRESHOLD			0xA02C
> +#define GEN6_RP_DOWN_THRESHOLD			0xA030
> +#define GEN6_RP_CUR_UP_EI			0xA050
> +#define GEN6_RP_CUR_UP				0xA054
> +#define GEN6_RP_PREV_UP				0xA058

Dito.

> +#define GEN6_RP_CUR_DOWN_EI			0xA05C
> +#define GEN6_RP_CUR_DOWN			0xA060
> +#define GEN6_RP_PREV_DOWN			0xA064
> +#define GEN6_RP_UP_EI				0xA068
> +#define GEN6_RP_DOWN_EI				0xA06C

Dito.

> +#define GEN6_RP_IDLE_HYSTERSIS			0xA070
> +#define GEN6_RC_STATE				0xA094
> +#define GEN6_RC1_WAKE_RATE_LIMIT		0xA098
> +#define GEN6_RC6_WAKE_RATE_LIMIT		0xA09C
> +#define GEN6_RC6pp_WAKE_RATE_LIMIT		0xA0A0
> +#define GEN6_RC_EVALUATION_INTERVAL		0xA0A8
> +#define GEN6_RC_IDLE_HYSTERSIS			0xA0AC
> +#define GEN6_RC_SLEEP				0xA0B0
> +#define GEN6_RC1e_THRESHOLD			0xA0B4
> +#define GEN6_RC6_THRESHOLD			0xA0B8
> +#define GEN6_RC6p_THRESHOLD			0xA0BC
> +#define GEN6_RC6pp_THRESHOLD			0xA0C0
> +#define GEN6_PMINTRMSK				0xA168
> +
>  #endif /* _I810_REG_H */
> diff --git a/tools/intel_reg_dumper.c b/tools/intel_reg_dumper.c
> index c5249cb..9f281eb 100644
> --- a/tools/intel_reg_dumper.c
> +++ b/tools/intel_reg_dumper.c
> @@ -1826,6 +1826,23 @@ _intel_dump_regs(struct reg_debug *regs, int count)
>  	}
>  }
>  
> +DEBUGSTRING(gen6_rp_control)
> +{
> +	snprintf(result, len, "%s",
> +		 (val & (1 << 7)) ? "enabled" : "disabled");
> +}
> +
> +static struct reg_debug gen6_rp_debug_regs[] = {
> +	DEFINEREG2(GEN6_RP_CONTROL, gen6_rp_control),
> +	DEFINEREG(GEN6_RPNSWREQ),
> +	DEFINEREG(GEN6_RP_DOWN_TIMEOUT),
> +	DEFINEREG(GEN6_RP_INTERRUPT_LIMITS),
> +	DEFINEREG(GEN6_RP_UP_THRESHOLD),
> +	DEFINEREG(GEN6_RP_UP_EI),
> +	DEFINEREG(GEN6_RP_DOWN_EI),
> +	DEFINEREG(GEN6_RP_IDLE_HYSTERSIS),
> +};
> +
>  static void
>  intel_dump_other_regs(void)
>  {
> @@ -2097,5 +2114,8 @@ int main(int argc, char** argv)
>  		intel_dump_other_regs();
>  	}
>  
> +	if (IS_GEN6(devid) || IS_GEN7(devid))
> +		intel_dump_regs(gen6_rp_debug_regs);
> +
>  	return 0;
>  }


Thanks,

Paul

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Re: [PATCH 4/5] intel_reg_dumper: Add dumping of GPU turbo regs.

[Eric Anholt]

[-- Attachment #1.1: Type: text/plain, Size: 868 bytes --]

On Mon, 20 Feb 2012 23:53:26 +0100, Paul Menzel <paulepanter@users.sourceforge.net> wrote:
> Dear Eric,
> 
> 
> Am Montag, den 20.02.2012, 10:04 -0800 schrieb Eric Anholt:
> > I was interested in finding why my IVB system is not getting GPU turbo
> > after suspend/resume.  The piece that looks weird to me is that
> > INTERRUPT_THRESHOLD is sitting at 0, whereas pre-suspend it's
> > 0x12000000.
> 
> are all of your patches in this series missing the Signed-off-by line?

Signed-off-by is a linux kernel practice.  Other projects don't require
it, though some people who write a lot of kernel code happen to -s their
other patches.

> Looking at this patch in Evolution the indentation looks off for some
> entries. Like the one above.

That will often be the case when you read a diff, since it has the extra
"+" or " " character at the start.

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[PATCH 5/5] gem_ringfill: Make this actually test that all the batches executed.

[Eric Anholt]

I was looking into some strange behavior in Mesa that looks like
batches maybe being skipped, but this test didn't catch it.
---
 tests/gem_ringfill.c |   65 ++++++++++++++++++++++++++++++++++++++++++++++---
 1 files changed, 61 insertions(+), 4 deletions(-)

diff --git a/tests/gem_ringfill.c b/tests/gem_ringfill.c
index 5050e57..685a010 100644
--- a/tests/gem_ringfill.c
+++ b/tests/gem_ringfill.c
@@ -31,6 +31,7 @@
  * catching failure to manage the ring properly near full.
  */
 
+#include <stdbool.h>
 #include <stdlib.h>
 #include <stdio.h>
 #include <string.h>
@@ -50,13 +51,17 @@
 static drm_intel_bufmgr *bufmgr;
 struct intel_batchbuffer *batch;
 static const int width = 512, height = 512;
-static const int size = 1024 * 1024;
 
 int main(int argc, char **argv)
 {
 	int fd;
 	int i;
 	drm_intel_bo *src_bo, *dst_bo;
+	uint32_t *map;
+	int fails = 0;
+	int pitch = width * 4;
+	int size = pitch * height;
+	int blits;
 
 	fd = drm_open_any();
 
@@ -67,6 +72,20 @@ int main(int argc, char **argv)
 	src_bo = drm_intel_bo_alloc(bufmgr, "src bo", size, 4096);
 	dst_bo = drm_intel_bo_alloc(bufmgr, "src bo", size, 4096);
 
+	/* Fill the src with indexes of the pixels */
+	drm_intel_bo_map(src_bo, true);
+	map = src_bo->virtual;
+	for (i = 0; i < width * height; i++)
+		map[i] = i;
+	drm_intel_bo_unmap(src_bo);
+
+	/* Fill the dst with garbage. */
+	drm_intel_bo_map(dst_bo, true);
+	map = dst_bo->virtual;
+	for (i = 0; i < width * height; i++)
+		map[i] = 0xd0d0d0d0;
+	drm_intel_bo_unmap(dst_bo);
+
 	/* The ring we've been using is 128k, and each rendering op
 	 * will use at least 8 dwords:
 	 *
@@ -82,15 +101,53 @@ int main(int argc, char **argv)
 	 * So iterate just a little more than that -- if we don't fill the ring
 	 * doing this, we aren't likely to with this test.
 	 */
-	for (i = 0; i < 128 * 1024 / (8 * 4) * 1.25; i++) {
-		intel_copy_bo(batch, dst_bo, src_bo, width, height);
+	blits = width * height;
+	for (i = 0; i < blits; i++) {
+		int x = i % width;
+		int y = i / width;
+
+		assert(y < height);
+
+		BEGIN_BATCH(8);
+		OUT_BATCH(XY_SRC_COPY_BLT_CMD |
+			  XY_SRC_COPY_BLT_WRITE_ALPHA |
+			  XY_SRC_COPY_BLT_WRITE_RGB);
+		OUT_BATCH((3 << 24) | /* 32 bits */
+			  (0xcc << 16) | /* copy ROP */
+			  pitch);
+		OUT_BATCH((y << 16) | x); /* dst x1,y1 */
+		OUT_BATCH(((y + 1) << 16) | (x + 1)); /* dst x2,y2 */
+		OUT_RELOC(dst_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
+		OUT_BATCH((y << 16) | x); /* src x1,y1 */
+		OUT_BATCH(pitch);
+		OUT_RELOC(src_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
+		ADVANCE_BATCH();
+
 		intel_batchbuffer_flush(batch);
 	}
 
+	/* verify */
+	drm_intel_bo_map(dst_bo, false);
+	map = dst_bo->virtual;
+	for (i = 0; i < blits; i++) {
+		int x = i % width;
+		int y = i / width;
+
+		if (map[i] != i) {
+
+			printf("Copy #%d at %d,%d failed: read 0x%08x\n",
+			       i, x, y, map[i]);
+
+			if (fails++ > 9)
+				exit(1);
+		}
+	}
+	drm_intel_bo_unmap(dst_bo);
+
 	intel_batchbuffer_free(batch);
 	drm_intel_bufmgr_destroy(bufmgr);
 
 	close(fd);
 
-	return 0;
+	return fails != 0;
 }
-- 
1.7.9

Re: [PATCH 5/5] gem_ringfill: Make this actually test that all the batches executed.

[Chris Wilson]

On Mon, 20 Feb 2012 10:04:02 -0800, Eric Anholt <eric@anholt.net> wrote:
> I was looking into some strange behavior in Mesa that looks like
> batches maybe being skipped, but this test didn't catch it.

Even if it doesn't yet hit the error, it looks a good step towards such
a test case.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 5/5] gem_ringfill: Make this actually test that all the batches executed.

[Chris Wilson]

On Mon, 20 Feb 2012 10:04:02 -0800, Eric Anholt <eric@anholt.net> wrote:
> I was looking into some strange behavior in Mesa that looks like
> batches maybe being skipped, but this test didn't catch it.

After a little bit of experimenting with dummy loads, the bug only
seems to manifest itself on the render ring.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 5/5] gem_ringfill: Make this actually test that all the batches executed.

[Daniel Vetter]

On Mon, Feb 20, 2012 at 10:04:02AM -0800, Eric Anholt wrote:
> I was looking into some strange behavior in Mesa that looks like
> batches maybe being skipped, but this test didn't catch it.
> ---

Nice set of patches, slurped in the entire series.

Thanks, Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
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