[PATCH v3 0/4] pinctrl: qcom: eliza: Split up some QUP function groups

[PATCH v3 0/4] pinctrl: qcom: eliza: Split up some QUP function groups

[Alexander Koskovich]

Problem with previous representation of some QUP functions in pingroups
was that if they had the same name as another function on multiple
slots on a pin, the latter one was effectively unselectable.

This series splits them up and allows boards to specify exact routing.

Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
---
Changes in v3
- Clarify commit message(s)
- Also split qup1_se4 (has same issue)
- Don't unsplit lanes that don't need to be unsplit from base group
- Link to v1: https://lore.kernel.org/r/20260420-fix-eliza-pinctrl-v2-0-b68329fd6701@pm.me

Changes in v2:
- Update bindings to reflect new split functions
- Link to v1: https://lore.kernel.org/r/20260418-fix-eliza-pinctrl-v1-1-864bf95ac83b@pm.me

---
Alexander Koskovich (4):
      dt-bindings: pinctrl: qcom,eliza-tlmm: Split QUP lane mirror alternates
      dt-bindings: pinctrl: qcom,eliza-tlmm: Split QUP1_SE4 lanes
      pinctrl: qcom: eliza: Split QUP lane mirror alternates
      pinctrl: qcom: eliza: Split QUP1_SE4 lanes

 .../bindings/pinctrl/qcom,eliza-tlmm.yaml          |  26 ++--
 drivers/pinctrl/qcom/pinctrl-eliza.c               | 162 ++++++++++++++++++---
 2 files changed, 154 insertions(+), 34 deletions(-)
---
base-commit: 90700e10d2ad61c13a5117cfa5e08d9f2e497dcc
change-id: 20260418-fix-eliza-pinctrl-b6e66dd92766

Best regards,
-- 
Alexander Koskovich <akoskovich@pm.me>

[PATCH v3 1/4] dt-bindings: pinctrl: qcom,eliza-tlmm: Split QUP lane mirror alternates

[Alexander Koskovich]

Several QUP lanes have MIRA/MIRB mirror routings that let the same lane
be muxed out on alternative GPIOs. On Eliza these were all collapsed
under the base function name (e.g. qup1_se6), which prevented boards
from selecting the mirror variants.

Add explicit function names for each mirror lane, matching the pattern
already established by qcom,sm8550-tlmm and related bindings.

Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
---
 .../bindings/pinctrl/qcom,eliza-tlmm.yaml          | 25 +++++++++++++---------
 1 file changed, 15 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml
index 282650426487..be7b4680045f 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml
@@ -86,16 +86,21 @@ $defs:
                 qdss_gpio_tracectl, qdss_gpio_tracedata, qlink_big_enable,
                 qlink_big_request, qlink_little_enable,
                 qlink_little_request, qlink_wmss, qspi0, qspi_clk,
-                qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4,
-                qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1,
-                qup2_se2, qup2_se3, qup2_se4, qup2_se5, qup2_se6,
-                qup2_se7, resout_gpio, sd_write_protect, sdc1, sdc2,
-                sdc2_fb_clk, tb_trig_sdc1, tb_trig_sdc2, tmess_prng0,
-                tmess_prng1, tmess_prng2, tmess_prng3, tsense_pwm1,
-                tsense_pwm2, tsense_pwm3, tsense_pwm4, uim0_clk,
-                uim0_data, uim0_present, uim0_reset, uim1_clk, uim1_data,
-                uim1_present, uim1_reset, usb0_hs, usb_phy, vfr_0, vfr_1,
-                vsense_trigger_mirnat, wcn_sw_ctrl ]
+                qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se2_l2_mira,
+                qup1_se2_l2_mirb, qup1_se2_l3_mira, qup1_se2_l3_mirb,
+                qup1_se3, qup1_se4, qup1_se5, qup1_se6, qup1_se6_l1_mira,
+                qup1_se6_l1_mirb, qup1_se6_l3_mira, qup1_se6_l3_mirb,
+                qup1_se7, qup1_se7_l0_mira, qup1_se7_l0_mirb,
+                qup1_se7_l1_mira, qup1_se7_l1_mirb, qup2_se0, qup2_se1,
+                qup2_se2, qup2_se3, qup2_se3_l0_mira, qup2_se3_l0_mirb,
+                qup2_se3_l1_mira, qup2_se3_l1_mirb, qup2_se4, qup2_se5,
+                qup2_se6, qup2_se7, resout_gpio, sd_write_protect, sdc1,
+                sdc2, sdc2_fb_clk, tb_trig_sdc1, tb_trig_sdc2,
+                tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3,
+                tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4,
+                uim0_clk, uim0_data, uim0_present, uim0_reset, uim1_clk,
+                uim1_data, uim1_present, uim1_reset, usb0_hs, usb_phy,
+                vfr_0, vfr_1, vsense_trigger_mirnat, wcn_sw_ctrl ]
     required:
       - pins
 

-- 
2.53.0

Re: [PATCH v3 1/4] dt-bindings: pinctrl: qcom,eliza-tlmm: Split QUP lane mirror alternates

[Krzysztof Kozlowski]

On Thu, Apr 23, 2026 at 04:43:19AM +0000, Alexander Koskovich wrote:
> Several QUP lanes have MIRA/MIRB mirror routings that let the same lane
> be muxed out on alternative GPIOs. On Eliza these were all collapsed
> under the base function name (e.g. qup1_se6), which prevented boards
> from selecting the mirror variants.
> 
> Add explicit function names for each mirror lane, matching the pattern
> already established by qcom,sm8550-tlmm and related bindings.
> 
> Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
> ---
>  .../bindings/pinctrl/qcom,eliza-tlmm.yaml          | 25 +++++++++++++---------
>  1 file changed, 15 insertions(+), 10 deletions(-)

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

[PATCH v3 2/4] dt-bindings: pinctrl: qcom,eliza-tlmm: Split QUP1_SE4 lanes

[Alexander Koskovich]

QUP1_SE4 shares GPIO_36 & GPIO_37 for both L0/L1 and L3/L2 so the
function name cannot be the same or the alternate function cannot
be selected.

Split them up into individual lane functions so boards can specify.

Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
---
 Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml
index be7b4680045f..fa0177529277 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml
@@ -88,7 +88,8 @@ $defs:
                 qlink_little_request, qlink_wmss, qspi0, qspi_clk,
                 qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se2_l2_mira,
                 qup1_se2_l2_mirb, qup1_se2_l3_mira, qup1_se2_l3_mirb,
-                qup1_se3, qup1_se4, qup1_se5, qup1_se6, qup1_se6_l1_mira,
+                qup1_se3, qup1_se4_l0, qup1_se4_l1, qup1_se4_l2,
+                qup1_se4_l3, qup1_se5, qup1_se6, qup1_se6_l1_mira,
                 qup1_se6_l1_mirb, qup1_se6_l3_mira, qup1_se6_l3_mirb,
                 qup1_se7, qup1_se7_l0_mira, qup1_se7_l0_mirb,
                 qup1_se7_l1_mira, qup1_se7_l1_mirb, qup2_se0, qup2_se1,

-- 
2.53.0

Re: [PATCH v3 2/4] dt-bindings: pinctrl: qcom,eliza-tlmm: Split QUP1_SE4 lanes

[Krzysztof Kozlowski]

On Thu, Apr 23, 2026 at 04:43:27AM +0000, Alexander Koskovich wrote:
> QUP1_SE4 shares GPIO_36 & GPIO_37 for both L0/L1 and L3/L2 so the
> function name cannot be the same or the alternate function cannot
> be selected.
> 
> Split them up into individual lane functions so boards can specify.
> 
> Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
> ---
>  Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

[PATCH v3 3/4] pinctrl: qcom: eliza: Split QUP lane mirror alternates

[Alexander Koskovich]

Several QUP lanes have MIRA/MIRB mirror routings which are collapsed
under a single function name (e.g. qup1_se6).

This is an issue because it means there are multiple functions defined
for a given pin that share the same name:

[42] = PINGROUP(42, qup1_se6, qup1_se2, qup1_se6...

So when you select pin 42 and request function qup1_se6, it will select
the first instance of it in this group, which just happens to be
QUP1_SE6_L2, making the second instance (QUP1_SE6_L1_MIRA) effectively
unreachable.

Split each of these lanes that has an alternative GPIO into their own
function so they can actually be selected, following the pattern seen
in pinctrl-sm8550.c.

Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
---
 drivers/pinctrl/qcom/pinctrl-eliza.c | 132 ++++++++++++++++++++++++++++++-----
 1 file changed, 114 insertions(+), 18 deletions(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-eliza.c b/drivers/pinctrl/qcom/pinctrl-eliza.c
index c1f756cbcdeb..8f74756771b8 100644
--- a/drivers/pinctrl/qcom/pinctrl-eliza.c
+++ b/drivers/pinctrl/qcom/pinctrl-eliza.c
@@ -563,15 +563,31 @@ enum eliza_functions {
 	msm_mux_qup1_se0,
 	msm_mux_qup1_se1,
 	msm_mux_qup1_se2,
+	msm_mux_qup1_se2_l2_mira,
+	msm_mux_qup1_se2_l2_mirb,
+	msm_mux_qup1_se2_l3_mira,
+	msm_mux_qup1_se2_l3_mirb,
 	msm_mux_qup1_se3,
 	msm_mux_qup1_se4,
 	msm_mux_qup1_se5,
 	msm_mux_qup1_se6,
+	msm_mux_qup1_se6_l1_mira,
+	msm_mux_qup1_se6_l1_mirb,
+	msm_mux_qup1_se6_l3_mira,
+	msm_mux_qup1_se6_l3_mirb,
 	msm_mux_qup1_se7,
+	msm_mux_qup1_se7_l0_mira,
+	msm_mux_qup1_se7_l0_mirb,
+	msm_mux_qup1_se7_l1_mira,
+	msm_mux_qup1_se7_l1_mirb,
 	msm_mux_qup2_se0,
 	msm_mux_qup2_se1,
 	msm_mux_qup2_se2,
 	msm_mux_qup2_se3,
+	msm_mux_qup2_se3_l0_mira,
+	msm_mux_qup2_se3_l0_mirb,
+	msm_mux_qup2_se3_l1_mira,
+	msm_mux_qup2_se3_l1_mirb,
 	msm_mux_qup2_se4,
 	msm_mux_qup2_se5,
 	msm_mux_qup2_se6,
@@ -978,7 +994,23 @@ static const char *const qup1_se1_groups[] = {
 };
 
 static const char *const qup1_se2_groups[] = {
-	"gpio52", "gpio53", "gpio54", "gpio52", "gpio55", "gpio53", "gpio40", "gpio42", "gpio30",
+	"gpio52", "gpio53", "gpio40", "gpio42", "gpio30",
+};
+
+static const char *const qup1_se2_l2_mira_groups[] = {
+	"gpio54",
+};
+
+static const char *const qup1_se2_l2_mirb_groups[] = {
+	"gpio52",
+};
+
+static const char *const qup1_se2_l3_mira_groups[] = {
+	"gpio55",
+};
+
+static const char *const qup1_se2_l3_mirb_groups[] = {
+	"gpio53",
 };
 
 static const char *const qup1_se3_groups[] = {
@@ -994,11 +1026,43 @@ static const char *const qup1_se5_groups[] = {
 };
 
 static const char *const qup1_se6_groups[] = {
-	"gpio40", "gpio42", "gpio54", "gpio42", "gpio40", "gpio55",
+	"gpio40", "gpio42",
+};
+
+static const char *const qup1_se6_l1_mira_groups[] = {
+	"gpio42",
+};
+
+static const char *const qup1_se6_l1_mirb_groups[] = {
+	"gpio54",
+};
+
+static const char *const qup1_se6_l3_mira_groups[] = {
+	"gpio40",
+};
+
+static const char *const qup1_se6_l3_mirb_groups[] = {
+	"gpio55",
 };
 
 static const char *const qup1_se7_groups[] = {
-	"gpio81", "gpio78", "gpio80", "gpio114", "gpio114", "gpio78",
+	"gpio78", "gpio114",
+};
+
+static const char *const qup1_se7_l0_mira_groups[] = {
+	"gpio81",
+};
+
+static const char *const qup1_se7_l0_mirb_groups[] = {
+	"gpio78",
+};
+
+static const char *const qup1_se7_l1_mira_groups[] = {
+	"gpio80",
+};
+
+static const char *const qup1_se7_l1_mirb_groups[] = {
+	"gpio114",
 };
 
 static const char *const qup2_se0_groups[] = {
@@ -1014,7 +1078,23 @@ static const char *const qup2_se2_groups[] = {
 };
 
 static const char *const qup2_se3_groups[] = {
-	"gpio79", "gpio116", "gpio97", "gpio100", "gpio100", "gpio116",
+	"gpio100", "gpio116",
+};
+
+static const char *const qup2_se3_l0_mira_groups[] = {
+	"gpio79",
+};
+
+static const char *const qup2_se3_l0_mirb_groups[] = {
+	"gpio116",
+};
+
+static const char *const qup2_se3_l1_mira_groups[] = {
+	"gpio97",
+};
+
+static const char *const qup2_se3_l1_mirb_groups[] = {
+	"gpio100",
 };
 
 static const char *const qup2_se4_groups[] = {
@@ -1236,15 +1316,31 @@ static const struct pinfunction eliza_functions[] = {
 	MSM_PIN_FUNCTION(qup1_se0),
 	MSM_PIN_FUNCTION(qup1_se1),
 	MSM_PIN_FUNCTION(qup1_se2),
+	MSM_PIN_FUNCTION(qup1_se2_l2_mira),
+	MSM_PIN_FUNCTION(qup1_se2_l2_mirb),
+	MSM_PIN_FUNCTION(qup1_se2_l3_mira),
+	MSM_PIN_FUNCTION(qup1_se2_l3_mirb),
 	MSM_PIN_FUNCTION(qup1_se3),
 	MSM_PIN_FUNCTION(qup1_se4),
 	MSM_PIN_FUNCTION(qup1_se5),
 	MSM_PIN_FUNCTION(qup1_se6),
+	MSM_PIN_FUNCTION(qup1_se6_l1_mira),
+	MSM_PIN_FUNCTION(qup1_se6_l1_mirb),
+	MSM_PIN_FUNCTION(qup1_se6_l3_mira),
+	MSM_PIN_FUNCTION(qup1_se6_l3_mirb),
 	MSM_PIN_FUNCTION(qup1_se7),
+	MSM_PIN_FUNCTION(qup1_se7_l0_mira),
+	MSM_PIN_FUNCTION(qup1_se7_l0_mirb),
+	MSM_PIN_FUNCTION(qup1_se7_l1_mira),
+	MSM_PIN_FUNCTION(qup1_se7_l1_mirb),
 	MSM_PIN_FUNCTION(qup2_se0),
 	MSM_PIN_FUNCTION(qup2_se1),
 	MSM_PIN_FUNCTION(qup2_se2),
 	MSM_PIN_FUNCTION(qup2_se3),
+	MSM_PIN_FUNCTION(qup2_se3_l0_mira),
+	MSM_PIN_FUNCTION(qup2_se3_l0_mirb),
+	MSM_PIN_FUNCTION(qup2_se3_l1_mira),
+	MSM_PIN_FUNCTION(qup2_se3_l1_mirb),
 	MSM_PIN_FUNCTION(qup2_se4),
 	MSM_PIN_FUNCTION(qup2_se5),
 	MSM_PIN_FUNCTION(qup2_se6),
@@ -1326,9 +1422,9 @@ static const struct msm_pingroup eliza_groups[] = {
 	[37] = PINGROUP(37, qup1_se4, qup1_se4, ibi_i3c, _, _, _, _, _, _, _, _),
 	[38] = PINGROUP(38, _, _, _, _, _, _, _, _, _, _, _),
 	[39] = PINGROUP(39, _, _, _, _, _, _, _, _, _, _, _),
-	[40] = PINGROUP(40, qup1_se6, qup1_se2, qup1_se6, _, qdss_gpio_tracedata, gnss_adc1, ddr_pxi1, _, _, _, _),
+	[40] = PINGROUP(40, qup1_se6, qup1_se2, qup1_se6_l3_mira, _, qdss_gpio_tracedata, gnss_adc1, ddr_pxi1, _, _, _, _),
 	[41] = PINGROUP(41, _, _, _, _, _, _, _, _, _, _, _),
-	[42] = PINGROUP(42, qup1_se6, qup1_se2, qup1_se6, qdss_gpio_tracedata, gnss_adc0, ddr_pxi1, _, _, _, _, _),
+	[42] = PINGROUP(42, qup1_se6, qup1_se2, qup1_se6_l1_mira, qdss_gpio_tracedata, gnss_adc0, ddr_pxi1, _, _, _, _, _),
 	[43] = PINGROUP(43, _, _, _, _, _, _, _, _, _, _, _),
 	[44] = PINGROUP(44, qup1_se3, _, _, _, _, _, _, _, _, _, _),
 	[45] = PINGROUP(45, qup1_se3, _, _, _, _, _, _, _, _, _, _),
@@ -1338,10 +1434,10 @@ static const struct msm_pingroup eliza_groups[] = {
 	[49] = PINGROUP(49, _, _, _, _, _, _, _, _, _, _, _),
 	[50] = PINGROUP(50, sdc2_fb_clk, _, _, _, _, _, _, _, _, _, _),
 	[51] = PINGROUP(51, _, _, _, _, _, _, _, _, _, _, _),
-	[52] = PINGROUP(52, qup1_se2, pcie1_clk_req_n, qup1_se2, ddr_bist_complete, qdss_gpio_tracedata, _, vsense_trigger_mirnat, _, _, _, _),
-	[53] = PINGROUP(53, qup1_se2, qup1_se2, gcc_gp1, ddr_bist_stop, _, qdss_gpio_tracedata, _, _, _, _, _),
-	[54] = PINGROUP(54, qup1_se2, qup1_se6, qdss_gpio_tracedata, gnss_adc1, atest_usb, ddr_pxi0, _, _, _, _, _),
-	[55] = PINGROUP(55, qup1_se2, dp0_hot, qup1_se6, _, gnss_adc0, atest_usb, ddr_pxi0, _, _, _, _),
+	[52] = PINGROUP(52, qup1_se2, pcie1_clk_req_n, qup1_se2_l2_mirb, ddr_bist_complete, qdss_gpio_tracedata, _, vsense_trigger_mirnat, _, _, _, _),
+	[53] = PINGROUP(53, qup1_se2, qup1_se2_l3_mirb, gcc_gp1, ddr_bist_stop, _, qdss_gpio_tracedata, _, _, _, _, _),
+	[54] = PINGROUP(54, qup1_se2_l2_mira, qup1_se6_l1_mirb, qdss_gpio_tracedata, gnss_adc1, atest_usb, ddr_pxi0, _, _, _, _, _),
+	[55] = PINGROUP(55, qup1_se2_l3_mira, dp0_hot, qup1_se6_l3_mirb, _, gnss_adc0, atest_usb, ddr_pxi0, _, _, _, _),
 	[56] = PINGROUP(56, usb0_hs, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4, _, _, _, _, _, _),
 	[57] = PINGROUP(57, sd_write_protect, _, _, _, _, _, _, _, _, _, _),
 	[58] = PINGROUP(58, _, _, _, _, _, _, _, _, _, _, _),
@@ -1364,10 +1460,10 @@ static const struct msm_pingroup eliza_groups[] = {
 	[75] = PINGROUP(75, cci_i2c_scl, _, phase_flag, _, _, _, _, _, _, _, _),
 	[76] = PINGROUP(76, cci_i2c_sda, cci_timer, prng_rosc2, _, phase_flag, _, _, _, _, _, _),
 	[77] = PINGROUP(77, cci_i2c_scl, jitter_bist, _, _, _, _, _, _, _, _, _),
-	[78] = PINGROUP(78, qup1_se7, qup1_se7, _, phase_flag, _, _, _, _, _, _, _),
-	[79] = PINGROUP(79, qspi0, mdp_vsync, qup2_se3, _, _, _, _, _, _, _, _),
-	[80] = PINGROUP(80, pcie0_clk_req_n, qup1_se7, _, phase_flag, _, _, _, _, _, _, _),
-	[81] = PINGROUP(81, wcn_sw_ctrl, qup1_se7, dbg_out_clk, _, _, _, _, _, _, _, _),
+	[78] = PINGROUP(78, qup1_se7, qup1_se7_l0_mirb, _, phase_flag, _, _, _, _, _, _, _),
+	[79] = PINGROUP(79, qspi0, mdp_vsync, qup2_se3_l0_mira, _, _, _, _, _, _, _, _),
+	[80] = PINGROUP(80, pcie0_clk_req_n, qup1_se7_l1_mira, _, phase_flag, _, _, _, _, _, _, _),
+	[81] = PINGROUP(81, wcn_sw_ctrl, qup1_se7_l0_mira, dbg_out_clk, _, _, _, _, _, _, _, _),
 	[82] = PINGROUP(82, _, _, _, _, _, _, _, _, _, _, _),
 	[83] = PINGROUP(83, _, _, _, _, _, _, _, _, _, _, _),
 	[84] = PINGROUP(84, uim0_data, _, _, _, _, _, _, _, _, _, _),
@@ -1383,10 +1479,10 @@ static const struct msm_pingroup eliza_groups[] = {
 	[94] = PINGROUP(94, qlink_wmss, _, _, _, _, _, _, _, _, _, _),
 	[95] = PINGROUP(95, qlink_big_request, _, _, _, _, _, _, _, _, _, _),
 	[96] = PINGROUP(96, qlink_big_enable, _, _, _, _, _, _, _, _, _, _),
-	[97] = PINGROUP(97, uim1_data, qspi0, qup2_se3, _, _, _, _, _, _, _, _),
+	[97] = PINGROUP(97, uim1_data, qspi0, qup2_se3_l1_mira, _, _, _, _, _, _, _, _),
 	[98] = PINGROUP(98, uim1_clk, qspi0, _, _, _, _, _, _, _, _, _),
 	[99] = PINGROUP(99, uim1_reset, qspi0, _, _, _, _, _, _, _, _, _),
-	[100] = PINGROUP(100, uim1_present, qspi0, qup2_se3, coex_uart2_tx, qup2_se3, mdp_vsync, _, _, _, _, _),
+	[100] = PINGROUP(100, uim1_present, qspi0, qup2_se3, coex_uart2_tx, qup2_se3_l1_mirb, mdp_vsync, _, _, _, _, _),
 	[101] = PINGROUP(101, _, _, _, _, _, _, _, _, _, _, _),
 	[102] = PINGROUP(102, _, _, _, _, _, _, _, _, _, _, _),
 	[103] = PINGROUP(103, _, _, _, _, _, _, _, _, _, _, _),
@@ -1400,9 +1496,9 @@ static const struct msm_pingroup eliza_groups[] = {
 	[111] = PINGROUP(111, coex_uart1_tx, _, _, _, _, _, _, _, _, _, _),
 	[112] = PINGROUP(112, coex_uart1_rx, _, _, _, _, _, _, _, _, _, _),
 	[113] = PINGROUP(113, _, nav_gpio3, _, _, _, _, _, _, _, _, _),
-	[114] = PINGROUP(114, qup1_se7, qup1_se7, _, qdss_gpio_tracedata, _, _, _, _, _, _, _),
+	[114] = PINGROUP(114, qup1_se7, qup1_se7_l1_mirb, _, qdss_gpio_tracedata, _, _, _, _, _, _, _),
 	[115] = PINGROUP(115, _, qspi0, cci_async_in, _, _, _, _, _, _, _, _),
-	[116] = PINGROUP(116, qspi0, coex_uart2_rx, qup2_se3, qup2_se3, _, _, _, _, _, _, _),
+	[116] = PINGROUP(116, qspi0, coex_uart2_rx, qup2_se3, qup2_se3_l0_mirb, _, _, _, _, _, _, _),
 	[117] = PINGROUP(117, nav_gpio1, _, vfr_1, _, _, _, _, _, _, _, _),
 	[118] = PINGROUP(118, nav_gpio2, _, _, _, _, _, _, _, _, _, _),
 	[119] = PINGROUP(119, nav_gpio0, _, _, _, _, _, _, _, _, _, _),

-- 
2.53.0

Re: [PATCH v3 3/4] pinctrl: qcom: eliza: Split QUP lane mirror alternates

[Konrad Dybcio]

On 4/23/26 6:43 AM, Alexander Koskovich wrote:
> Several QUP lanes have MIRA/MIRB mirror routings which are collapsed
> under a single function name (e.g. qup1_se6).
> 
> This is an issue because it means there are multiple functions defined
> for a given pin that share the same name:
> 
> [42] = PINGROUP(42, qup1_se6, qup1_se2, qup1_se6...
> 
> So when you select pin 42 and request function qup1_se6, it will select
> the first instance of it in this group, which just happens to be
> QUP1_SE6_L2, making the second instance (QUP1_SE6_L1_MIRA) effectively
> unreachable.
> 
> Split each of these lanes that has an alternative GPIO into their own
> function so they can actually be selected, following the pattern seen
> in pinctrl-sm8550.c.
> 
> Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

[PATCH v3 4/4] pinctrl: qcom: eliza: Split QUP1_SE4 lanes

[Alexander Koskovich]

QUP1_SE4 shares GPIO_36 & GPIO_37 for both L0/L1 and L3/L2 so the
function name cannot be the same or the alternate function cannot
be selected.

Split them up into individual lane functions so boards can specify.

Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
---
 drivers/pinctrl/qcom/pinctrl-eliza.c | 30 ++++++++++++++++++++++++------
 1 file changed, 24 insertions(+), 6 deletions(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-eliza.c b/drivers/pinctrl/qcom/pinctrl-eliza.c
index 8f74756771b8..40e263e35b45 100644
--- a/drivers/pinctrl/qcom/pinctrl-eliza.c
+++ b/drivers/pinctrl/qcom/pinctrl-eliza.c
@@ -568,7 +568,10 @@ enum eliza_functions {
 	msm_mux_qup1_se2_l3_mira,
 	msm_mux_qup1_se2_l3_mirb,
 	msm_mux_qup1_se3,
-	msm_mux_qup1_se4,
+	msm_mux_qup1_se4_l0,
+	msm_mux_qup1_se4_l1,
+	msm_mux_qup1_se4_l2,
+	msm_mux_qup1_se4_l3,
 	msm_mux_qup1_se5,
 	msm_mux_qup1_se6,
 	msm_mux_qup1_se6_l1_mira,
@@ -1017,8 +1020,20 @@ static const char *const qup1_se3_groups[] = {
 	"gpio44", "gpio45", "gpio46", "gpio47",
 };
 
-static const char *const qup1_se4_groups[] = {
-	"gpio36", "gpio37", "gpio37", "gpio36",
+static const char *const qup1_se4_l0_groups[] = {
+	"gpio36",
+};
+
+static const char *const qup1_se4_l1_groups[] = {
+	"gpio37",
+};
+
+static const char *const qup1_se4_l2_groups[] = {
+	"gpio37",
+};
+
+static const char *const qup1_se4_l3_groups[] = {
+	"gpio36",
 };
 
 static const char *const qup1_se5_groups[] = {
@@ -1321,7 +1336,10 @@ static const struct pinfunction eliza_functions[] = {
 	MSM_PIN_FUNCTION(qup1_se2_l3_mira),
 	MSM_PIN_FUNCTION(qup1_se2_l3_mirb),
 	MSM_PIN_FUNCTION(qup1_se3),
-	MSM_PIN_FUNCTION(qup1_se4),
+	MSM_PIN_FUNCTION(qup1_se4_l0),
+	MSM_PIN_FUNCTION(qup1_se4_l1),
+	MSM_PIN_FUNCTION(qup1_se4_l2),
+	MSM_PIN_FUNCTION(qup1_se4_l3),
 	MSM_PIN_FUNCTION(qup1_se5),
 	MSM_PIN_FUNCTION(qup1_se6),
 	MSM_PIN_FUNCTION(qup1_se6_l1_mira),
@@ -1418,8 +1436,8 @@ static const struct msm_pingroup eliza_groups[] = {
 	[33] = PINGROUP(33, qup1_se1, ibi_i3c, host2wlan_sol, gcc_gp3, _, _, _, _, _, _, _),
 	[34] = PINGROUP(34, qup1_se1, qup1_se5, tb_trig_sdc1, ddr_bist_start, qdss_gpio_tracedata, _, _, _, _, _, _),
 	[35] = PINGROUP(35, qup1_se1, qup1_se5, tb_trig_sdc2, gcc_gp2, qdss_gpio_tracedata, _, _, _, _, _, _),
-	[36] = PINGROUP(36, qup1_se4, qup1_se4, ibi_i3c, _, _, _, _, _, _, _, _),
-	[37] = PINGROUP(37, qup1_se4, qup1_se4, ibi_i3c, _, _, _, _, _, _, _, _),
+	[36] = PINGROUP(36, qup1_se4_l0, qup1_se4_l3, ibi_i3c, _, _, _, _, _, _, _, _),
+	[37] = PINGROUP(37, qup1_se4_l1, qup1_se4_l2, ibi_i3c, _, _, _, _, _, _, _, _),
 	[38] = PINGROUP(38, _, _, _, _, _, _, _, _, _, _, _),
 	[39] = PINGROUP(39, _, _, _, _, _, _, _, _, _, _, _),
 	[40] = PINGROUP(40, qup1_se6, qup1_se2, qup1_se6_l3_mira, _, qdss_gpio_tracedata, gnss_adc1, ddr_pxi1, _, _, _, _),

-- 
2.53.0

Re: [PATCH v3 4/4] pinctrl: qcom: eliza: Split QUP1_SE4 lanes

[Konrad Dybcio]

On 4/23/26 6:43 AM, Alexander Koskovich wrote:
> QUP1_SE4 shares GPIO_36 & GPIO_37 for both L0/L1 and L3/L2 so the
> function name cannot be the same or the alternate function cannot
> be selected.
> 
> Split them up into individual lane functions so boards can specify.
> 
> Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH v3 4/4] pinctrl: qcom: eliza: Split QUP1_SE4 lanes

[Abel Vesa]

On 26-04-23 04:43:46, Alexander Koskovich wrote:
> QUP1_SE4 shares GPIO_36 & GPIO_37 for both L0/L1 and L3/L2 so the
> function name cannot be the same or the alternate function cannot
> be selected.
> 
> Split them up into individual lane functions so boards can specify.
> 
> Signed-off-by: Alexander Koskovich <akoskovich@pm.me>

Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>

Re: [PATCH v3 4/4] pinctrl: qcom: eliza: Split QUP1_SE4 lanes

[Bjorn Andersson]

On Thu, Apr 23, 2026 at 04:43:46AM +0000, Alexander Koskovich wrote:
> QUP1_SE4 shares GPIO_36 & GPIO_37 for both L0/L1 and L3/L2 so the
> function name cannot be the same or the alternate function cannot
> be selected.
> 
> Split them up into individual lane functions so boards can specify.
> 

This works, but it forces the DeviceTree source author to write a state
per pin even though these are typically configured in pairs.

What we did for hawi was to use the naming: qup1_se4_01 and qup1_se4_23
to express the two possible function pairs.


I don't have any strong opinions on how to proceed with this platform
(eliza), but I'm hoping we can follow the pair-wise scheme going
forward.

Regards,
Bjorn

> Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
> ---
>  drivers/pinctrl/qcom/pinctrl-eliza.c | 30 ++++++++++++++++++++++++------
>  1 file changed, 24 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/pinctrl/qcom/pinctrl-eliza.c b/drivers/pinctrl/qcom/pinctrl-eliza.c
> index 8f74756771b8..40e263e35b45 100644
> --- a/drivers/pinctrl/qcom/pinctrl-eliza.c
> +++ b/drivers/pinctrl/qcom/pinctrl-eliza.c
> @@ -568,7 +568,10 @@ enum eliza_functions {
>  	msm_mux_qup1_se2_l3_mira,
>  	msm_mux_qup1_se2_l3_mirb,
>  	msm_mux_qup1_se3,
> -	msm_mux_qup1_se4,
> +	msm_mux_qup1_se4_l0,
> +	msm_mux_qup1_se4_l1,
> +	msm_mux_qup1_se4_l2,
> +	msm_mux_qup1_se4_l3,
>  	msm_mux_qup1_se5,
>  	msm_mux_qup1_se6,
>  	msm_mux_qup1_se6_l1_mira,
> @@ -1017,8 +1020,20 @@ static const char *const qup1_se3_groups[] = {
>  	"gpio44", "gpio45", "gpio46", "gpio47",
>  };
>  
> -static const char *const qup1_se4_groups[] = {
> -	"gpio36", "gpio37", "gpio37", "gpio36",
> +static const char *const qup1_se4_l0_groups[] = {
> +	"gpio36",
> +};
> +
> +static const char *const qup1_se4_l1_groups[] = {
> +	"gpio37",
> +};
> +
> +static const char *const qup1_se4_l2_groups[] = {
> +	"gpio37",
> +};
> +
> +static const char *const qup1_se4_l3_groups[] = {
> +	"gpio36",
>  };
>  
>  static const char *const qup1_se5_groups[] = {
> @@ -1321,7 +1336,10 @@ static const struct pinfunction eliza_functions[] = {
>  	MSM_PIN_FUNCTION(qup1_se2_l3_mira),
>  	MSM_PIN_FUNCTION(qup1_se2_l3_mirb),
>  	MSM_PIN_FUNCTION(qup1_se3),
> -	MSM_PIN_FUNCTION(qup1_se4),
> +	MSM_PIN_FUNCTION(qup1_se4_l0),
> +	MSM_PIN_FUNCTION(qup1_se4_l1),
> +	MSM_PIN_FUNCTION(qup1_se4_l2),
> +	MSM_PIN_FUNCTION(qup1_se4_l3),
>  	MSM_PIN_FUNCTION(qup1_se5),
>  	MSM_PIN_FUNCTION(qup1_se6),
>  	MSM_PIN_FUNCTION(qup1_se6_l1_mira),
> @@ -1418,8 +1436,8 @@ static const struct msm_pingroup eliza_groups[] = {
>  	[33] = PINGROUP(33, qup1_se1, ibi_i3c, host2wlan_sol, gcc_gp3, _, _, _, _, _, _, _),
>  	[34] = PINGROUP(34, qup1_se1, qup1_se5, tb_trig_sdc1, ddr_bist_start, qdss_gpio_tracedata, _, _, _, _, _, _),
>  	[35] = PINGROUP(35, qup1_se1, qup1_se5, tb_trig_sdc2, gcc_gp2, qdss_gpio_tracedata, _, _, _, _, _, _),
> -	[36] = PINGROUP(36, qup1_se4, qup1_se4, ibi_i3c, _, _, _, _, _, _, _, _),
> -	[37] = PINGROUP(37, qup1_se4, qup1_se4, ibi_i3c, _, _, _, _, _, _, _, _),
> +	[36] = PINGROUP(36, qup1_se4_l0, qup1_se4_l3, ibi_i3c, _, _, _, _, _, _, _, _),
> +	[37] = PINGROUP(37, qup1_se4_l1, qup1_se4_l2, ibi_i3c, _, _, _, _, _, _, _, _),
>  	[38] = PINGROUP(38, _, _, _, _, _, _, _, _, _, _, _),
>  	[39] = PINGROUP(39, _, _, _, _, _, _, _, _, _, _, _),
>  	[40] = PINGROUP(40, qup1_se6, qup1_se2, qup1_se6_l3_mira, _, qdss_gpio_tracedata, gnss_adc1, ddr_pxi1, _, _, _, _),
> 
> -- 
> 2.53.0
> 
> 

Re: [PATCH v3 0/4] pinctrl: qcom: eliza: Split up some QUP function groups

[Linus Walleij]

On Thu, Apr 23, 2026 at 6:43 AM Alexander Koskovich <akoskovich@pm.me> wrote:

> Problem with previous representation of some QUP functions in pingroups
> was that if they had the same name as another function on multiple
> slots on a pin, the latter one was effectively unselectable.
>
> This series splits them up and allows boards to specify exact routing.
>
> Signed-off-by: Alexander Koskovich <akoskovich@pm.me>
> ---
> Changes in v3

All patches applied for v7.2!

Yours,
Linus Walleij