From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
To: kernel test robot <lkp@intel.com>
Cc: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Stephen Boyd <swboyd@chromium.org>,
kbuild-all@lists.01.org, clang-built-linux@googlegroups.com,
linux-arm-msm@vger.kernel.org,
Douglas Anderson <dianders@chromium.org>,
linux-kernel@vger.kernel.org,
"Isaac J. Manjarres" <isaacm@codeaurora.org>
Subject: Re: [PATCH] soc: qcom: llcc: Support chipsets that can write to llcc registers
Date: Mon, 17 Aug 2020 19:38:50 +0530 [thread overview]
Message-ID: <ca48bfaf94267bc9883ad6c41de3f796@codeaurora.org> (raw)
In-Reply-To: <202008172052.mtVMHotl%lkp@intel.com>
On 2020-08-17 18:13, kernel test robot wrote:
> Hi Sai,
>
> Thank you for the patch! Perhaps something to improve:
>
> [auto build test WARNING on linux/master]
> [also build test WARNING on linus/master v5.9-rc1 next-20200817]
> [cannot apply to agross-msm/qcom/for-next]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch]
>
> url:
> https://github.com/0day-ci/linux/commits/Sai-Prakash-Ranjan/soc-qcom-llcc-Support-chipsets-that-can-write-to-llcc-registers/20200817-161342
> base:
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
> bcf876870b95592b52519ed4aafcf9d95999bc9c
> config: mips-randconfig-r006-20200817 (attached as .config)
> compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project
> de71b46a519db014ce906a39f8a0e1b235ef1568)
> reproduce (this is a W=1 build):
> wget
> https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross
> -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # install mips cross compiling tool for clang build
> # apt-get install binutils-mips-linux-gnu
> # save the attached .config to linux build tree
> COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross
> ARCH=mips
>
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <lkp@intel.com>
>
> All warnings (new ones prefixed by >>):
>
> drivers/soc/qcom/llcc-qcom.c:343:28: warning: unused variable 'np'
> [-Wunused-variable]
> const struct device_node *np = dev_of_node(&pdev->dev);
> ^
>>> drivers/soc/qcom/llcc-qcom.c:324:34: warning: unused variable
>>> 'qcom_llcc_configure_of_match' [-Wunused-const-variable]
> static const struct of_device_id qcom_llcc_configure_of_match[] = {
> ^
> 2 warnings generated.
>
Ok, W=1 build and CONFIG_OF=n, so I need __maybe_unused for
qcom_llcc_configure_of_match.
Will add and send v2.
Thanks,
Sai
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
member
of Code Aurora Forum, hosted by The Linux Foundation
WARNING: multiple messages have this Message-ID (diff)
From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
To: kbuild-all@lists.01.org
Subject: Re: [PATCH] soc: qcom: llcc: Support chipsets that can write to llcc registers
Date: Mon, 17 Aug 2020 19:38:50 +0530 [thread overview]
Message-ID: <ca48bfaf94267bc9883ad6c41de3f796@codeaurora.org> (raw)
In-Reply-To: <202008172052.mtVMHotl%lkp@intel.com>
[-- Attachment #1: Type: text/plain, Size: 2308 bytes --]
On 2020-08-17 18:13, kernel test robot wrote:
> Hi Sai,
>
> Thank you for the patch! Perhaps something to improve:
>
> [auto build test WARNING on linux/master]
> [also build test WARNING on linus/master v5.9-rc1 next-20200817]
> [cannot apply to agross-msm/qcom/for-next]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch]
>
> url:
> https://github.com/0day-ci/linux/commits/Sai-Prakash-Ranjan/soc-qcom-llcc-Support-chipsets-that-can-write-to-llcc-registers/20200817-161342
> base:
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
> bcf876870b95592b52519ed4aafcf9d95999bc9c
> config: mips-randconfig-r006-20200817 (attached as .config)
> compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project
> de71b46a519db014ce906a39f8a0e1b235ef1568)
> reproduce (this is a W=1 build):
> wget
> https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross
> -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # install mips cross compiling tool for clang build
> # apt-get install binutils-mips-linux-gnu
> # save the attached .config to linux build tree
> COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross
> ARCH=mips
>
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <lkp@intel.com>
>
> All warnings (new ones prefixed by >>):
>
> drivers/soc/qcom/llcc-qcom.c:343:28: warning: unused variable 'np'
> [-Wunused-variable]
> const struct device_node *np = dev_of_node(&pdev->dev);
> ^
>>> drivers/soc/qcom/llcc-qcom.c:324:34: warning: unused variable
>>> 'qcom_llcc_configure_of_match' [-Wunused-const-variable]
> static const struct of_device_id qcom_llcc_configure_of_match[] = {
> ^
> 2 warnings generated.
>
Ok, W=1 build and CONFIG_OF=n, so I need __maybe_unused for
qcom_llcc_configure_of_match.
Will add and send v2.
Thanks,
Sai
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
member
of Code Aurora Forum, hosted by The Linux Foundation
next prev parent reply other threads:[~2020-08-17 14:09 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-17 8:11 [PATCH] soc: qcom: llcc: Support chipsets that can write to llcc registers Sai Prakash Ranjan
2020-08-17 12:43 ` kernel test robot
2020-08-17 12:43 ` kernel test robot
2020-08-17 14:08 ` Sai Prakash Ranjan [this message]
2020-08-17 14:08 ` Sai Prakash Ranjan
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