[Qemu-devel] [PATCH 0/7] tcg-sparc improvements, v2

[Qemu-devel] [PATCH 0/7] tcg-sparc improvements, v2

[Richard Henderson]

Changes since v1:
 * Add comments for all optional instructions that aren't implemented
   on each architecture, as requested.
 * Rebase vs master.


r~


Richard Henderson (7):
  tcg-sparc: Implement neg.
  tcg-sparc: Implement not.
  tcg: Optional target implementation of ANDC.
  tcg: Optional target implementation of ORC.
  tcg-sparc: Implement ANDC.
  tcg-sparc: Implement ORC.
  tcg: Add comments for all optional instructions not implemented.

 tcg/arm/tcg-target.h    |   14 ++++++++++++++
 tcg/i386/tcg-target.h   |   12 +++++++-----
 tcg/mips/tcg-target.h   |    4 +++-
 tcg/ppc/tcg-target.h    |   10 +++++++++-
 tcg/ppc64/tcg-target.h  |   25 ++++++++++++++++++++++---
 tcg/s390/tcg-target.h   |   30 ++++++++++++++++++++++++++++++
 tcg/sparc/tcg-target.c  |   30 ++++++++++++++++++++++++++++++
 tcg/sparc/tcg-target.h  |   31 ++++++++++++++++++++++++-------
 tcg/tcg-op.h            |   22 ++++++++++++++++++++++
 tcg/tcg-opc.h           |   12 ++++++++++++
 tcg/x86_64/tcg-target.h |    6 +++++-
 11 files changed, 178 insertions(+), 18 deletions(-)

[Qemu-devel] [PATCH 1/7] tcg-sparc: Implement neg.

[Richard Henderson]

The fallback implementation of "ret = 0 - arg1" isn't ideal,
first because of the extra tcg op to load the zero, and second
because we fail to handle zero as %g0 for arg1 of the sub.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/sparc/tcg-target.c |   13 +++++++++++++
 tcg/sparc/tcg-target.h |    5 +++--
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index 5b4347a..f5cf95d 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -1234,6 +1234,10 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
         c = ARITH_UMUL;
         goto gen_arith;
 
+    OP_32_64(neg):
+	c = ARITH_SUB;
+	goto gen_arith1;
+
     case INDEX_op_div_i32:
         tcg_out_div32(s, args[0], args[1], args[2], const_args[2], 0);
         break;
@@ -1392,6 +1396,10 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
         tcg_out_arithc(s, args[0], args[1], args[2], const_args[2], c);
         break;
 
+    gen_arith1:
+	tcg_out_arithc(s, args[0], TCG_REG_G0, args[1], const_args[1], c);
+	break;
+
     default:
         fprintf(stderr, "unknown opcode 0x%x\n", opc);
         tcg_abort();
@@ -1431,6 +1439,8 @@ static const TCGTargetOpDef sparc_op_defs[] = {
     { INDEX_op_shr_i32, { "r", "r", "rJ" } },
     { INDEX_op_sar_i32, { "r", "r", "rJ" } },
 
+    { INDEX_op_neg_i32, { "r", "rJ" } },
+
     { INDEX_op_brcond_i32, { "r", "rJ" } },
     { INDEX_op_setcond_i32, { "r", "r", "rJ" } },
 
@@ -1484,6 +1494,9 @@ static const TCGTargetOpDef sparc_op_defs[] = {
     { INDEX_op_shl_i64, { "r", "r", "rJ" } },
     { INDEX_op_shr_i64, { "r", "r", "rJ" } },
     { INDEX_op_sar_i64, { "r", "r", "rJ" } },
+
+    { INDEX_op_neg_i64, { "r", "rJ" } },
+
     { INDEX_op_ext32s_i64, { "r", "ri" } },
     { INDEX_op_ext32u_i64, { "r", "ri" } },
 
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index d27ed5a..66031ba 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -91,15 +91,16 @@ enum {
 #define TCG_TARGET_HAS_div_i32
 #define TCG_TARGET_HAS_div_i64
 
+#define TCG_TARGET_HAS_neg_i32
+
 #if TCG_TARGET_REG_BITS == 64
 #define TCG_TARGET_HAS_ext32s_i64
 #define TCG_TARGET_HAS_ext32u_i64
+#define TCG_TARGET_HAS_neg_i64
 #endif
 
 //#define TCG_TARGET_HAS_bswap32_i32
 //#define TCG_TARGET_HAS_bswap64_i64
-//#define TCG_TARGET_HAS_neg_i32
-//#define TCG_TARGET_HAS_neg_i64
 
 
 /* Note: must be synced with dyngen-exec.h and Makefile.target */
-- 
1.6.6

[Qemu-devel] [PATCH 2/7] tcg-sparc: Implement not.

[Richard Henderson]

The fallback implementation of "ret = arg1 ^ -1" isn't ideal
because of the extra tcg op to load the minus one.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/sparc/tcg-target.c |    6 ++++++
 tcg/sparc/tcg-target.h |    2 ++
 2 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index f5cf95d..55c74af 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -226,6 +226,7 @@ static inline int tcg_target_const_match(tcg_target_long val,
 #define ARITH_AND  (INSN_OP(2) | INSN_OP3(0x01))
 #define ARITH_OR   (INSN_OP(2) | INSN_OP3(0x02))
 #define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12))
+#define ARITH_ORN  (INSN_OP(2) | INSN_OP3(0x06))
 #define ARITH_XOR  (INSN_OP(2) | INSN_OP3(0x03))
 #define ARITH_SUB  (INSN_OP(2) | INSN_OP3(0x04))
 #define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14))
@@ -1237,6 +1238,9 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
     OP_32_64(neg):
 	c = ARITH_SUB;
 	goto gen_arith1;
+    OP_32_64(not):
+	c = ARITH_ORN;
+	goto gen_arith1;
 
     case INDEX_op_div_i32:
         tcg_out_div32(s, args[0], args[1], args[2], const_args[2], 0);
@@ -1440,6 +1444,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
     { INDEX_op_sar_i32, { "r", "r", "rJ" } },
 
     { INDEX_op_neg_i32, { "r", "rJ" } },
+    { INDEX_op_not_i32, { "r", "rJ" } },
 
     { INDEX_op_brcond_i32, { "r", "rJ" } },
     { INDEX_op_setcond_i32, { "r", "r", "rJ" } },
@@ -1496,6 +1501,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
     { INDEX_op_sar_i64, { "r", "r", "rJ" } },
 
     { INDEX_op_neg_i64, { "r", "rJ" } },
+    { INDEX_op_not_i64, { "r", "rJ" } },
 
     { INDEX_op_ext32s_i64, { "r", "ri" } },
     { INDEX_op_ext32u_i64, { "r", "ri" } },
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index 66031ba..f5ee205 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -92,11 +92,13 @@ enum {
 #define TCG_TARGET_HAS_div_i64
 
 #define TCG_TARGET_HAS_neg_i32
+#define TCG_TARGET_HAS_not_i32
 
 #if TCG_TARGET_REG_BITS == 64
 #define TCG_TARGET_HAS_ext32s_i64
 #define TCG_TARGET_HAS_ext32u_i64
 #define TCG_TARGET_HAS_neg_i64
+#define TCG_TARGET_HAS_not_i64
 #endif
 
 //#define TCG_TARGET_HAS_bswap32_i32
-- 
1.6.6

[Qemu-devel] [PATCH 3/7] tcg: Optional target implementation of ANDC.

[Richard Henderson]

Previously ANDC was always implemented by tcg-op.h with
an explicit NOT opcode.  Allow a target implementation.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/tcg-op.h  |   11 +++++++++++
 tcg/tcg-opc.h |    6 ++++++
 2 files changed, 17 insertions(+), 0 deletions(-)

diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 13eaa5a..447878d 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -1650,20 +1650,31 @@ static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, TCGv_i64 hi
 
 static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 {
+#ifdef TCG_TARGET_HAS_andc_i32
+    tcg_gen_op3_i32(INDEX_op_andc_i32, ret, arg1, arg2);
+#else
     TCGv_i32 t0;
     t0 = tcg_temp_new_i32();
     tcg_gen_not_i32(t0, arg2);
     tcg_gen_and_i32(ret, arg1, t0);
     tcg_temp_free_i32(t0);
+#endif
 }
 
 static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 {
+#ifdef TCG_TARGET_HAS_andc_i64
+    tcg_gen_op3_i64(INDEX_op_andc_i64, ret, arg1, arg2);
+#elif defined(TCG_TARGET_HAS_andc_i32) && TCG_TARGET_REG_BITS == 32
+    tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
+    tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
+#else
     TCGv_i64 t0;
     t0 = tcg_temp_new_i64();
     tcg_gen_not_i64(t0, arg2);
     tcg_gen_and_i64(ret, arg1, t0);
     tcg_temp_free_i64(t0);
+#endif
 }
 
 static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 89db3b4..6d855a7 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -109,6 +109,9 @@ DEF2(not_i32, 1, 1, 0, 0)
 #ifdef TCG_TARGET_HAS_neg_i32
 DEF2(neg_i32, 1, 1, 0, 0)
 #endif
+#ifdef TCG_TARGET_HAS_andc_i32
+DEF2(andc_i32, 1, 2, 0, 0)
+#endif
 
 #if TCG_TARGET_REG_BITS == 64
 DEF2(mov_i64, 1, 1, 0, 0)
@@ -185,6 +188,9 @@ DEF2(not_i64, 1, 1, 0, 0)
 #ifdef TCG_TARGET_HAS_neg_i64
 DEF2(neg_i64, 1, 1, 0, 0)
 #endif
+#ifdef TCG_TARGET_HAS_andc_i64
+DEF2(andc_i64, 1, 2, 0, 0)
+#endif
 #endif
 
 /* QEMU specific */
-- 
1.6.6

[Qemu-devel] [PATCH 4/7] tcg: Optional target implementation of ORC.

[Richard Henderson]

Previously ORC was always implemented by tcg-op.h with
an explicit NOT opcode.  Allow a target implementation.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/tcg-op.h  |   11 +++++++++++
 tcg/tcg-opc.h |    6 ++++++
 2 files changed, 17 insertions(+), 0 deletions(-)

diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 447878d..6ae1760 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -1715,20 +1715,31 @@ static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 
 static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 {
+#ifdef TCG_TARGET_HAS_orc_i32
+    tcg_gen_op3_i32(INDEX_op_orc_i32, ret, arg1, arg2);
+#else
     TCGv_i32 t0;
     t0 = tcg_temp_new_i32();
     tcg_gen_not_i32(t0, arg2);
     tcg_gen_or_i32(ret, arg1, t0);
     tcg_temp_free_i32(t0);
+#endif
 }
 
 static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 {
+#ifdef TCG_TARGET_HAS_orc_i64
+    tcg_gen_op3_i64(INDEX_op_orc_i64, ret, arg1, arg2);
+#elif defined(TCG_TARGET_HAS_orc_i32) && TCG_TARGET_REG_BITS == 32
+    tcg_gen_orc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
+    tcg_gen_orc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
+#else
     TCGv_i64 t0;
     t0 = tcg_temp_new_i64();
     tcg_gen_not_i64(t0, arg2);
     tcg_gen_or_i64(ret, arg1, t0);
     tcg_temp_free_i64(t0);
+#endif
 }
 
 static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 6d855a7..34cdba5 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -112,6 +112,9 @@ DEF2(neg_i32, 1, 1, 0, 0)
 #ifdef TCG_TARGET_HAS_andc_i32
 DEF2(andc_i32, 1, 2, 0, 0)
 #endif
+#ifdef TCG_TARGET_HAS_orc_i32
+DEF2(orc_i32, 1, 2, 0, 0)
+#endif
 
 #if TCG_TARGET_REG_BITS == 64
 DEF2(mov_i64, 1, 1, 0, 0)
@@ -191,6 +194,9 @@ DEF2(neg_i64, 1, 1, 0, 0)
 #ifdef TCG_TARGET_HAS_andc_i64
 DEF2(andc_i64, 1, 2, 0, 0)
 #endif
+#ifdef TCG_TARGET_HAS_orc_i64
+DEF2(orc_i64, 1, 2, 0, 0)
+#endif
 #endif
 
 /* QEMU specific */
-- 
1.6.6

[Qemu-devel] [PATCH 5/7] tcg-sparc: Implement ANDC.

[Richard Henderson]

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/sparc/tcg-target.c |    6 ++++++
 tcg/sparc/tcg-target.h |    2 ++
 2 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index 55c74af..1ea474d 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -224,6 +224,7 @@ static inline int tcg_target_const_match(tcg_target_long val,
 #define ARITH_ADD  (INSN_OP(2) | INSN_OP3(0x00))
 #define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10))
 #define ARITH_AND  (INSN_OP(2) | INSN_OP3(0x01))
+#define ARITH_ANDN (INSN_OP(2) | INSN_OP3(0x05))
 #define ARITH_OR   (INSN_OP(2) | INSN_OP3(0x02))
 #define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12))
 #define ARITH_ORN  (INSN_OP(2) | INSN_OP3(0x06))
@@ -1216,6 +1217,9 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
     OP_32_64(and):
         c = ARITH_AND;
         goto gen_arith;
+    OP_32_64(andc):
+        c = ARITH_ANDN;
+        goto gen_arith;
     OP_32_64(or):
         c = ARITH_OR;
         goto gen_arith;
@@ -1436,6 +1440,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
     { INDEX_op_remu_i32, { "r", "r", "rJ" } },
     { INDEX_op_sub_i32, { "r", "r", "rJ" } },
     { INDEX_op_and_i32, { "r", "r", "rJ" } },
+    { INDEX_op_andc_i32, { "r", "r", "rJ" } },
     { INDEX_op_or_i32, { "r", "r", "rJ" } },
     { INDEX_op_xor_i32, { "r", "r", "rJ" } },
 
@@ -1493,6 +1498,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
     { INDEX_op_remu_i64, { "r", "r", "rJ" } },
     { INDEX_op_sub_i64, { "r", "r", "rJ" } },
     { INDEX_op_and_i64, { "r", "r", "rJ" } },
+    { INDEX_op_andc_i64, { "r", "r", "rJ" } },
     { INDEX_op_or_i64, { "r", "r", "rJ" } },
     { INDEX_op_xor_i64, { "r", "r", "rJ" } },
 
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index f5ee205..4ea0c19 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -93,12 +93,14 @@ enum {
 
 #define TCG_TARGET_HAS_neg_i32
 #define TCG_TARGET_HAS_not_i32
+#define TCG_TARGET_HAS_andc_i32
 
 #if TCG_TARGET_REG_BITS == 64
 #define TCG_TARGET_HAS_ext32s_i64
 #define TCG_TARGET_HAS_ext32u_i64
 #define TCG_TARGET_HAS_neg_i64
 #define TCG_TARGET_HAS_not_i64
+#define TCG_TARGET_HAS_andc_i64
 #endif
 
 //#define TCG_TARGET_HAS_bswap32_i32
-- 
1.6.6

[Qemu-devel] [PATCH 6/7] tcg-sparc: Implement ORC.

[Richard Henderson]

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/sparc/tcg-target.c |    5 +++++
 tcg/sparc/tcg-target.h |    2 ++
 2 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index 1ea474d..891b8c4 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -1223,6 +1223,9 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
     OP_32_64(or):
         c = ARITH_OR;
         goto gen_arith;
+    OP_32_64(orc):
+        c = ARITH_ORN;
+        goto gen_arith;
     OP_32_64(xor):
         c = ARITH_XOR;
         goto gen_arith;
@@ -1442,6 +1445,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
     { INDEX_op_and_i32, { "r", "r", "rJ" } },
     { INDEX_op_andc_i32, { "r", "r", "rJ" } },
     { INDEX_op_or_i32, { "r", "r", "rJ" } },
+    { INDEX_op_orc_i32, { "r", "r", "rJ" } },
     { INDEX_op_xor_i32, { "r", "r", "rJ" } },
 
     { INDEX_op_shl_i32, { "r", "r", "rJ" } },
@@ -1500,6 +1504,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
     { INDEX_op_and_i64, { "r", "r", "rJ" } },
     { INDEX_op_andc_i64, { "r", "r", "rJ" } },
     { INDEX_op_or_i64, { "r", "r", "rJ" } },
+    { INDEX_op_orc_i64, { "r", "r", "rJ" } },
     { INDEX_op_xor_i64, { "r", "r", "rJ" } },
 
     { INDEX_op_shl_i64, { "r", "r", "rJ" } },
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index 4ea0c19..dc68787 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -94,6 +94,7 @@ enum {
 #define TCG_TARGET_HAS_neg_i32
 #define TCG_TARGET_HAS_not_i32
 #define TCG_TARGET_HAS_andc_i32
+#define TCG_TARGET_HAS_orc_i32
 
 #if TCG_TARGET_REG_BITS == 64
 #define TCG_TARGET_HAS_ext32s_i64
@@ -101,6 +102,7 @@ enum {
 #define TCG_TARGET_HAS_neg_i64
 #define TCG_TARGET_HAS_not_i64
 #define TCG_TARGET_HAS_andc_i64
+#define TCG_TARGET_HAS_orc_i64
 #endif
 
 //#define TCG_TARGET_HAS_bswap32_i32
-- 
1.6.6

[Qemu-devel] [PATCH 7/7] tcg: Add comments for all optional instructions not implemented.

[Richard Henderson]

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/arm/tcg-target.h    |   14 ++++++++++++++
 tcg/i386/tcg-target.h   |   12 +++++++-----
 tcg/mips/tcg-target.h   |    4 +++-
 tcg/ppc/tcg-target.h    |   10 +++++++++-
 tcg/ppc64/tcg-target.h  |   25 ++++++++++++++++++++++---
 tcg/s390/tcg-target.h   |   30 ++++++++++++++++++++++++++++++
 tcg/sparc/tcg-target.h  |   22 ++++++++++++++++------
 tcg/x86_64/tcg-target.h |    6 +++++-
 8 files changed, 106 insertions(+), 17 deletions(-)

diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 71e1ec5..5eac7bf 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -63,6 +63,20 @@ enum {
 #define TCG_TARGET_STACK_ALIGN		8
 #define TCG_TARGET_CALL_STACK_OFFSET	0
 
+/* optional instructions */
+// #define TCG_TARGET_HAS_div_i32
+// #define TCG_TARGET_HAS_rot_i32
+// #define TCG_TARGET_HAS_ext8s_i32
+// #define TCG_TARGET_HAS_ext16s_i32
+// #define TCG_TARGET_HAS_ext8u_i32
+// #define TCG_TARGET_HAS_ext16u_i32
+// #define TCG_TARGET_HAS_bswap16_i32
+// #define TCG_TARGET_HAS_bswap32_i32
+// #define TCG_TARGET_HAS_not_i32
+// #define TCG_TARGET_HAS_neg_i32
+// #define TCG_TARGET_HAS_andc_i32
+// #define TCG_TARGET_HAS_orc_i32
+
 #define TCG_TARGET_HAS_GUEST_BASE
 
 enum {
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 69227c3..f97034c 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -45,15 +45,17 @@ enum {
 #define TCG_TARGET_CALL_STACK_OFFSET 0
 
 /* optional instructions */
-#define TCG_TARGET_HAS_bswap16_i32
-#define TCG_TARGET_HAS_bswap32_i32
-#define TCG_TARGET_HAS_neg_i32
-#define TCG_TARGET_HAS_not_i32
+#define TCG_TARGET_HAS_rot_i32
 #define TCG_TARGET_HAS_ext8s_i32
 #define TCG_TARGET_HAS_ext16s_i32
-#define TCG_TARGET_HAS_rot_i32
 #define TCG_TARGET_HAS_ext8u_i32
 #define TCG_TARGET_HAS_ext16u_i32
+#define TCG_TARGET_HAS_bswap16_i32
+#define TCG_TARGET_HAS_bswap32_i32
+#define TCG_TARGET_HAS_neg_i32
+#define TCG_TARGET_HAS_not_i32
+// #define TCG_TARGET_HAS_andc_i32
+// #define TCG_TARGET_HAS_orc_i32
 
 #define TCG_TARGET_HAS_GUEST_BASE
 
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index 46760a5..377b0c8 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -80,11 +80,13 @@ enum {
 /* optional instructions */
 #define TCG_TARGET_HAS_div_i32
 #define TCG_TARGET_HAS_not_i32
+#undef TCG_TARGET_HAS_rot_i32
 #undef TCG_TARGET_HAS_ext8s_i32
 #undef TCG_TARGET_HAS_ext16s_i32
 #undef TCG_TARGET_HAS_bswap32_i32
 #undef TCG_TARGET_HAS_bswap16_i32
-#undef TCG_TARGET_HAS_rot_i32
+#undef TCG_TARGET_HAS_andc_i32
+#undef TCG_TARGET_HAS_orc_i32
 
 /* optional instructions automatically implemented */
 #undef TCG_TARGET_HAS_neg_i32      /* sub  rd, zero, rt   */
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 0197e79..0deb857 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -77,10 +77,18 @@ enum {
 #endif
 
 /* optional instructions */
-#define TCG_TARGET_HAS_neg_i32
 #define TCG_TARGET_HAS_div_i32
+// #define TCG_TARGET_HAS_rot_i32
 #define TCG_TARGET_HAS_ext8s_i32
 #define TCG_TARGET_HAS_ext16s_i32
+// #define TCG_TARGET_HAS_ext8u_i32
+// #define TCG_TARGET_HAS_ext16u_i32
+// #define TCG_TARGET_HAS_bswap16_i32
+// #define TCG_TARGET_HAS_bswap32_i32
+// #define TCG_TARGET_HAS_not_i32
+#define TCG_TARGET_HAS_neg_i32
+// #define TCG_TARGET_HAS_andc_i32
+// #define TCG_TARGET_HAS_orc_i32
 
 #define TCG_AREG0 TCG_REG_R27
 #define TCG_AREG1 TCG_REG_R24
diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h
index 94b800f..8f7891b 100644
--- a/tcg/ppc64/tcg-target.h
+++ b/tcg/ppc64/tcg-target.h
@@ -68,15 +68,34 @@ enum {
 #define TCG_TARGET_CALL_STACK_OFFSET 48
 
 /* optional instructions */
-#define TCG_TARGET_HAS_neg_i32
 #define TCG_TARGET_HAS_div_i32
-#define TCG_TARGET_HAS_neg_i64
-#define TCG_TARGET_HAS_div_i64
+// #define TCG_TARGET_HAS_rot_i32
 #define TCG_TARGET_HAS_ext8s_i32
 #define TCG_TARGET_HAS_ext16s_i32
+// #define TCG_TARGET_HAS_ext8u_i32
+// #define TCG_TARGET_HAS_ext16u_i32
+// #define TCG_TARGET_HAS_bswap16_i32
+// #define TCG_TARGET_HAS_bswap32_i32
+// #define TCG_TARGET_HAS_not_i32
+#define TCG_TARGET_HAS_neg_i32
+// #define TCG_TARGET_HAS_andc_i32
+// #define TCG_TARGET_HAS_orc_i32
+
+#define TCG_TARGET_HAS_div_i64
+// #define TCG_TARGET_HAS_rot_i64
 #define TCG_TARGET_HAS_ext8s_i64
 #define TCG_TARGET_HAS_ext16s_i64
 #define TCG_TARGET_HAS_ext32s_i64
+// #define TCG_TARGET_HAS_ext8u_i64
+// #define TCG_TARGET_HAS_ext16u_i64
+// #define TCG_TARGET_HAS_ext32u_i64
+// #define TCG_TARGET_HAS_bswap16_i64
+// #define TCG_TARGET_HAS_bswap32_i64
+// #define TCG_TARGET_HAS_bswap64_i64
+// #define TCG_TARGET_HAS_not_i64
+#define TCG_TARGET_HAS_neg_i64
+// #define TCG_TARGET_HAS_andc_i64
+// #define TCG_TARGET_HAS_orc_i64
 
 #define TCG_AREG0 TCG_REG_R27
 #define TCG_AREG1 TCG_REG_R24
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index 91b931d..e803401 100644
--- a/tcg/s390/tcg-target.h
+++ b/tcg/s390/tcg-target.h
@@ -46,6 +46,36 @@ enum {
 };
 #define TCG_TARGET_NB_REGS 16
 
+/* optional instructions */
+// #define TCG_TARGET_HAS_div_i32
+// #define TCG_TARGET_HAS_rot_i32
+// #define TCG_TARGET_HAS_ext8s_i32
+// #define TCG_TARGET_HAS_ext16s_i32
+// #define TCG_TARGET_HAS_ext8u_i32
+// #define TCG_TARGET_HAS_ext16u_i32
+// #define TCG_TARGET_HAS_bswap16_i32
+// #define TCG_TARGET_HAS_bswap32_i32
+// #define TCG_TARGET_HAS_not_i32
+// #define TCG_TARGET_HAS_neg_i32
+// #define TCG_TARGET_HAS_andc_i32
+// #define TCG_TARGET_HAS_orc_i32
+
+// #define TCG_TARGET_HAS_div_i64
+// #define TCG_TARGET_HAS_rot_i64
+// #define TCG_TARGET_HAS_ext8s_i64
+// #define TCG_TARGET_HAS_ext16s_i64
+// #define TCG_TARGET_HAS_ext32s_i64
+// #define TCG_TARGET_HAS_ext8u_i64
+// #define TCG_TARGET_HAS_ext16u_i64
+// #define TCG_TARGET_HAS_ext32u_i64
+// #define TCG_TARGET_HAS_bswap16_i64
+// #define TCG_TARGET_HAS_bswap32_i64
+// #define TCG_TARGET_HAS_bswap64_i64
+// #define TCG_TARGET_HAS_not_i64
+// #define TCG_TARGET_HAS_neg_i64
+// #define TCG_TARGET_HAS_andc_i64
+// #define TCG_TARGET_HAS_orc_i64
+
 /* used for function call generation */
 #define TCG_REG_CALL_STACK		TCG_REG_R15
 #define TCG_TARGET_STACK_ALIGN		8
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index dc68787..dbc574d 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -89,26 +89,36 @@ enum {
 
 /* optional instructions */
 #define TCG_TARGET_HAS_div_i32
-#define TCG_TARGET_HAS_div_i64
-
+// #define TCG_TARGET_HAS_rot_i32
+// #define TCG_TARGET_HAS_ext8s_i32
+// #define TCG_TARGET_HAS_ext16s_i32
+// #define TCG_TARGET_HAS_ext8u_i32
+// #define TCG_TARGET_HAS_ext16u_i32
+// #define TCG_TARGET_HAS_bswap16_i32
+// #define TCG_TARGET_HAS_bswap32_i32
 #define TCG_TARGET_HAS_neg_i32
 #define TCG_TARGET_HAS_not_i32
 #define TCG_TARGET_HAS_andc_i32
 #define TCG_TARGET_HAS_orc_i32
 
 #if TCG_TARGET_REG_BITS == 64
+#define TCG_TARGET_HAS_div_i64
+// #define TCG_TARGET_HAS_rot_i64
+// #define TCG_TARGET_HAS_ext8s_i64
+// #define TCG_TARGET_HAS_ext16s_i64
 #define TCG_TARGET_HAS_ext32s_i64
+// #define TCG_TARGET_HAS_ext8u_i64
+// #define TCG_TARGET_HAS_ext16u_i64
 #define TCG_TARGET_HAS_ext32u_i64
+// #define TCG_TARGET_HAS_bswap16_i64
+// #define TCG_TARGET_HAS_bswap32_i64
+// #define TCG_TARGET_HAS_bswap64_i64
 #define TCG_TARGET_HAS_neg_i64
 #define TCG_TARGET_HAS_not_i64
 #define TCG_TARGET_HAS_andc_i64
 #define TCG_TARGET_HAS_orc_i64
 #endif
 
-//#define TCG_TARGET_HAS_bswap32_i32
-//#define TCG_TARGET_HAS_bswap64_i64
-
-
 /* Note: must be synced with dyngen-exec.h and Makefile.target */
 #ifdef CONFIG_SOLARIS
 #define TCG_AREG0 TCG_REG_G2
diff --git a/tcg/x86_64/tcg-target.h b/tcg/x86_64/tcg-target.h
index 3ca392f..765f0b4 100644
--- a/tcg/x86_64/tcg-target.h
+++ b/tcg/x86_64/tcg-target.h
@@ -75,10 +75,14 @@ enum {
 #define TCG_TARGET_HAS_ext8u_i64
 #define TCG_TARGET_HAS_ext16u_i64
 #define TCG_TARGET_HAS_ext32u_i64
-
 #define TCG_TARGET_HAS_rot_i32
 #define TCG_TARGET_HAS_rot_i64
 
+// #define TCG_TARGET_HAS_andc_i32
+// #define TCG_TARGET_HAS_andc_i64
+// #define TCG_TARGET_HAS_orc_i32
+// #define TCG_TARGET_HAS_orc_i64
+
 #define TCG_TARGET_HAS_GUEST_BASE
 
 /* Note: must be synced with dyngen-exec.h */
-- 
1.6.6

[Qemu-devel] Re: [PATCH 0/7] tcg-sparc improvements, v2

[Blue Swirl]

Thanks, applied all.

On 2/19/10, Richard Henderson <rth@twiddle.net> wrote:
> Changes since v1:
>   * Add comments for all optional instructions that aren't implemented
>    on each architecture, as requested.
>   * Rebase vs master.
>
>
>  r~
>
>
>  Richard Henderson (7):
>   tcg-sparc: Implement neg.
>   tcg-sparc: Implement not.
>   tcg: Optional target implementation of ANDC.
>   tcg: Optional target implementation of ORC.
>   tcg-sparc: Implement ANDC.
>   tcg-sparc: Implement ORC.
>   tcg: Add comments for all optional instructions not implemented.
>
>   tcg/arm/tcg-target.h    |   14 ++++++++++++++
>   tcg/i386/tcg-target.h   |   12 +++++++-----
>   tcg/mips/tcg-target.h   |    4 +++-
>   tcg/ppc/tcg-target.h    |   10 +++++++++-
>   tcg/ppc64/tcg-target.h  |   25 ++++++++++++++++++++++---
>   tcg/s390/tcg-target.h   |   30 ++++++++++++++++++++++++++++++
>   tcg/sparc/tcg-target.c  |   30 ++++++++++++++++++++++++++++++
>   tcg/sparc/tcg-target.h  |   31 ++++++++++++++++++++++++-------
>   tcg/tcg-op.h            |   22 ++++++++++++++++++++++
>   tcg/tcg-opc.h           |   12 ++++++++++++
>   tcg/x86_64/tcg-target.h |    6 +++++-
>   11 files changed, 178 insertions(+), 18 deletions(-)
>
>