[Qemu-devel] [PATCH 0/2] arm/virt: Add full-sized CPU affinity handling

[Qemu-devel] [PATCH 0/2] arm/virt: Add full-sized CPU affinity handling

[Pavel Fedin]

This small patchset is actually a small extraction from vGICv3 support,
as it was suggested in
https://lists.gnu.org/archive/html/qemu-devel/2015-09/msg00921.html.
Initially i wanted to just make a check, but ended up full implementation
which is not more difficult. Since we don't make any assumptions about
particular affinity layout in non-TCG code, i don't see why this would not
work with KVM.

In order to avoid using magic numbers i refactored out some useful
affinity-related constants.

Pavel Fedin (2):
  target-arm: Refactor CPU affinity handling
  arm/virt: Add full-sized CPU affinity handling

 hw/arm/virt.c        | 32 ++++++++++++++++++++++++++++++--
 target-arm/cpu-qom.h | 12 ++++++++++++
 target-arm/cpu.c     |  2 +-
 target-arm/kvm32.c   |  3 +--
 target-arm/kvm64.c   |  3 +--
 5 files changed, 45 insertions(+), 7 deletions(-)

-- 
2.4.4

[Qemu-devel] [PATCH 1/2] target-arm: Refactor CPU affinity handling

[Pavel Fedin]

Introduces reusable definitions for CPU affinity masks/shifts and gets rid
of hardcoded magic numbers.

Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
---
 target-arm/cpu-qom.h | 12 ++++++++++++
 target-arm/cpu.c     |  2 +-
 target-arm/kvm32.c   |  3 +--
 target-arm/kvm64.c   |  3 +--
 4 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 00c0716..e4ee092 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -227,6 +227,18 @@ void arm_gt_vtimer_cb(void *opaque);
 void arm_gt_htimer_cb(void *opaque);
 void arm_gt_stimer_cb(void *opaque);
 
+#define ARM_AFF0_SHIFT 0
+#define ARM_AFF0_MASK  (0xFFULL << ARM_AFF0_SHIFT)
+#define ARM_AFF1_SHIFT 8
+#define ARM_AFF1_MASK  (0xFFULL << ARM_AFF1_SHIFT)
+#define ARM_AFF2_SHIFT 16
+#define ARM_AFF2_MASK  (0xFFULL << ARM_AFF2_SHIFT)
+#define ARM_AFF3_SHIFT 32
+#define ARM_AFF3_MASK  (0xFFULL << ARM_AFF3_SHIFT)
+
+#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK)
+#define ARM64_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK)
+
 #ifdef TARGET_AARCH64
 int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index cc6c6f3..d54b77d 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -459,7 +459,7 @@ static void arm_cpu_initfn(Object *obj)
      */
     Aff1 = cs->cpu_index / ARM_CPUS_PER_CLUSTER;
     Aff0 = cs->cpu_index % ARM_CPUS_PER_CLUSTER;
-    cpu->mp_affinity = (Aff1 << 8) | Aff0;
+    cpu->mp_affinity = (Aff1 << ARM_AFF1_SHIFT) | Aff0;
 
 #ifndef CONFIG_USER_ONLY
     /* Our inbound IRQ and FIQ lines */
diff --git a/target-arm/kvm32.c b/target-arm/kvm32.c
index 421ce0e..3ae57a6 100644
--- a/target-arm/kvm32.c
+++ b/target-arm/kvm32.c
@@ -181,7 +181,6 @@ int kvm_arm_cpreg_level(uint64_t regidx)
     return KVM_PUT_RUNTIME_STATE;
 }
 
-#define ARM_MPIDR_HWID_BITMASK 0xFFFFFF
 #define ARM_CPU_ID_MPIDR       0, 0, 0, 5
 
 int kvm_arch_init_vcpu(CPUState *cs)
@@ -234,7 +233,7 @@ int kvm_arch_init_vcpu(CPUState *cs)
     if (ret) {
         return ret;
     }
-    cpu->mp_affinity = mpidr & ARM_MPIDR_HWID_BITMASK;
+    cpu->mp_affinity = mpidr & ARM32_AFFINITY_MASK;
 
     return kvm_arm_init_cpreg_list(cpu);
 }
diff --git a/target-arm/kvm64.c b/target-arm/kvm64.c
index bd60889..ceebfeb 100644
--- a/target-arm/kvm64.c
+++ b/target-arm/kvm64.c
@@ -77,7 +77,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc)
     return true;
 }
 
-#define ARM_MPIDR_HWID_BITMASK 0xFF00FFFFFFULL
 #define ARM_CPU_ID_MPIDR       3, 0, 0, 0, 5
 
 int kvm_arch_init_vcpu(CPUState *cs)
@@ -120,7 +119,7 @@ int kvm_arch_init_vcpu(CPUState *cs)
     if (ret) {
         return ret;
     }
-    cpu->mp_affinity = mpidr & ARM_MPIDR_HWID_BITMASK;
+    cpu->mp_affinity = mpidr & ARM64_AFFINITY_MASK;
 
     return kvm_arm_init_cpreg_list(cpu);
 }
-- 
2.4.4

[Qemu-devel] [PATCH 2/2] arm/virt: Add full-sized CPU affinity handling

[Pavel Fedin]

At least with KVM, currently there's no reason why qemu would not be
capable of handling Aff3 != 0. This commit fixes up FDT creation in such
a case.

Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
---
 hw/arm/virt.c | 32 ++++++++++++++++++++++++++++++--
 1 file changed, 30 insertions(+), 2 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index d5a8417..ea3e678 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -284,9 +284,32 @@ static void fdt_add_timer_nodes(const VirtBoardInfo *vbi)
 static void fdt_add_cpu_nodes(const VirtBoardInfo *vbi)
 {
     int cpu;
+    int addr_cells = 1;
+
+    /*
+     * From Documentation/devicetree/bindings/arm/cpus.txt
+     *  On ARM v8 64-bit systems value should be set to 2,
+     *  that corresponds to the MPIDR_EL1 register size.
+     *  If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
+     *  in the system, #address-cells can be set to 1, since
+     *  MPIDR_EL1[63:32] bits are not used for CPUs
+     *  identification.
+     *
+     *  Here we actually don't know whether our system is 32- or 64-bit one.
+     *  The simplest way to go is to examine affinity IDs of all our CPUs. If
+     *  at least one of them has Aff3 populated, we set #address-cells to 2.
+     */
+    for (cpu = 0; cpu < vbi->smp_cpus; cpu++) {
+        ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
+
+        if (armcpu->mp_affinity & ARM_AFF3_MASK) {
+            addr_cells = 2;
+            break;
+        }
+    }
 
     qemu_fdt_add_subnode(vbi->fdt, "/cpus");
-    qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#address-cells", 0x1);
+    qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#address-cells", addr_cells);
     qemu_fdt_setprop_cell(vbi->fdt, "/cpus", "#size-cells", 0x0);
 
     for (cpu = vbi->smp_cpus - 1; cpu >= 0; cpu--) {
@@ -303,7 +326,12 @@ static void fdt_add_cpu_nodes(const VirtBoardInfo *vbi)
                                         "enable-method", "psci");
         }
 
-        qemu_fdt_setprop_cell(vbi->fdt, nodename, "reg", armcpu->mp_affinity);
+        if (addr_cells == 2) {
+            qemu_fdt_setprop_u64(vbi->fdt, nodename, "reg", armcpu->mp_affinity);
+        } else {
+            qemu_fdt_setprop_cell(vbi->fdt, nodename, "reg", armcpu->mp_affinity);
+        }
+
         g_free(nodename);
     }
 }
-- 
2.4.4

Re: [Qemu-devel] [PATCH 0/2] arm/virt: Add full-sized CPU affinity handling

[Peter Maydell]

On 4 September 2015 at 12:39, Pavel Fedin <p.fedin@samsung.com> wrote:
> This small patchset is actually a small extraction from vGICv3 support,
> as it was suggested in
> https://lists.gnu.org/archive/html/qemu-devel/2015-09/msg00921.html.
> Initially i wanted to just make a check, but ended up full implementation
> which is not more difficult. Since we don't make any assumptions about
> particular affinity layout in non-TCG code, i don't see why this would not
> work with KVM.
>
> In order to avoid using magic numbers i refactored out some useful
> affinity-related constants.

Thanks, applied to target-arm.next.

PS: neither patch passed checkpatch.pl and I had to fix them
up by hand; please test and fix style errors before sending
patches out.

thanks
-- PMM

Re: [Qemu-devel] [PATCH 0/2] arm/virt: Add full-sized CPU affinity handling

[Pavel Fedin]

 Hello!

> Thanks, applied to target-arm.next.

 Thanks.

> PS: neither patch passed checkpatch.pl and I had to fix them
> up by hand; please test and fix style errors before sending
> patches out.

 I am horribly sorry, i sometimes simply forget to do this. :( Lots of patchwork today...

Kind regards,
Pavel Fedin
Expert Engineer
Samsung Electronics Research center Russia