* [PATCH v1 0/2] Add support for MediaTek AHCI SATA @ 2017-08-01 7:33 ` Ryder Lee 0 siblings, 0 replies; 6+ messages in thread From: Ryder Lee @ 2017-08-01 7:33 UTC (permalink / raw) To: Hans de Goede, Tejun Heo Cc: Rob Herring, devicetree, linux-mediatek, linux-kernel, linux-ide, Long Cheng, Ryder Lee Hi, This patch series add support for AHCI compatible SATA controller, and it is compliant with the ahci 1.3 and sata 3.0 specification. This driver is slightly different than ahci_platform.c (e.g., reset control, subsystem setting). changes since v1: - update binding text: add missing "specifier pairs" descriptions. - fix kbuild test warning: fix the error handling. Ryder Lee (2): ata: mediatek: add support for MediaTek SATA controller dt-bindings: ata: add DT bindings for MediaTek SATA controller Documentation/devicetree/bindings/ata/ahci-mtk.txt | 50 ++++++ drivers/ata/Kconfig | 10 ++ drivers/ata/Makefile | 1 + drivers/ata/ahci_mtk.c | 196 +++++++++++++++++++++ 4 files changed, 257 insertions(+) create mode 100644 Documentation/devicetree/bindings/ata/ahci-mtk.txt create mode 100644 drivers/ata/ahci_mtk.c -- 1.9.1 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v1 0/2] Add support for MediaTek AHCI SATA @ 2017-08-01 7:33 ` Ryder Lee 0 siblings, 0 replies; 6+ messages in thread From: Ryder Lee @ 2017-08-01 7:33 UTC (permalink / raw) To: Hans de Goede, Tejun Heo Cc: Rob Herring, devicetree, linux-mediatek, linux-kernel, linux-ide, Long Cheng, Ryder Lee Hi, This patch series add support for AHCI compatible SATA controller, and it is compliant with the ahci 1.3 and sata 3.0 specification. This driver is slightly different than ahci_platform.c (e.g., reset control, subsystem setting). changes since v1: - update binding text: add missing "specifier pairs" descriptions. - fix kbuild test warning: fix the error handling. Ryder Lee (2): ata: mediatek: add support for MediaTek SATA controller dt-bindings: ata: add DT bindings for MediaTek SATA controller Documentation/devicetree/bindings/ata/ahci-mtk.txt | 50 ++++++ drivers/ata/Kconfig | 10 ++ drivers/ata/Makefile | 1 + drivers/ata/ahci_mtk.c | 196 +++++++++++++++++++++ 4 files changed, 257 insertions(+) create mode 100644 Documentation/devicetree/bindings/ata/ahci-mtk.txt create mode 100644 drivers/ata/ahci_mtk.c -- 1.9.1 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v1 1/2] ata: mediatek: add support for MediaTek SATA controller 2017-08-01 7:33 ` Ryder Lee @ 2017-08-01 7:33 ` Ryder Lee -1 siblings, 0 replies; 6+ messages in thread From: Ryder Lee @ 2017-08-01 7:33 UTC (permalink / raw) To: Hans de Goede, Tejun Heo Cc: Rob Herring, devicetree, linux-mediatek, linux-kernel, linux-ide, Long Cheng, Ryder Lee This adds support the AHCI-compliant Serial ATA controller present on MediaTek SoCs. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> --- drivers/ata/Kconfig | 10 +++ drivers/ata/Makefile | 1 + drivers/ata/ahci_mtk.c | 196 +++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 207 insertions(+) create mode 100644 drivers/ata/ahci_mtk.c diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 948fc86..7d3eb47 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -153,6 +153,16 @@ config AHCI_CEVA If unsure, say N. +config AHCI_MTK + tristate "MediaTek AHCI SATA support" + depends on ARCH_MEDIATEK + select MFD_SYSCON + help + This option enables support for the MediaTek SoC's + onboard AHCI SATA controller. + + If unsure, say N. + config AHCI_MVEBU tristate "Marvell EBU AHCI SATA support" depends on ARCH_MVEBU diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile index a26ef5a..ff9cd2e 100644 --- a/drivers/ata/Makefile +++ b/drivers/ata/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_AHCI_CEVA) += ahci_ceva.o libahci.o libahci_platform.o obj-$(CONFIG_AHCI_DA850) += ahci_da850.o libahci.o libahci_platform.o obj-$(CONFIG_AHCI_DM816) += ahci_dm816.o libahci.o libahci_platform.o obj-$(CONFIG_AHCI_IMX) += ahci_imx.o libahci.o libahci_platform.o +obj-$(CONFIG_AHCI_MTK) += ahci_mtk.o libahci.o libahci_platform.o obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o libahci.o libahci_platform.o obj-$(CONFIG_AHCI_OCTEON) += ahci_octeon.o obj-$(CONFIG_AHCI_SUNXI) += ahci_sunxi.o libahci.o libahci_platform.o diff --git a/drivers/ata/ahci_mtk.c b/drivers/ata/ahci_mtk.c new file mode 100644 index 0000000..6361316 --- /dev/null +++ b/drivers/ata/ahci_mtk.c @@ -0,0 +1,196 @@ +/* + * MeidaTek AHCI SATA driver + * + * Copyright (c) 2017 MediaTek Inc. + * Author: Ryder Lee <ryder.lee@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/ahci_platform.h> +#include <linux/kernel.h> +#include <linux/libata.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/pm.h> +#include <linux/regmap.h> +#include <linux/reset.h> +#include "ahci.h" + +#define DRV_NAME "ahci" + +#define SYS_CFG 0x14 +#define SYS_CFG_SATA_MSK GENMASK(31, 30) +#define SYS_CFG_SATA_EN BIT(31) + +struct mtk_ahci_drv_data { + struct regmap *mode; + struct reset_control *axi_rst; + struct reset_control *sw_rst; + struct reset_control *reg_rst; +}; + +static const struct ata_port_info ahci_port_info = { + .flags = AHCI_FLAG_COMMON, + .pio_mask = ATA_PIO4, + .udma_mask = ATA_UDMA6, + .port_ops = &ahci_platform_ops, +}; + +static struct scsi_host_template ahci_platform_sht = { + AHCI_SHT(DRV_NAME), +}; + +static int mtk_ahci_platform_resets(struct ahci_host_priv *hpriv, + struct device *dev) +{ + struct mtk_ahci_drv_data *drv_data = hpriv->plat_data; + int err; + + /* reset AXI bus and phy part */ + drv_data->axi_rst = devm_reset_control_get_optional(dev, "axi-rst"); + if (PTR_ERR(drv_data->axi_rst) == -EPROBE_DEFER) + return PTR_ERR(drv_data->axi_rst); + + drv_data->sw_rst = devm_reset_control_get_optional(dev, "sw-rst"); + if (PTR_ERR(drv_data->sw_rst) == -EPROBE_DEFER) + return PTR_ERR(drv_data->sw_rst); + + drv_data->reg_rst = devm_reset_control_get_optional(dev, "reg-rst"); + if (PTR_ERR(drv_data->reg_rst) == -EPROBE_DEFER) + return PTR_ERR(drv_data->reg_rst); + + err = reset_control_assert(drv_data->axi_rst); + if (err) { + dev_err(dev, "assert axi bus failed\n"); + return err; + } + + err = reset_control_assert(drv_data->sw_rst); + if (err) { + dev_err(dev, "assert phy digital part failed\n"); + return err; + } + + err = reset_control_assert(drv_data->reg_rst); + if (err) { + dev_err(dev, "assert phy register part failed\n"); + return err; + } + + err = reset_control_deassert(drv_data->reg_rst); + if (err) { + dev_err(dev, "deassert phy register part failed\n"); + return err; + } + + err = reset_control_deassert(drv_data->sw_rst); + if (err) { + dev_err(dev, "deassert phy digital part failed\n"); + return err; + } + + err = reset_control_deassert(drv_data->axi_rst); + if (err) { + dev_err(dev, "deassert axi bus failed\n"); + return err; + } + + return 0; +} + +static int mtk_ahci_parse_property(struct ahci_host_priv *hpriv, + struct device *dev) +{ + struct mtk_ahci_drv_data *drv_data = hpriv->plat_data; + struct device_node *np = dev->of_node; + + /* enable SATA function if needed */ + if (of_find_property(np, "mediatek,phy-mode", NULL)) { + drv_data->mode = syscon_regmap_lookup_by_phandle( + np, "mediatek,phy-mode"); + if (IS_ERR(drv_data->mode)) { + dev_err(dev, "missing phy-mode phandle\n"); + return PTR_ERR(drv_data->mode); + } + + regmap_update_bits(drv_data->mode, SYS_CFG, SYS_CFG_SATA_MSK, + SYS_CFG_SATA_EN); + } + + of_property_read_u32(np, "ports-implemented", &hpriv->force_port_map); + + return 0; +} + +static int mtk_ahci_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mtk_ahci_drv_data *drv_data; + struct ahci_host_priv *hpriv; + int err; + + drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); + if (!drv_data) + return -ENOMEM; + + hpriv = ahci_platform_get_resources(pdev); + if (IS_ERR(hpriv)) + return PTR_ERR(hpriv); + + hpriv->plat_data = drv_data; + + err = mtk_ahci_parse_property(hpriv, dev); + if (err) + return err; + + err = mtk_ahci_platform_resets(hpriv, dev); + if (err) + return err; + + err = ahci_platform_enable_resources(hpriv); + if (err) + return err; + + err = ahci_platform_init_host(pdev, hpriv, &ahci_port_info, + &ahci_platform_sht); + if (err) + goto disable_resources; + + return 0; + +disable_resources: + ahci_platform_disable_resources(hpriv); + return err; +} + +static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_platform_suspend, + ahci_platform_resume); + +static const struct of_device_id ahci_of_match[] = { + { .compatible = "mediatek,ahci", }, + {}, +}; +MODULE_DEVICE_TABLE(of, ahci_of_match); + +static struct platform_driver mtk_ahci_driver = { + .probe = mtk_ahci_probe, + .remove = ata_platform_remove_one, + .driver = { + .name = DRV_NAME, + .of_match_table = ahci_of_match, + .pm = &ahci_pm_ops, + }, +}; +module_platform_driver(mtk_ahci_driver); + +MODULE_DESCRIPTION("MeidaTek SATA AHCI Driver"); +MODULE_LICENSE("GPL v2"); -- 1.9.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v1 1/2] ata: mediatek: add support for MediaTek SATA controller @ 2017-08-01 7:33 ` Ryder Lee 0 siblings, 0 replies; 6+ messages in thread From: Ryder Lee @ 2017-08-01 7:33 UTC (permalink / raw) To: Hans de Goede, Tejun Heo Cc: Rob Herring, devicetree, linux-mediatek, linux-kernel, linux-ide, Long Cheng, Ryder Lee This adds support the AHCI-compliant Serial ATA controller present on MediaTek SoCs. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> --- drivers/ata/Kconfig | 10 +++ drivers/ata/Makefile | 1 + drivers/ata/ahci_mtk.c | 196 +++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 207 insertions(+) create mode 100644 drivers/ata/ahci_mtk.c diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 948fc86..7d3eb47 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -153,6 +153,16 @@ config AHCI_CEVA If unsure, say N. +config AHCI_MTK + tristate "MediaTek AHCI SATA support" + depends on ARCH_MEDIATEK + select MFD_SYSCON + help + This option enables support for the MediaTek SoC's + onboard AHCI SATA controller. + + If unsure, say N. + config AHCI_MVEBU tristate "Marvell EBU AHCI SATA support" depends on ARCH_MVEBU diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile index a26ef5a..ff9cd2e 100644 --- a/drivers/ata/Makefile +++ b/drivers/ata/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_AHCI_CEVA) += ahci_ceva.o libahci.o libahci_platform.o obj-$(CONFIG_AHCI_DA850) += ahci_da850.o libahci.o libahci_platform.o obj-$(CONFIG_AHCI_DM816) += ahci_dm816.o libahci.o libahci_platform.o obj-$(CONFIG_AHCI_IMX) += ahci_imx.o libahci.o libahci_platform.o +obj-$(CONFIG_AHCI_MTK) += ahci_mtk.o libahci.o libahci_platform.o obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o libahci.o libahci_platform.o obj-$(CONFIG_AHCI_OCTEON) += ahci_octeon.o obj-$(CONFIG_AHCI_SUNXI) += ahci_sunxi.o libahci.o libahci_platform.o diff --git a/drivers/ata/ahci_mtk.c b/drivers/ata/ahci_mtk.c new file mode 100644 index 0000000..6361316 --- /dev/null +++ b/drivers/ata/ahci_mtk.c @@ -0,0 +1,196 @@ +/* + * MeidaTek AHCI SATA driver + * + * Copyright (c) 2017 MediaTek Inc. + * Author: Ryder Lee <ryder.lee@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/ahci_platform.h> +#include <linux/kernel.h> +#include <linux/libata.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/pm.h> +#include <linux/regmap.h> +#include <linux/reset.h> +#include "ahci.h" + +#define DRV_NAME "ahci" + +#define SYS_CFG 0x14 +#define SYS_CFG_SATA_MSK GENMASK(31, 30) +#define SYS_CFG_SATA_EN BIT(31) + +struct mtk_ahci_drv_data { + struct regmap *mode; + struct reset_control *axi_rst; + struct reset_control *sw_rst; + struct reset_control *reg_rst; +}; + +static const struct ata_port_info ahci_port_info = { + .flags = AHCI_FLAG_COMMON, + .pio_mask = ATA_PIO4, + .udma_mask = ATA_UDMA6, + .port_ops = &ahci_platform_ops, +}; + +static struct scsi_host_template ahci_platform_sht = { + AHCI_SHT(DRV_NAME), +}; + +static int mtk_ahci_platform_resets(struct ahci_host_priv *hpriv, + struct device *dev) +{ + struct mtk_ahci_drv_data *drv_data = hpriv->plat_data; + int err; + + /* reset AXI bus and phy part */ + drv_data->axi_rst = devm_reset_control_get_optional(dev, "axi-rst"); + if (PTR_ERR(drv_data->axi_rst) == -EPROBE_DEFER) + return PTR_ERR(drv_data->axi_rst); + + drv_data->sw_rst = devm_reset_control_get_optional(dev, "sw-rst"); + if (PTR_ERR(drv_data->sw_rst) == -EPROBE_DEFER) + return PTR_ERR(drv_data->sw_rst); + + drv_data->reg_rst = devm_reset_control_get_optional(dev, "reg-rst"); + if (PTR_ERR(drv_data->reg_rst) == -EPROBE_DEFER) + return PTR_ERR(drv_data->reg_rst); + + err = reset_control_assert(drv_data->axi_rst); + if (err) { + dev_err(dev, "assert axi bus failed\n"); + return err; + } + + err = reset_control_assert(drv_data->sw_rst); + if (err) { + dev_err(dev, "assert phy digital part failed\n"); + return err; + } + + err = reset_control_assert(drv_data->reg_rst); + if (err) { + dev_err(dev, "assert phy register part failed\n"); + return err; + } + + err = reset_control_deassert(drv_data->reg_rst); + if (err) { + dev_err(dev, "deassert phy register part failed\n"); + return err; + } + + err = reset_control_deassert(drv_data->sw_rst); + if (err) { + dev_err(dev, "deassert phy digital part failed\n"); + return err; + } + + err = reset_control_deassert(drv_data->axi_rst); + if (err) { + dev_err(dev, "deassert axi bus failed\n"); + return err; + } + + return 0; +} + +static int mtk_ahci_parse_property(struct ahci_host_priv *hpriv, + struct device *dev) +{ + struct mtk_ahci_drv_data *drv_data = hpriv->plat_data; + struct device_node *np = dev->of_node; + + /* enable SATA function if needed */ + if (of_find_property(np, "mediatek,phy-mode", NULL)) { + drv_data->mode = syscon_regmap_lookup_by_phandle( + np, "mediatek,phy-mode"); + if (IS_ERR(drv_data->mode)) { + dev_err(dev, "missing phy-mode phandle\n"); + return PTR_ERR(drv_data->mode); + } + + regmap_update_bits(drv_data->mode, SYS_CFG, SYS_CFG_SATA_MSK, + SYS_CFG_SATA_EN); + } + + of_property_read_u32(np, "ports-implemented", &hpriv->force_port_map); + + return 0; +} + +static int mtk_ahci_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mtk_ahci_drv_data *drv_data; + struct ahci_host_priv *hpriv; + int err; + + drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); + if (!drv_data) + return -ENOMEM; + + hpriv = ahci_platform_get_resources(pdev); + if (IS_ERR(hpriv)) + return PTR_ERR(hpriv); + + hpriv->plat_data = drv_data; + + err = mtk_ahci_parse_property(hpriv, dev); + if (err) + return err; + + err = mtk_ahci_platform_resets(hpriv, dev); + if (err) + return err; + + err = ahci_platform_enable_resources(hpriv); + if (err) + return err; + + err = ahci_platform_init_host(pdev, hpriv, &ahci_port_info, + &ahci_platform_sht); + if (err) + goto disable_resources; + + return 0; + +disable_resources: + ahci_platform_disable_resources(hpriv); + return err; +} + +static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_platform_suspend, + ahci_platform_resume); + +static const struct of_device_id ahci_of_match[] = { + { .compatible = "mediatek,ahci", }, + {}, +}; +MODULE_DEVICE_TABLE(of, ahci_of_match); + +static struct platform_driver mtk_ahci_driver = { + .probe = mtk_ahci_probe, + .remove = ata_platform_remove_one, + .driver = { + .name = DRV_NAME, + .of_match_table = ahci_of_match, + .pm = &ahci_pm_ops, + }, +}; +module_platform_driver(mtk_ahci_driver); + +MODULE_DESCRIPTION("MeidaTek SATA AHCI Driver"); +MODULE_LICENSE("GPL v2"); -- 1.9.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v1 2/2] dt-bindings: ata: add DT bindings for MediaTek SATA controller 2017-08-01 7:33 ` Ryder Lee @ 2017-08-01 7:33 ` Ryder Lee -1 siblings, 0 replies; 6+ messages in thread From: Ryder Lee @ 2017-08-01 7:33 UTC (permalink / raw) To: Hans de Goede, Tejun Heo Cc: Rob Herring, devicetree, linux-mediatek, linux-kernel, linux-ide, Long Cheng, Ryder Lee Add DT bindings for the onboard SATA controller present on the MediaTek SoCs. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> --- Documentation/devicetree/bindings/ata/ahci-mtk.txt | 50 ++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/ata/ahci-mtk.txt diff --git a/Documentation/devicetree/bindings/ata/ahci-mtk.txt b/Documentation/devicetree/bindings/ata/ahci-mtk.txt new file mode 100644 index 0000000..8f64f15 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/ahci-mtk.txt @@ -0,0 +1,50 @@ +MediaTek Seria ATA controller + +Required properties: + - compatible : Must be "mediatek,ahci". + - reg : Physical base addresses and length of register sets. + - interrupts : Interrupt associated with the SATA device. + - interrupt-names : Associated name must be: "hostc". + - clocks : A list of phandle and clock specifier pairs, one for each + entry in clock-names. + - clock-names : Associated names must be: "ahb", "axi", "asic", "rbc", "pm". + - phys : A phandle and PHY specifier pair for the PHY port. + - phy-names : Associated name must be: "sata-phy". + - ports-implemented : Mask that indicates which ports that the HBA supports + are available for software to use. Useful if PORTS_IMPL + is not programmed by the BIOS, which is true with some + embedded SOC's. + +Optional properties: + - power-domains : A phandle and power domain specifier pair to the power + domain which is responsible for collapsing and restoring + power to the peripheral. + - resets : Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. + - reset-names : Associated names must be: "axi-rst", "sw-rst", "reg-rst". + - mediatek,phy-mode : A phandle to the system controller, used to enable + SATA function. + +Example: + + sata: sata@1a200000 { + compatible = "mediatek,ahci"; + reg = <0 0x1a200000 0 0x1100>; + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hostc"; + clocks = <&pciesys CLK_SATA_AHB_EN>, + <&pciesys CLK_SATA_AXI_EN>, + <&pciesys CLK_SATA_ASIC_EN>, + <&pciesys CLK_SATA_RBC_EN>, + <&pciesys CLK_SATA_PM_EN>; + clock-names = "ahb", "axi", "asic", "rbc", "pm"; + phys = <&u3port1 PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; + resets = <&pciesys MT7622_SATA_AXI_BUS_RST>, + <&pciesys MT7622_SATA_PHY_SW_RST>, + <&pciesys MT7622_SATA_PHY_REG_RST>; + reset-names = "axi-rst", "sw-rst", "reg-rst"; + mediatek,phy-mode = <&pciesys>; + }; -- 1.9.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v1 2/2] dt-bindings: ata: add DT bindings for MediaTek SATA controller @ 2017-08-01 7:33 ` Ryder Lee 0 siblings, 0 replies; 6+ messages in thread From: Ryder Lee @ 2017-08-01 7:33 UTC (permalink / raw) To: Hans de Goede, Tejun Heo Cc: Rob Herring, devicetree, linux-mediatek, linux-kernel, linux-ide, Long Cheng, Ryder Lee Add DT bindings for the onboard SATA controller present on the MediaTek SoCs. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> --- Documentation/devicetree/bindings/ata/ahci-mtk.txt | 50 ++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/ata/ahci-mtk.txt diff --git a/Documentation/devicetree/bindings/ata/ahci-mtk.txt b/Documentation/devicetree/bindings/ata/ahci-mtk.txt new file mode 100644 index 0000000..8f64f15 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/ahci-mtk.txt @@ -0,0 +1,50 @@ +MediaTek Seria ATA controller + +Required properties: + - compatible : Must be "mediatek,ahci". + - reg : Physical base addresses and length of register sets. + - interrupts : Interrupt associated with the SATA device. + - interrupt-names : Associated name must be: "hostc". + - clocks : A list of phandle and clock specifier pairs, one for each + entry in clock-names. + - clock-names : Associated names must be: "ahb", "axi", "asic", "rbc", "pm". + - phys : A phandle and PHY specifier pair for the PHY port. + - phy-names : Associated name must be: "sata-phy". + - ports-implemented : Mask that indicates which ports that the HBA supports + are available for software to use. Useful if PORTS_IMPL + is not programmed by the BIOS, which is true with some + embedded SOC's. + +Optional properties: + - power-domains : A phandle and power domain specifier pair to the power + domain which is responsible for collapsing and restoring + power to the peripheral. + - resets : Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. + - reset-names : Associated names must be: "axi-rst", "sw-rst", "reg-rst". + - mediatek,phy-mode : A phandle to the system controller, used to enable + SATA function. + +Example: + + sata: sata@1a200000 { + compatible = "mediatek,ahci"; + reg = <0 0x1a200000 0 0x1100>; + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hostc"; + clocks = <&pciesys CLK_SATA_AHB_EN>, + <&pciesys CLK_SATA_AXI_EN>, + <&pciesys CLK_SATA_ASIC_EN>, + <&pciesys CLK_SATA_RBC_EN>, + <&pciesys CLK_SATA_PM_EN>; + clock-names = "ahb", "axi", "asic", "rbc", "pm"; + phys = <&u3port1 PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; + resets = <&pciesys MT7622_SATA_AXI_BUS_RST>, + <&pciesys MT7622_SATA_PHY_SW_RST>, + <&pciesys MT7622_SATA_PHY_REG_RST>; + reset-names = "axi-rst", "sw-rst", "reg-rst"; + mediatek,phy-mode = <&pciesys>; + }; -- 1.9.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2017-08-01 7:34 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2017-08-01 7:33 [PATCH v1 0/2] Add support for MediaTek AHCI SATA Ryder Lee 2017-08-01 7:33 ` Ryder Lee 2017-08-01 7:33 ` [PATCH v1 1/2] ata: mediatek: add support for MediaTek SATA controller Ryder Lee 2017-08-01 7:33 ` Ryder Lee 2017-08-01 7:33 ` [PATCH v1 2/2] dt-bindings: ata: add DT bindings " Ryder Lee 2017-08-01 7:33 ` Ryder Lee
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