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From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
To: Mathieu Poirier <mathieu.poirier@linaro.org>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Leo Yan <leo.yan@linaro.org>, Rob Herring <robh+dt@kernel.org>,
	devicetree@vger.kernel.org,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Andy Gross <andy.gross@linaro.org>,
	David Brown <david.brown@linaro.org>,
	Mark Rutland <mark.rutland@arm.com>
Cc: Rajendra Nayak <rnayak@codeaurora.org>,
	Vivek Gautam <vivek.gautam@codeaurora.org>,
	Sibi Sankar <sibis@codeaurora.org>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Subject: [PATCHv3 0/1] coresight: Do not default to CPU0 for missing CPU phandle
Date: Mon, 24 Jun 2019 09:06:08 +0530	[thread overview]
Message-ID: <cover.1561346998.git.saiprakash.ranjan@codeaurora.org> (raw)

In case of missing CPU phandle, the affinity is set default to
CPU0 which is not a correct assumption. Fix this in coresight
platform to set affinity to invalid and abort the probe in drivers.
Also update the dt-bindings accordingly.

v3:
 * Addressed review comments from Suzuki and updated
   acpi_coresight_get_cpu.
 * Removed patch 2 which had invalid check for online
   cpus.

v2:
 * Addressed review comments from Suzuki and Mathieu.
 * Allows the probe of etm and cpu-debug to abort earlier
   in case of unavailability of respective cpus.

Sai Prakash Ranjan (1):
  coresight: Do not default to CPU0 for missing CPU phandle

 .../bindings/arm/coresight-cpu-debug.txt         |  4 ++--
 .../devicetree/bindings/arm/coresight.txt        |  8 +++++---
 .../hwtracing/coresight/coresight-cpu-debug.c    |  3 +++
 drivers/hwtracing/coresight/coresight-etm3x.c    |  3 +++
 drivers/hwtracing/coresight/coresight-etm4x.c    |  3 +++
 drivers/hwtracing/coresight/coresight-platform.c | 16 ++++++++--------
 6 files changed, 24 insertions(+), 13 deletions(-)

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation


WARNING: multiple messages have this Message-ID (diff)
From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
To: Mathieu Poirier <mathieu.poirier@linaro.org>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Leo Yan <leo.yan@linaro.org>, Rob Herring <robh+dt@kernel.org>,
	devicetree@vger.kernel.org,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Andy Gross <andy.gross@linaro.org>,
	David Brown <david.brown@linaro.org>,
	Mark Rutland <mark.rutland@arm.com>
Cc: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>,
	Rajendra Nayak <rnayak@codeaurora.org>,
	linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
	Sibi Sankar <sibis@codeaurora.org>,
	Vivek Gautam <vivek.gautam@codeaurora.org>,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCHv3 0/1] coresight: Do not default to CPU0 for missing CPU phandle
Date: Mon, 24 Jun 2019 09:06:08 +0530	[thread overview]
Message-ID: <cover.1561346998.git.saiprakash.ranjan@codeaurora.org> (raw)

In case of missing CPU phandle, the affinity is set default to
CPU0 which is not a correct assumption. Fix this in coresight
platform to set affinity to invalid and abort the probe in drivers.
Also update the dt-bindings accordingly.

v3:
 * Addressed review comments from Suzuki and updated
   acpi_coresight_get_cpu.
 * Removed patch 2 which had invalid check for online
   cpus.

v2:
 * Addressed review comments from Suzuki and Mathieu.
 * Allows the probe of etm and cpu-debug to abort earlier
   in case of unavailability of respective cpus.

Sai Prakash Ranjan (1):
  coresight: Do not default to CPU0 for missing CPU phandle

 .../bindings/arm/coresight-cpu-debug.txt         |  4 ++--
 .../devicetree/bindings/arm/coresight.txt        |  8 +++++---
 .../hwtracing/coresight/coresight-cpu-debug.c    |  3 +++
 drivers/hwtracing/coresight/coresight-etm3x.c    |  3 +++
 drivers/hwtracing/coresight/coresight-etm4x.c    |  3 +++
 drivers/hwtracing/coresight/coresight-platform.c | 16 ++++++++--------
 6 files changed, 24 insertions(+), 13 deletions(-)

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation


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             reply	other threads:[~2019-06-24  3:36 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-24  3:36 Sai Prakash Ranjan [this message]
2019-06-24  3:36 ` [PATCHv3 0/1] coresight: Do not default to CPU0 for missing CPU phandle Sai Prakash Ranjan
2019-06-24  3:36 ` [PATCHv3 1/1] " Sai Prakash Ranjan
2019-06-24  3:36   ` Sai Prakash Ranjan
2019-06-24  8:26   ` Suzuki K Poulose
2019-06-24  8:26     ` Suzuki K Poulose
2019-06-24  9:27     ` Sai Prakash Ranjan
2019-06-24  9:27       ` Sai Prakash Ranjan
2019-06-26 17:41   ` Mathieu Poirier
2019-06-26 17:41     ` Mathieu Poirier
2019-06-26 17:41     ` Mathieu Poirier
2019-06-26 19:02     ` Sai Prakash Ranjan
2019-06-26 19:02       ` Sai Prakash Ranjan

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