* [PATCH 1/2] dt-bindings: serial: lantiq: Convert to YAML schema
2019-08-14 8:22 [PATCH 0/2] dt-bindings: serial: lantiq: Convert to YAML & add support for new SoC Rahul Tanwar
@ 2019-08-14 8:22 ` Rahul Tanwar
2019-08-14 8:22 ` [PATCH 2/2] dt-bindings: lantiq: Update for new SoC Rahul Tanwar
1 sibling, 0 replies; 3+ messages in thread
From: Rahul Tanwar @ 2019-08-14 8:22 UTC (permalink / raw)
To: gregkh, robh+dt, robh, mark.rutland, linux-serial
Cc: linux-kernel, andriy.shevchenko, qi-ming.wu, cheol.yong.kim,
rahul.tanwar, Rahul Tanwar
Convert the existing DT binding document for Lantiq SoC ASC serial controller
from txt format to YAML format.
Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com>
---
.../devicetree/bindings/serial/lantiq_asc.txt | 31 ----------
.../devicetree/bindings/serial/lantiq_asc.yaml | 70 ++++++++++++++++++++++
2 files changed, 70 insertions(+), 31 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/serial/lantiq_asc.txt
create mode 100644 Documentation/devicetree/bindings/serial/lantiq_asc.yaml
diff --git a/Documentation/devicetree/bindings/serial/lantiq_asc.txt b/Documentation/devicetree/bindings/serial/lantiq_asc.txt
deleted file mode 100644
index 40e81a5818f6..000000000000
--- a/Documentation/devicetree/bindings/serial/lantiq_asc.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-Lantiq SoC ASC serial controller
-
-Required properties:
-- compatible : Should be "lantiq,asc"
-- reg : Address and length of the register set for the device
-- interrupts: the 3 (tx rx err) interrupt numbers. The interrupt specifier
- depends on the interrupt-parent interrupt controller.
-
-Optional properties:
-- clocks: Should contain frequency clock and gate clock
-- clock-names: Should be "freq" and "asc"
-
-Example:
-
-asc0: serial@16600000 {
- compatible = "lantiq,asc";
- reg = <0x16600000 0x100000>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SHARED 103 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SHARED 105 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SHARED 106 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cgu CLK_SSX4>, <&cgu GCLK_UART>;
- clock-names = "freq", "asc";
-};
-
-asc1: serial@e100c00 {
- compatible = "lantiq,asc";
- reg = <0xE100C00 0x400>;
- interrupt-parent = <&icu0>;
- interrupts = <112 113 114>;
-};
diff --git a/Documentation/devicetree/bindings/serial/lantiq_asc.yaml b/Documentation/devicetree/bindings/serial/lantiq_asc.yaml
new file mode 100644
index 000000000000..9757f0a24232
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/lantiq_asc.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/serial/lantiq_asc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Lantiq SoC ASC serial controller
+
+maintainers:
+ - Rahul Tanwar <rahul.tanwar@intel.com>
+
+allOf:
+ - $ref: /schemas/serial.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ items:
+ - const: lantiq,asc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 1
+ maxItems: 3
+ items:
+ - description: tx or combined interrupt
+ - description: rx interrupt
+ - description: err interrupt
+
+ clocks:
+ description:
+ When present, first entry listed should contain phandle
+ to the frequency clock and second entry should contain
+ phandle to the gate clock.
+
+ clock-names:
+ items:
+ - const: freq
+ - const: asc
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+
+examples:
+ - |
+ asc0: serial@16600000 {
+ compatible = "lantiq,asc";
+ reg = <0x16600000 0x100000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SHARED 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SHARED 106 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cgu CLK_SSX4>, <&cgu GCLK_UART>;
+ clock-names = "freq", "asc";
+ };
+
+ - |
+ asc1: serial@e100c00 {
+ compatible = "lantiq,asc";
+ reg = <0xE100C00 0x400>;
+ interrupt-parent = <&icu0>;
+ interrupts = <112 113 114>;
+ };
+
+...
--
2.11.0
^ permalink raw reply related [flat|nested] 3+ messages in thread* [PATCH 2/2] dt-bindings: lantiq: Update for new SoC
2019-08-14 8:22 [PATCH 0/2] dt-bindings: serial: lantiq: Convert to YAML & add support for new SoC Rahul Tanwar
2019-08-14 8:22 ` [PATCH 1/2] dt-bindings: serial: lantiq: Convert to YAML schema Rahul Tanwar
@ 2019-08-14 8:22 ` Rahul Tanwar
1 sibling, 0 replies; 3+ messages in thread
From: Rahul Tanwar @ 2019-08-14 8:22 UTC (permalink / raw)
To: gregkh, robh+dt, robh, mark.rutland, linux-serial
Cc: linux-kernel, andriy.shevchenko, qi-ming.wu, cheol.yong.kim,
rahul.tanwar, Rahul Tanwar
Intel Lightning Mountain(LGM) SoC reuses Lantiq ASC serial controller IP.
This patch updates the dt bindings to support LGM as well.
Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com>
---
.../devicetree/bindings/serial/lantiq_asc.yaml | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/Documentation/devicetree/bindings/serial/lantiq_asc.yaml b/Documentation/devicetree/bindings/serial/lantiq_asc.yaml
index 9757f0a24232..d552fd31c16c 100644
--- a/Documentation/devicetree/bindings/serial/lantiq_asc.yaml
+++ b/Documentation/devicetree/bindings/serial/lantiq_asc.yaml
@@ -17,6 +17,7 @@ properties:
oneOf:
items:
- const: lantiq,asc
+ - const: intel,lgm-asc
reg:
maxItems: 1
@@ -28,6 +29,12 @@ properties:
- description: tx or combined interrupt
- description: rx interrupt
- description: err interrupt
+ description:
+ For lantiq,asc compatible, it supports 3 separate
+ interrupts for tx rx & err. Whereas, for intel,lgm-asc
+ compatible, it supports combined single interrupt for
+ all of tx, rx & err interrupts.
+
clocks:
description:
@@ -67,4 +74,14 @@ examples:
interrupts = <112 113 114>;
};
+ - |
+ asc0: serial@e0a00000 {
+ compatible = "intel,lgm-asc";
+ reg = <0xe0a00000 0x1000>;
+ interrupt-parent = <&ioapic1>;
+ interrupts = <128 1>;
+ clocks = <&cgu0 LGM_CLK_NOC4>, <&cgu0 LGM_GCLK_ASC0>;
+ clock-names = "freq", "asc";
+ };
+
...
--
2.11.0
^ permalink raw reply related [flat|nested] 3+ messages in thread