* [PATCH 0/2] TM field check failed
@ 2019-10-08 2:34 ` qi1.zhang
0 siblings, 0 replies; 7+ messages in thread
From: qi1.zhang @ 2019-10-08 1:39 UTC (permalink / raw)
To: qemu-devel; +Cc: qi1.zhang, ehabkost, mst, pbonzini, rth
From: "Zhang, Qi" <qi1.zhang@intel.com>
*** BLURB HERE ***
Zhang, Qi (2):
intel_iommu: split the resevred fields arrays into two ones
intel_iommu: TM field should not be in reserved bits
hw/i386/intel_iommu.c | 35 ++++++++++++++++++++--------------
hw/i386/intel_iommu_internal.h | 17 +++++++++++++----
2 files changed, 34 insertions(+), 18 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/2] intel_iommu: split the resevred fields arrays into two ones
@ 2019-10-08 2:34 ` qi1.zhang
0 siblings, 0 replies; 7+ messages in thread
From: qi1.zhang @ 2019-10-08 1:39 UTC (permalink / raw)
To: qemu-devel; +Cc: qi1.zhang, ehabkost, mst, pbonzini, rth
From: "Zhang, Qi" <qi1.zhang@intel.com>
Signed-off-by: Zhang, Qi <qi1.zhang@intel.com>
---
hw/i386/intel_iommu.c | 31 +++++++++++++++++--------------
1 file changed, 17 insertions(+), 14 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index f1de8fdb75..a118efaeaf 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -910,18 +910,19 @@ static dma_addr_t vtd_get_iova_pgtbl_base(IntelIOMMUState *s,
/*
* Rsvd field masks for spte:
- * Index [1] to [4] 4k pages
- * Index [5] to [8] large pages
+ * vtd_spte_rsvd 4k pages
+ * vtd_spte_rsvd_large large pages
*/
-static uint64_t vtd_paging_entry_rsvd_field[9];
+static uint64_t vtd_spte_rsvd[5];
+static uint64_t vtd_spte_rsvd_large[5];
static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, uint32_t level)
{
if (slpte & VTD_SL_PT_PAGE_SIZE_MASK) {
/* Maybe large page */
- return slpte & vtd_paging_entry_rsvd_field[level + 4];
+ return slpte & vtd_spte_rsvd_large[level];
} else {
- return slpte & vtd_paging_entry_rsvd_field[level];
+ return slpte & vtd_spte_rsvd[level];
}
}
@@ -3547,15 +3548,17 @@ static void vtd_init(IntelIOMMUState *s)
/*
* Rsvd field masks for spte
*/
- vtd_paging_entry_rsvd_field[0] = ~0ULL;
- vtd_paging_entry_rsvd_field[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[5] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[6] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[7] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[8] = VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd[0] = ~0ULL;
+ vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
+
+ vtd_spte_rsvd_large[0] = ~0ULL;
+ vtd_spte_rsvd_large[1] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd_large[4] = VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_bits);
if (x86_iommu_ir_supported(x86_iommu)) {
s->ecap |= VTD_ECAP_IR | VTD_ECAP_MHMV;
--
2.20.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/2] intel_iommu: TM field should not be in reserved bits
@ 2019-10-08 2:34 ` qi1.zhang
0 siblings, 0 replies; 7+ messages in thread
From: qi1.zhang @ 2019-10-08 1:39 UTC (permalink / raw)
To: qemu-devel; +Cc: qi1.zhang, ehabkost, mst, pbonzini, rth
From: "Zhang, Qi" <qi1.zhang@intel.com>
When dt is supported, TM field should not be Reserved(0).
Refer to VT-d Spec 9.8
Signed-off-by: Zhang, Qi <qi1.zhang@intel.com>
Signed-off-by: Qi, Yadong <yadong.qi@intel.com>
---
hw/i386/intel_iommu.c | 12 ++++++++----
hw/i386/intel_iommu_internal.h | 17 +++++++++++++----
2 files changed, 21 insertions(+), 8 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index a118efaeaf..d62604ece3 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -3549,15 +3549,19 @@ static void vtd_init(IntelIOMMUState *s)
* Rsvd field masks for spte
*/
vtd_spte_rsvd[0] = ~0ULL;
- vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits,
+ x86_iommu->dt_supported);
vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
vtd_spte_rsvd_large[0] = ~0ULL;
- vtd_spte_rsvd_large[1] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits);
- vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits);
- vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd_large[1] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits,
+ x86_iommu->dt_supported);
+ vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits,
+ x86_iommu->dt_supported);
+ vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits,
+ x86_iommu->dt_supported);
vtd_spte_rsvd_large[4] = VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_bits);
if (x86_iommu_ir_supported(x86_iommu)) {
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index c1235a7063..3a839a8925 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -387,7 +387,9 @@ typedef union VTDInvDesc VTDInvDesc;
#define VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO 0xffff0000ffe0fff8
/* Rsvd field masks for spte */
-#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw) \
+#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw, dt_supported) \
+ dt_supported ? \
+ (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
(0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
#define VTD_SPTE_PAGE_L2_RSVD_MASK(aw) \
(0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
@@ -395,11 +397,17 @@ typedef union VTDInvDesc VTDInvDesc;
(0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
#define VTD_SPTE_PAGE_L4_RSVD_MASK(aw) \
(0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
-#define VTD_SPTE_LPAGE_L1_RSVD_MASK(aw) \
+#define VTD_SPTE_LPAGE_L1_RSVD_MASK(aw, dt_supported) \
+ dt_supported ? \
+ (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
(0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
-#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw) \
+#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw, dt_supported) \
+ dt_supported ? \
+ (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
(0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
-#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw) \
+#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw, dt_supported) \
+ dt_supported ? \
+ (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
(0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
#define VTD_SPTE_LPAGE_L4_RSVD_MASK(aw) \
(0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
@@ -506,5 +514,6 @@ typedef struct VTDRootEntry VTDRootEntry;
#define VTD_SL_W (1ULL << 1)
#define VTD_SL_PT_BASE_ADDR_MASK(aw) (~(VTD_PAGE_SIZE - 1) & VTD_HAW_MASK(aw))
#define VTD_SL_IGN_COM 0xbff0000000000000ULL
+#define VTD_SL_TM (1ULL << 62)
#endif
--
2.20.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v1 0/2] TM field check failed
@ 2019-10-08 2:34 ` qi1.zhang
0 siblings, 0 replies; 7+ messages in thread
From: qi1.zhang @ 2019-10-08 2:34 UTC (permalink / raw)
To: qemu-devel; +Cc: qi1.zhang, ehabkost, mst, pbonzini, yadong.qi, rth
From: "Zhang, Qi" <qi1.zhang@intel.com>
spilt the reserved fields arrays and remove TM field
from reserved bits
Changelog V1:
add descriptons
Zhang, Qi (2):
intel_iommu: split the resevred fields arrays into two ones
intel_iommu: TM field should not be in reserved bits
hw/i386/intel_iommu.c | 35 ++++++++++++++++++++--------------
hw/i386/intel_iommu_internal.h | 17 +++++++++++++----
2 files changed, 34 insertions(+), 18 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v1 1/2] intel_iommu: split the resevred fields arrays into two ones
@ 2019-10-08 2:34 ` qi1.zhang
0 siblings, 0 replies; 7+ messages in thread
From: qi1.zhang @ 2019-10-08 2:34 UTC (permalink / raw)
To: qemu-devel; +Cc: qi1.zhang, ehabkost, mst, pbonzini, yadong.qi, rth
From: "Zhang, Qi" <qi1.zhang@intel.com>
Signed-off-by: Zhang, Qi <qi1.zhang@intel.com>
---
hw/i386/intel_iommu.c | 31 +++++++++++++++++--------------
1 file changed, 17 insertions(+), 14 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index f1de8fdb75..a118efaeaf 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -910,18 +910,19 @@ static dma_addr_t vtd_get_iova_pgtbl_base(IntelIOMMUState *s,
/*
* Rsvd field masks for spte:
- * Index [1] to [4] 4k pages
- * Index [5] to [8] large pages
+ * vtd_spte_rsvd 4k pages
+ * vtd_spte_rsvd_large large pages
*/
-static uint64_t vtd_paging_entry_rsvd_field[9];
+static uint64_t vtd_spte_rsvd[5];
+static uint64_t vtd_spte_rsvd_large[5];
static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, uint32_t level)
{
if (slpte & VTD_SL_PT_PAGE_SIZE_MASK) {
/* Maybe large page */
- return slpte & vtd_paging_entry_rsvd_field[level + 4];
+ return slpte & vtd_spte_rsvd_large[level];
} else {
- return slpte & vtd_paging_entry_rsvd_field[level];
+ return slpte & vtd_spte_rsvd[level];
}
}
@@ -3547,15 +3548,17 @@ static void vtd_init(IntelIOMMUState *s)
/*
* Rsvd field masks for spte
*/
- vtd_paging_entry_rsvd_field[0] = ~0ULL;
- vtd_paging_entry_rsvd_field[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[5] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[6] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[7] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits);
- vtd_paging_entry_rsvd_field[8] = VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd[0] = ~0ULL;
+ vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
+
+ vtd_spte_rsvd_large[0] = ~0ULL;
+ vtd_spte_rsvd_large[1] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd_large[4] = VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_bits);
if (x86_iommu_ir_supported(x86_iommu)) {
s->ecap |= VTD_ECAP_IR | VTD_ECAP_MHMV;
--
2.20.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2 2/2] intel_iommu: TM field should not be in reserved bits
@ 2019-10-08 2:34 ` qi1.zhang
0 siblings, 0 replies; 7+ messages in thread
From: qi1.zhang @ 2019-10-08 2:34 UTC (permalink / raw)
To: qemu-devel; +Cc: qi1.zhang, ehabkost, mst, pbonzini, yadong.qi, rth
From: "Zhang, Qi" <qi1.zhang@intel.com>
When dt is supported, TM field should not be Reserved(0).
Refer to VT-d Spec 9.8
Signed-off-by: Zhang, Qi <qi1.zhang@intel.com>
Signed-off-by: Qi, Yadong <yadong.qi@intel.com>
---
hw/i386/intel_iommu.c | 12 ++++++++----
hw/i386/intel_iommu_internal.h | 17 +++++++++++++----
2 files changed, 21 insertions(+), 8 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index a118efaeaf..d62604ece3 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -3549,15 +3549,19 @@ static void vtd_init(IntelIOMMUState *s)
* Rsvd field masks for spte
*/
vtd_spte_rsvd[0] = ~0ULL;
- vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits,
+ x86_iommu->dt_supported);
vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
vtd_spte_rsvd_large[0] = ~0ULL;
- vtd_spte_rsvd_large[1] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits);
- vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits);
- vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits);
+ vtd_spte_rsvd_large[1] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits,
+ x86_iommu->dt_supported);
+ vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits,
+ x86_iommu->dt_supported);
+ vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits,
+ x86_iommu->dt_supported);
vtd_spte_rsvd_large[4] = VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_bits);
if (x86_iommu_ir_supported(x86_iommu)) {
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index c1235a7063..3a839a8925 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -387,7 +387,9 @@ typedef union VTDInvDesc VTDInvDesc;
#define VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO 0xffff0000ffe0fff8
/* Rsvd field masks for spte */
-#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw) \
+#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw, dt_supported) \
+ dt_supported ? \
+ (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
(0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
#define VTD_SPTE_PAGE_L2_RSVD_MASK(aw) \
(0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
@@ -395,11 +397,17 @@ typedef union VTDInvDesc VTDInvDesc;
(0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
#define VTD_SPTE_PAGE_L4_RSVD_MASK(aw) \
(0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
-#define VTD_SPTE_LPAGE_L1_RSVD_MASK(aw) \
+#define VTD_SPTE_LPAGE_L1_RSVD_MASK(aw, dt_supported) \
+ dt_supported ? \
+ (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
(0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
-#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw) \
+#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw, dt_supported) \
+ dt_supported ? \
+ (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
(0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
-#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw) \
+#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw, dt_supported) \
+ dt_supported ? \
+ (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
(0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
#define VTD_SPTE_LPAGE_L4_RSVD_MASK(aw) \
(0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
@@ -506,5 +514,6 @@ typedef struct VTDRootEntry VTDRootEntry;
#define VTD_SL_W (1ULL << 1)
#define VTD_SL_PT_BASE_ADDR_MASK(aw) (~(VTD_PAGE_SIZE - 1) & VTD_HAW_MASK(aw))
#define VTD_SL_IGN_COM 0xbff0000000000000ULL
+#define VTD_SL_TM (1ULL << 62)
#endif
--
2.20.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* RE: [PATCH v1 0/2] TM field check failed
2019-10-08 2:34 ` [PATCH v1 " qi1.zhang
` (2 preceding siblings ...)
(?)
@ 2019-10-12 5:05 ` Zhang, Qi1
-1 siblings, 0 replies; 7+ messages in thread
From: Zhang, Qi1 @ 2019-10-12 5:05 UTC (permalink / raw)
To: qemu-devel@nongnu.org
Cc: ehabkost@redhat.com, mst@redhat.com, pbonzini@redhat.com,
Qi, Yadong, rth@twiddle.net
Hello, everyone
May I know you have comments on this patch set? Thank you!
BRs
Qi Zhang
> -----Original Message-----
> From: Zhang, Qi1 <qi1.zhang@intel.com>
> Sent: Tuesday, October 8, 2019 10:35 AM
> To: qemu-devel@nongnu.org
> Cc: mst@redhat.com; marcel.apfelbaum@gmail.com; pbonzini@redhat.com;
> rth@twiddle.net; ehabkost@redhat.com; Zhang, Qi1 <qi1.zhang@intel.com>;
> Qi, Yadong <yadong.qi@intel.com>
> Subject: [PATCH v1 0/2] TM field check failed
>
> From: "Zhang, Qi" <qi1.zhang@intel.com>
>
> spilt the reserved fields arrays and remove TM field from reserved bits
>
> Changelog V1:
> add descriptons
>
> Zhang, Qi (2):
> intel_iommu: split the resevred fields arrays into two ones
> intel_iommu: TM field should not be in reserved bits
>
> hw/i386/intel_iommu.c | 35 ++++++++++++++++++++--------------
> hw/i386/intel_iommu_internal.h | 17 +++++++++++++----
> 2 files changed, 34 insertions(+), 18 deletions(-)
>
> --
> 2.20.1
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2019-10-12 5:06 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
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2019-10-08 1:39 [PATCH 0/2] TM field check failed qi1.zhang
2019-10-08 2:34 ` [PATCH v1 " qi1.zhang
2019-10-08 1:39 ` [PATCH 1/2] intel_iommu: split the resevred fields arrays into two ones qi1.zhang
2019-10-08 2:34 ` [PATCH v1 " qi1.zhang
2019-10-08 1:39 ` [PATCH 2/2] intel_iommu: TM field should not be in reserved bits qi1.zhang
2019-10-08 2:34 ` [PATCH v2 " qi1.zhang
2019-10-12 5:05 ` [PATCH v1 0/2] TM field check failed Zhang, Qi1
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