* [PATCH v3 00/10] xen/arm: smmuv3: Merge Linux fixes to Xen
@ 2022-09-05 16:30 Rahul Singh
2022-09-05 16:30 ` [PATCH v3 01/10] xen/arm: smmuv3: Fix l1 stream table size in the error message Rahul Singh
` (9 more replies)
0 siblings, 10 replies; 17+ messages in thread
From: Rahul Singh @ 2022-09-05 16:30 UTC (permalink / raw)
To: xen-devel
Cc: Bertrand Marquis, Stefano Stabellini, Julien Grall,
Volodymyr Babchuk
This patch series merge the applicable Linux fixes to Xen.
Bixuan Cui (1):
xen/arm: smmuv3: Change *array into *const array
Christophe JAILLET (1):
xen/arm: smmuv3: Avoid open coded arithmetic in memory allocation
Gustavo A. R. Silva (1):
xen/arm: smmuv3: Fix fall-through warning for Clang
Jean-Philippe Brucker (2):
xen/arm: smmuv3: Fix endianness annotations
xen/arm: smmuv3: Move definitions to a header
Robin Murphy (1):
xen/arm: smmuv3: Remove the page 1 fixup
Zenghui Yu (2):
xen/arm: smmuv3: Fix l1 stream table size in the error message
xen/arm: smmuv3: Remove the unused fields for PREFETCH_CONFIG command
Zhen Lei (1):
xen/arm: smmuv3: Remove unnecessary oom message
Zhou Wang (1):
xen/arm: smmuv3: Ensure queue is read after updating prod pointer
xen/drivers/passthrough/arm/smmu-v3.c | 741 ++------------------------
xen/drivers/passthrough/arm/smmu-v3.h | 672 +++++++++++++++++++++++
2 files changed, 708 insertions(+), 705 deletions(-)
create mode 100644 xen/drivers/passthrough/arm/smmu-v3.h
--
2.25.1
^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH v3 01/10] xen/arm: smmuv3: Fix l1 stream table size in the error message 2022-09-05 16:30 [PATCH v3 00/10] xen/arm: smmuv3: Merge Linux fixes to Xen Rahul Singh @ 2022-09-05 16:30 ` Rahul Singh 2022-09-05 16:30 ` [PATCH v3 02/10] xen/arm: smmuv3: Fix endianness annotations Rahul Singh ` (8 subsequent siblings) 9 siblings, 0 replies; 17+ messages in thread From: Rahul Singh @ 2022-09-05 16:30 UTC (permalink / raw) To: xen-devel Cc: Zenghui Yu, Bertrand Marquis, Stefano Stabellini, Julien Grall, Volodymyr Babchuk, Will Deacon From: Zenghui Yu <yuzenghui@huawei.com> Backport Linux commit dc898eb84b25. This is the clean backport without any changes. The actual size of level-1 stream table is l1size. This looks like an oversight on commit d2e88e7c081ef ("iommu/arm-smmu: Fix LOG2SIZE setting for 2-level stream tables") which forgot to update the @size in error message as well. As memory allocation failure is already bad enough, nothing worse would happen. But let's be careful. Signed-off-by: Zenghui Yu <yuzenghui@huawei.com> Link: https://lore.kernel.org/r/20200826141758.341-1-yuzenghui@huawei.com Signed-off-by: Will Deacon <will@kernel.org> Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git dc898eb84b25 Acked-by: Stefano Stabellini <sstabellini@kernel.org> Signed-off-by: Rahul Singh <rahul.singh@arm.com> --- Changes in v3: - Added Stefano Acked-by Changes in v2: - fix commit msg --- --- xen/drivers/passthrough/arm/smmu-v3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthrough/arm/smmu-v3.c index f2562acc38..340609264d 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.c +++ b/xen/drivers/passthrough/arm/smmu-v3.c @@ -2348,7 +2348,7 @@ static int arm_smmu_init_strtab_2lvl(struct arm_smmu_device *smmu) if (!strtab) { dev_err(smmu->dev, "failed to allocate l1 stream table (%u bytes)\n", - size); + l1size); return -ENOMEM; } cfg->strtab = strtab; -- 2.25.1 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v3 02/10] xen/arm: smmuv3: Fix endianness annotations 2022-09-05 16:30 [PATCH v3 00/10] xen/arm: smmuv3: Merge Linux fixes to Xen Rahul Singh 2022-09-05 16:30 ` [PATCH v3 01/10] xen/arm: smmuv3: Fix l1 stream table size in the error message Rahul Singh @ 2022-09-05 16:30 ` Rahul Singh 2022-09-05 16:30 ` [PATCH v3 03/10] xen/arm: smmuv3: Ensure queue is read after updating prod pointer Rahul Singh ` (7 subsequent siblings) 9 siblings, 0 replies; 17+ messages in thread From: Rahul Singh @ 2022-09-05 16:30 UTC (permalink / raw) To: xen-devel Cc: Jean-Philippe Brucker, Bertrand Marquis, Stefano Stabellini, Julien Grall, Volodymyr Babchuk, Robin Murphy, Will Deacon From: Jean-Philippe Brucker <jean-philippe@linaro.org> Backport Linux commit 376cdf66f624. This is the clean backport without any changes. When building with C=1, sparse reports some issues regarding endianness annotations: arm-smmu-v3.c:221:26: warning: cast to restricted __le64 arm-smmu-v3.c:221:24: warning: incorrect type in assignment (different base types) arm-smmu-v3.c:221:24: expected restricted __le64 [usertype] arm-smmu-v3.c:221:24: got unsigned long long [usertype] arm-smmu-v3.c:229:20: warning: incorrect type in argument 1 (different base types) arm-smmu-v3.c:229:20: expected restricted __le64 [usertype] *[assigned] dst arm-smmu-v3.c:229:20: got unsigned long long [usertype] *ent arm-smmu-v3.c:229:25: warning: incorrect type in argument 2 (different base types) arm-smmu-v3.c:229:25: expected unsigned long long [usertype] *[assigned] src arm-smmu-v3.c:229:25: got restricted __le64 [usertype] * arm-smmu-v3.c:396:20: warning: incorrect type in argument 1 (different base types) arm-smmu-v3.c:396:20: expected restricted __le64 [usertype] *[assigned] dst arm-smmu-v3.c:396:20: got unsigned long long * arm-smmu-v3.c:396:25: warning: incorrect type in argument 2 (different base types) arm-smmu-v3.c:396:25: expected unsigned long long [usertype] *[assigned] src arm-smmu-v3.c:396:25: got restricted __le64 [usertype] * arm-smmu-v3.c:1349:32: warning: invalid assignment: |= arm-smmu-v3.c:1349:32: left side has type restricted __le64 arm-smmu-v3.c:1349:32: right side has type unsigned long arm-smmu-v3.c:1396:53: warning: incorrect type in argument 3 (different base types) arm-smmu-v3.c:1396:53: expected restricted __le64 [usertype] *dst arm-smmu-v3.c:1396:53: got unsigned long long [usertype] *strtab arm-smmu-v3.c:1424:39: warning: incorrect type in argument 1 (different base types) arm-smmu-v3.c:1424:39: expected unsigned long long [usertype] *[assigned] strtab arm-smmu-v3.c:1424:39: got restricted __le64 [usertype] *l2ptr While harmless, they are incorrect and could hide actual errors during development. Fix them. Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Reviewed-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/20200918141856.629722-1-jean-philippe@linaro.org Signed-off-by: Will Deacon <will@kernel.org> Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 376cdf66f624 Acked-by: Stefano Stabellini <sstabellini@kernel.org> Signed-off-by: Rahul Singh <rahul.singh@arm.com> --- Changes in v3: - Added Stefano Acked-by Changes in v2: - fix commit msg --- --- xen/drivers/passthrough/arm/smmu-v3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthrough/arm/smmu-v3.c index 340609264d..64d39bb4d3 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.c +++ b/xen/drivers/passthrough/arm/smmu-v3.c @@ -1037,7 +1037,7 @@ static int queue_insert_raw(struct arm_smmu_queue *q, u64 *ent) return 0; } -static void queue_read(__le64 *dst, u64 *src, size_t n_dwords) +static void queue_read(u64 *dst, __le64 *src, size_t n_dwords) { int i; @@ -1436,7 +1436,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, arm_smmu_cmdq_issue_cmd(smmu, &prefetch_cmd); } -static void arm_smmu_init_bypass_stes(u64 *strtab, unsigned int nent) +static void arm_smmu_init_bypass_stes(__le64 *strtab, unsigned int nent) { unsigned int i; -- 2.25.1 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v3 03/10] xen/arm: smmuv3: Ensure queue is read after updating prod pointer 2022-09-05 16:30 [PATCH v3 00/10] xen/arm: smmuv3: Merge Linux fixes to Xen Rahul Singh 2022-09-05 16:30 ` [PATCH v3 01/10] xen/arm: smmuv3: Fix l1 stream table size in the error message Rahul Singh 2022-09-05 16:30 ` [PATCH v3 02/10] xen/arm: smmuv3: Fix endianness annotations Rahul Singh @ 2022-09-05 16:30 ` Rahul Singh 2022-09-05 16:37 ` Julien Grall 2022-09-05 16:30 ` [PATCH v3 04/10] xen/arm: smmuv3: Move definitions to a header Rahul Singh ` (6 subsequent siblings) 9 siblings, 1 reply; 17+ messages in thread From: Rahul Singh @ 2022-09-05 16:30 UTC (permalink / raw) To: xen-devel Cc: Zhou Wang, Bertrand Marquis, Stefano Stabellini, Julien Grall, Volodymyr Babchuk, Will Deacon From: Zhou Wang <wangzhou1@hisilicon.com> Backport Linux commit a76a37777f2c. Rename __iomb to iomb() while merging to get in sync with other Xen definitions. Reading the 'prod' MMIO register in order to determine whether or not there is valid data beyond 'cons' for a given queue does not provide sufficient dependency ordering, as the resulting access is address dependent only on 'cons' and can therefore be speculated ahead of time, potentially allowing stale data to be read by the CPU. Use readl() instead of readl_relaxed() when updating the shadow copy of the 'prod' pointer, so that all speculated memory reads from the corresponding queue can occur only from valid slots. Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> Link: https://lore.kernel.org/r/1601281922-117296-1-git-send-email-wangzhou1@hisilicon.com [will: Use readl() instead of explicit barrier. Update 'cons' side to match.] Signed-off-by: Will Deacon <will@kernel.org> Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git a76a37777f2c Signed-off-by: Rahul Singh <rahul.singh@arm.com> --- Changes in v3: - rename __iomb() to iomb() and also move it from common file to smmu-v3.c file Changes in v2: - fix commit msg - add _iomb changes also from the origin patch --- xen/drivers/passthrough/arm/smmu-v3.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthrough/arm/smmu-v3.c index 64d39bb4d3..e632c75b21 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.c +++ b/xen/drivers/passthrough/arm/smmu-v3.c @@ -107,6 +107,8 @@ typedef paddr_t dma_addr_t; typedef paddr_t phys_addr_t; typedef unsigned int gfp_t; +#define iomb() dmb(osh) + #define platform_device device #define GFP_KERNEL 0 @@ -951,7 +953,7 @@ static void queue_sync_cons_out(struct arm_smmu_queue *q) * Ensure that all CPU accesses (reads and writes) to the queue * are complete before we update the cons pointer. */ - mb(); + iomb(); writel_relaxed(q->llq.cons, q->cons_reg); } @@ -963,8 +965,15 @@ static void queue_inc_cons(struct arm_smmu_ll_queue *q) static int queue_sync_prod_in(struct arm_smmu_queue *q) { + u32 prod; int ret = 0; - u32 prod = readl_relaxed(q->prod_reg); + + /* + * We can't use the _relaxed() variant here, as we must prevent + * speculative reads of the queue before we have determined that + * prod has indeed moved. + */ + prod = readl(q->prod_reg); if (Q_OVF(prod) != Q_OVF(q->llq.prod)) ret = -EOVERFLOW; -- 2.25.1 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH v3 03/10] xen/arm: smmuv3: Ensure queue is read after updating prod pointer 2022-09-05 16:30 ` [PATCH v3 03/10] xen/arm: smmuv3: Ensure queue is read after updating prod pointer Rahul Singh @ 2022-09-05 16:37 ` Julien Grall 2022-09-05 16:49 ` Rahul Singh 0 siblings, 1 reply; 17+ messages in thread From: Julien Grall @ 2022-09-05 16:37 UTC (permalink / raw) To: Rahul Singh, xen-devel Cc: Zhou Wang, Bertrand Marquis, Stefano Stabellini, Volodymyr Babchuk, Will Deacon On 05/09/2022 17:30, Rahul Singh wrote: > From: Zhou Wang <wangzhou1@hisilicon.com> > > Backport Linux commit a76a37777f2c. Rename __iomb to iomb() while > merging to get in sync with other Xen definitions. > > Reading the 'prod' MMIO register in order to determine whether or > not there is valid data beyond 'cons' for a given queue does not > provide sufficient dependency ordering, as the resulting access is > address dependent only on 'cons' and can therefore be speculated > ahead of time, potentially allowing stale data to be read by the > CPU. > > Use readl() instead of readl_relaxed() when updating the shadow copy > of the 'prod' pointer, so that all speculated memory reads from the > corresponding queue can occur only from valid slots. > > Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> > Link: https://lore.kernel.org/r/1601281922-117296-1-git-send-email-wangzhou1@hisilicon.com > [will: Use readl() instead of explicit barrier. Update 'cons' side to match.] > Signed-off-by: Will Deacon <will@kernel.org> > Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git a76a37777f2c > Signed-off-by: Rahul Singh <rahul.singh@arm.com> > --- > Changes in v3: > - rename __iomb() to iomb() and also move it from common file to > smmu-v3.c file Hmmm... Quoting Bertrand: "We need the __iomb as “linux compatibility” in fact so I would suggest for now to only introduce it at the beginning of smmu-v3.c with other linux compatibility stuff to prevent adding this to Xen overall." Which I also agreed. I couldn't a more recent conversation explaining your approach. Can you outline why you didn't follow the approached discussed? Cheers, > Changes in v2: > - fix commit msg > - add _iomb changes also from the origin patch > --- > xen/drivers/passthrough/arm/smmu-v3.c | 13 +++++++++++-- > 1 file changed, 11 insertions(+), 2 deletions(-) > > diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthrough/arm/smmu-v3.c > index 64d39bb4d3..e632c75b21 100644 > --- a/xen/drivers/passthrough/arm/smmu-v3.c > +++ b/xen/drivers/passthrough/arm/smmu-v3.c > @@ -107,6 +107,8 @@ typedef paddr_t dma_addr_t; > typedef paddr_t phys_addr_t; > typedef unsigned int gfp_t; > > +#define iomb() dmb(osh) > + > #define platform_device device > > #define GFP_KERNEL 0 > @@ -951,7 +953,7 @@ static void queue_sync_cons_out(struct arm_smmu_queue *q) > * Ensure that all CPU accesses (reads and writes) to the queue > * are complete before we update the cons pointer. > */ > - mb(); > + iomb(); > writel_relaxed(q->llq.cons, q->cons_reg); > } > > @@ -963,8 +965,15 @@ static void queue_inc_cons(struct arm_smmu_ll_queue *q) > > static int queue_sync_prod_in(struct arm_smmu_queue *q) > { > + u32 prod; > int ret = 0; > - u32 prod = readl_relaxed(q->prod_reg); > + > + /* > + * We can't use the _relaxed() variant here, as we must prevent > + * speculative reads of the queue before we have determined that > + * prod has indeed moved. > + */ > + prod = readl(q->prod_reg); > > if (Q_OVF(prod) != Q_OVF(q->llq.prod)) > ret = -EOVERFLOW; -- Julien Grall ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 03/10] xen/arm: smmuv3: Ensure queue is read after updating prod pointer 2022-09-05 16:37 ` Julien Grall @ 2022-09-05 16:49 ` Rahul Singh 2022-09-05 16:55 ` Julien Grall 0 siblings, 1 reply; 17+ messages in thread From: Rahul Singh @ 2022-09-05 16:49 UTC (permalink / raw) To: Julien Grall Cc: xen-devel, Zhou Wang, Bertrand Marquis, Stefano Stabellini, Volodymyr Babchuk, Will Deacon Hi Julien, > On 5 Sep 2022, at 5:37 pm, Julien Grall <julien@xen.org> wrote: > > > > On 05/09/2022 17:30, Rahul Singh wrote: >> From: Zhou Wang <wangzhou1@hisilicon.com> >> Backport Linux commit a76a37777f2c. Rename __iomb to iomb() while >> merging to get in sync with other Xen definitions. >> Reading the 'prod' MMIO register in order to determine whether or >> not there is valid data beyond 'cons' for a given queue does not >> provide sufficient dependency ordering, as the resulting access is >> address dependent only on 'cons' and can therefore be speculated >> ahead of time, potentially allowing stale data to be read by the >> CPU. >> Use readl() instead of readl_relaxed() when updating the shadow copy >> of the 'prod' pointer, so that all speculated memory reads from the >> corresponding queue can occur only from valid slots. >> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> >> Link: https://lore.kernel.org/r/1601281922-117296-1-git-send-email-wangzhou1@hisilicon.com >> [will: Use readl() instead of explicit barrier. Update 'cons' side to match.] >> Signed-off-by: Will Deacon <will@kernel.org> >> Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git a76a37777f2c >> Signed-off-by: Rahul Singh <rahul.singh@arm.com> >> --- >> Changes in v3: >> - rename __iomb() to iomb() and also move it from common file to >> smmu-v3.c file > > Hmmm... Quoting Bertrand: > > "We need the __iomb as “linux compatibility” in fact so I would suggest for now to only introduce it at the beginning of smmu-v3.c with other linux compatibility stuff to prevent adding this to Xen overall." > > Which I also agreed. I couldn't a more recent conversation explaining your approach. Can you outline why you didn't follow the approached discussed? > I am really sorry that I missed the naming and when I made the patch in my mind there was a comment from Stefano to rename the __iomb() to iomb(). I will send only this patch after fixing or do you want me to send the whole series? Regards, Rahul ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 03/10] xen/arm: smmuv3: Ensure queue is read after updating prod pointer 2022-09-05 16:49 ` Rahul Singh @ 2022-09-05 16:55 ` Julien Grall 2022-09-06 7:19 ` Bertrand Marquis 0 siblings, 1 reply; 17+ messages in thread From: Julien Grall @ 2022-09-05 16:55 UTC (permalink / raw) To: Rahul Singh Cc: xen-devel, Zhou Wang, Bertrand Marquis, Stefano Stabellini, Volodymyr Babchuk, Will Deacon On 05/09/2022 17:49, Rahul Singh wrote: > Hi Julien, Hi Rahul, > >> On 5 Sep 2022, at 5:37 pm, Julien Grall <julien@xen.org> wrote: >> >> >> >> On 05/09/2022 17:30, Rahul Singh wrote: >>> From: Zhou Wang <wangzhou1@hisilicon.com> >>> Backport Linux commit a76a37777f2c. Rename __iomb to iomb() while >>> merging to get in sync with other Xen definitions. >>> Reading the 'prod' MMIO register in order to determine whether or >>> not there is valid data beyond 'cons' for a given queue does not >>> provide sufficient dependency ordering, as the resulting access is >>> address dependent only on 'cons' and can therefore be speculated >>> ahead of time, potentially allowing stale data to be read by the >>> CPU. >>> Use readl() instead of readl_relaxed() when updating the shadow copy >>> of the 'prod' pointer, so that all speculated memory reads from the >>> corresponding queue can occur only from valid slots. >>> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> >>> Link: https://lore.kernel.org/r/1601281922-117296-1-git-send-email-wangzhou1@hisilicon.com >>> [will: Use readl() instead of explicit barrier. Update 'cons' side to match.] >>> Signed-off-by: Will Deacon <will@kernel.org> >>> Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git a76a37777f2c >>> Signed-off-by: Rahul Singh <rahul.singh@arm.com> >>> --- >>> Changes in v3: >>> - rename __iomb() to iomb() and also move it from common file to >>> smmu-v3.c file >> >> Hmmm... Quoting Bertrand: >> >> "We need the __iomb as “linux compatibility” in fact so I would suggest for now to only introduce it at the beginning of smmu-v3.c with other linux compatibility stuff to prevent adding this to Xen overall." >> >> Which I also agreed. I couldn't a more recent conversation explaining your approach. Can you outline why you didn't follow the approached discussed? >> > > I am really sorry that I missed the naming and when I made the patch in my mind there was a comment from Stefano to > rename the __iomb() to iomb(). I will send only this patch after fixing or do you want me to send the whole series? I would be fine if you only resend this patch. Also, looking at the other patches, you added the Acked-by before your Signed-off-by. In general, the tags are ordered chronologically, so this should be inverted. I can deal with that on commit once Bertrand confirmed he is happy with the series. Cheers, -- Julien Grall ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v3 03/10] xen/arm: smmuv3: Ensure queue is read after updating prod pointer 2022-09-05 16:55 ` Julien Grall @ 2022-09-06 7:19 ` Bertrand Marquis 0 siblings, 0 replies; 17+ messages in thread From: Bertrand Marquis @ 2022-09-06 7:19 UTC (permalink / raw) To: Julien Grall Cc: Rahul Singh, xen-devel, Zhou Wang, Stefano Stabellini, Volodymyr Babchuk, Will Deacon Hi Julien, > On 5 Sep 2022, at 17:55, Julien Grall <julien@xen.org> wrote: > > > > On 05/09/2022 17:49, Rahul Singh wrote: >> Hi Julien, > > Hi Rahul, > >>> On 5 Sep 2022, at 5:37 pm, Julien Grall <julien@xen.org> wrote: >>> >>> >>> >>> On 05/09/2022 17:30, Rahul Singh wrote: >>>> From: Zhou Wang <wangzhou1@hisilicon.com> >>>> Backport Linux commit a76a37777f2c. Rename __iomb to iomb() while >>>> merging to get in sync with other Xen definitions. >>>> Reading the 'prod' MMIO register in order to determine whether or >>>> not there is valid data beyond 'cons' for a given queue does not >>>> provide sufficient dependency ordering, as the resulting access is >>>> address dependent only on 'cons' and can therefore be speculated >>>> ahead of time, potentially allowing stale data to be read by the >>>> CPU. >>>> Use readl() instead of readl_relaxed() when updating the shadow copy >>>> of the 'prod' pointer, so that all speculated memory reads from the >>>> corresponding queue can occur only from valid slots. >>>> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com> >>>> Link: https://lore.kernel.org/r/1601281922-117296-1-git-send-email-wangzhou1@hisilicon.com >>>> [will: Use readl() instead of explicit barrier. Update 'cons' side to match.] >>>> Signed-off-by: Will Deacon <will@kernel.org> >>>> Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git a76a37777f2c >>>> Signed-off-by: Rahul Singh <rahul.singh@arm.com> >>>> --- >>>> Changes in v3: >>>> - rename __iomb() to iomb() and also move it from common file to >>>> smmu-v3.c file >>> >>> Hmmm... Quoting Bertrand: >>> >>> "We need the __iomb as “linux compatibility” in fact so I would suggest for now to only introduce it at the beginning of smmu-v3.c with other linux compatibility stuff to prevent adding this to Xen overall." >>> >>> Which I also agreed. I couldn't a more recent conversation explaining your approach. Can you outline why you didn't follow the approached discussed? >>> >> I am really sorry that I missed the naming and when I made the patch in my mind there was a comment from Stefano to >> rename the __iomb() to iomb(). I will send only this patch after fixing or do you want me to send the whole series? > > I would be fine if you only resend this patch. > > Also, looking at the other patches, you added the Acked-by before your Signed-off-by. In general, the tags are ordered chronologically, so this should be inverted. I can deal with that on commit once Bertrand confirmed he is happy with the series. With the acked-by needing to be moved and the iomb part, it will make your life easier if Rahul just resend the serie so Rahul please send a v4. Cheers Bertrand > > Cheers, > > -- > Julien Grall ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v3 04/10] xen/arm: smmuv3: Move definitions to a header 2022-09-05 16:30 [PATCH v3 00/10] xen/arm: smmuv3: Merge Linux fixes to Xen Rahul Singh ` (2 preceding siblings ...) 2022-09-05 16:30 ` [PATCH v3 03/10] xen/arm: smmuv3: Ensure queue is read after updating prod pointer Rahul Singh @ 2022-09-05 16:30 ` Rahul Singh 2022-09-05 22:20 ` Stefano Stabellini 2022-09-05 16:30 ` [PATCH v3 05/10] xen/arm: smmuv3: Remove the page 1 fixup Rahul Singh ` (5 subsequent siblings) 9 siblings, 1 reply; 17+ messages in thread From: Rahul Singh @ 2022-09-05 16:30 UTC (permalink / raw) To: xen-devel Cc: Jean-Philippe Brucker, Bertrand Marquis, Stefano Stabellini, Julien Grall, Volodymyr Babchuk, Eric Auger, Jonathan Cameron, Will Deacon From: Jean-Philippe Brucker <jean-philippe@linaro.org> Backport Linux commit e881e7839fba. Also, move Xen related struct definition to header to get it compiled. Allow sharing structure definitions with the upcoming SVA support for Arm SMMUv3, by moving them to a separate header. We could surgically extract only what is needed but keeping all definitions in one place looks nicer. Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/20200918101852.582559-8-jean-philippe@linaro.org Signed-off-by: Will Deacon <will@kernel.org> Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git e881e7839fba Signed-off-by: Rahul Singh <rahul.singh@arm.com> --- Changes in v3: - remove clean backport msg in commit msg Changes in v2: - fix commit msg - also move struct definition to header file to sync with Linux patch --- xen/drivers/passthrough/arm/smmu-v3.c | 665 +------------------------ xen/drivers/passthrough/arm/smmu-v3.h | 674 ++++++++++++++++++++++++++ 2 files changed, 675 insertions(+), 664 deletions(-) create mode 100644 xen/drivers/passthrough/arm/smmu-v3.h diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthrough/arm/smmu-v3.c index e632c75b21..e65b226b85 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.c +++ b/xen/drivers/passthrough/arm/smmu-v3.c @@ -90,6 +90,7 @@ #include <asm/iommu_fwspec.h> #include <asm/platform.h> +#include "smmu-v3.h" #define ARM_SMMU_VTCR_SH_IS 3 #define ARM_SMMU_VTCR_RGN_WBWA 1 @@ -103,22 +104,12 @@ #define ARM_SMMU_VTCR_PS_52_BIT 0x6ULL /* Linux compatibility functions. */ -typedef paddr_t dma_addr_t; -typedef paddr_t phys_addr_t; -typedef unsigned int gfp_t; - #define iomb() dmb(osh) #define platform_device device #define GFP_KERNEL 0 -/* Alias to Xen lock functions */ -#define mutex spinlock -#define mutex_init spin_lock_init -#define mutex_lock spin_lock -#define mutex_unlock spin_unlock - /* Device logger functions */ #define dev_name(dev) dt_node_full_name(dev->of_node) #define dev_dbg(dev, fmt, ...) \ @@ -159,12 +150,6 @@ typedef unsigned int gfp_t; #define readl_relaxed_poll_timeout(addr, val, cond, delay_us, timeout_us) \ readx_poll_timeout(readl_relaxed, addr, val, cond, delay_us, timeout_us) -#define FIELD_PREP(_mask, _val) \ - (((typeof(_mask))(_val) << (ffs64(_mask) - 1)) & (_mask)) - -#define FIELD_GET(_mask, _reg) \ - ((typeof(_mask))(((_reg) & (_mask)) >> (ffs64(_mask) - 1))) - /* * Helpers for DMA allocation. Just the function name is reused for * porting code, these allocation are not managed allocations @@ -197,27 +182,6 @@ static void *dmam_alloc_coherent(struct device *dev, size_t size, return vaddr; } - -/* Xen specific code. */ -struct iommu_domain { - /* Runtime SMMU configuration for this iommu_domain */ - atomic_t ref; - /* - * Used to link iommu_domain contexts for a same domain. - * There is at least one per-SMMU to used by the domain. - */ - struct list_head list; -}; - -/* Describes information required for a Xen domain */ -struct arm_smmu_xen_domain { - spinlock_t lock; - - /* List of iommu domains associated to this domain */ - struct list_head contexts; -}; - - /* Keep a list of devices associated with this driver */ static DEFINE_SPINLOCK(arm_smmu_devices_lock); static LIST_HEAD(arm_smmu_devices); @@ -261,635 +225,8 @@ static int platform_get_irq_byname_optional(struct device *dev, } /* Start of Linux SMMUv3 code */ -/* MMIO registers */ -#define ARM_SMMU_IDR0 0x0 -#define IDR0_ST_LVL GENMASK(28, 27) -#define IDR0_ST_LVL_2LVL 1 -#define IDR0_STALL_MODEL GENMASK(25, 24) -#define IDR0_STALL_MODEL_STALL 0 -#define IDR0_STALL_MODEL_FORCE 2 -#define IDR0_TTENDIAN GENMASK(22, 21) -#define IDR0_TTENDIAN_MIXED 0 -#define IDR0_TTENDIAN_LE 2 -#define IDR0_TTENDIAN_BE 3 -#define IDR0_CD2L (1 << 19) -#define IDR0_VMID16 (1 << 18) -#define IDR0_PRI (1 << 16) -#define IDR0_SEV (1 << 14) -#define IDR0_MSI (1 << 13) -#define IDR0_ASID16 (1 << 12) -#define IDR0_ATS (1 << 10) -#define IDR0_HYP (1 << 9) -#define IDR0_COHACC (1 << 4) -#define IDR0_TTF GENMASK(3, 2) -#define IDR0_TTF_AARCH64 2 -#define IDR0_TTF_AARCH32_64 3 -#define IDR0_S1P (1 << 1) -#define IDR0_S2P (1 << 0) - -#define ARM_SMMU_IDR1 0x4 -#define IDR1_TABLES_PRESET (1 << 30) -#define IDR1_QUEUES_PRESET (1 << 29) -#define IDR1_REL (1 << 28) -#define IDR1_CMDQS GENMASK(25, 21) -#define IDR1_EVTQS GENMASK(20, 16) -#define IDR1_PRIQS GENMASK(15, 11) -#define IDR1_SSIDSIZE GENMASK(10, 6) -#define IDR1_SIDSIZE GENMASK(5, 0) - -#define ARM_SMMU_IDR5 0x14 -#define IDR5_STALL_MAX GENMASK(31, 16) -#define IDR5_GRAN64K (1 << 6) -#define IDR5_GRAN16K (1 << 5) -#define IDR5_GRAN4K (1 << 4) -#define IDR5_OAS GENMASK(2, 0) -#define IDR5_OAS_32_BIT 0 -#define IDR5_OAS_36_BIT 1 -#define IDR5_OAS_40_BIT 2 -#define IDR5_OAS_42_BIT 3 -#define IDR5_OAS_44_BIT 4 -#define IDR5_OAS_48_BIT 5 -#define IDR5_OAS_52_BIT 6 -#define IDR5_VAX GENMASK(11, 10) -#define IDR5_VAX_52_BIT 1 - -#define ARM_SMMU_CR0 0x20 -#define CR0_ATSCHK (1 << 4) -#define CR0_CMDQEN (1 << 3) -#define CR0_EVTQEN (1 << 2) -#define CR0_PRIQEN (1 << 1) -#define CR0_SMMUEN (1 << 0) - -#define ARM_SMMU_CR0ACK 0x24 - -#define ARM_SMMU_CR1 0x28 -#define CR1_TABLE_SH GENMASK(11, 10) -#define CR1_TABLE_OC GENMASK(9, 8) -#define CR1_TABLE_IC GENMASK(7, 6) -#define CR1_QUEUE_SH GENMASK(5, 4) -#define CR1_QUEUE_OC GENMASK(3, 2) -#define CR1_QUEUE_IC GENMASK(1, 0) -/* CR1 cacheability fields don't quite follow the usual TCR-style encoding */ -#define CR1_CACHE_NC 0 -#define CR1_CACHE_WB 1 -#define CR1_CACHE_WT 2 - -#define ARM_SMMU_CR2 0x2c -#define CR2_PTM (1 << 2) -#define CR2_RECINVSID (1 << 1) -#define CR2_E2H (1 << 0) - -#define ARM_SMMU_GBPA 0x44 -#define GBPA_UPDATE (1U << 31) -#define GBPA_ABORT (1 << 20) - -#define ARM_SMMU_IRQ_CTRL 0x50 -#define IRQ_CTRL_EVTQ_IRQEN (1 << 2) -#define IRQ_CTRL_PRIQ_IRQEN (1 << 1) -#define IRQ_CTRL_GERROR_IRQEN (1 << 0) - -#define ARM_SMMU_IRQ_CTRLACK 0x54 - -#define ARM_SMMU_GERROR 0x60 -#define GERROR_SFM_ERR (1 << 8) -#define GERROR_MSI_GERROR_ABT_ERR (1 << 7) -#define GERROR_MSI_PRIQ_ABT_ERR (1 << 6) -#define GERROR_MSI_EVTQ_ABT_ERR (1 << 5) -#define GERROR_MSI_CMDQ_ABT_ERR (1 << 4) -#define GERROR_PRIQ_ABT_ERR (1 << 3) -#define GERROR_EVTQ_ABT_ERR (1 << 2) -#define GERROR_CMDQ_ERR (1 << 0) -#define GERROR_ERR_MASK 0xfd - -#define ARM_SMMU_GERRORN 0x64 - -#define ARM_SMMU_GERROR_IRQ_CFG0 0x68 -#define ARM_SMMU_GERROR_IRQ_CFG1 0x70 -#define ARM_SMMU_GERROR_IRQ_CFG2 0x74 - -#define ARM_SMMU_STRTAB_BASE 0x80 -#define STRTAB_BASE_RA (1UL << 62) -#define STRTAB_BASE_ADDR_MASK GENMASK_ULL(51, 6) - -#define ARM_SMMU_STRTAB_BASE_CFG 0x88 -#define STRTAB_BASE_CFG_FMT GENMASK(17, 16) -#define STRTAB_BASE_CFG_FMT_LINEAR 0 -#define STRTAB_BASE_CFG_FMT_2LVL 1 -#define STRTAB_BASE_CFG_SPLIT GENMASK(10, 6) -#define STRTAB_BASE_CFG_LOG2SIZE GENMASK(5, 0) - -#define ARM_SMMU_CMDQ_BASE 0x90 -#define ARM_SMMU_CMDQ_PROD 0x98 -#define ARM_SMMU_CMDQ_CONS 0x9c - -#define ARM_SMMU_EVTQ_BASE 0xa0 -#define ARM_SMMU_EVTQ_PROD 0x100a8 -#define ARM_SMMU_EVTQ_CONS 0x100ac -#define ARM_SMMU_EVTQ_IRQ_CFG0 0xb0 -#define ARM_SMMU_EVTQ_IRQ_CFG1 0xb8 -#define ARM_SMMU_EVTQ_IRQ_CFG2 0xbc - -#define ARM_SMMU_PRIQ_BASE 0xc0 -#define ARM_SMMU_PRIQ_PROD 0x100c8 -#define ARM_SMMU_PRIQ_CONS 0x100cc -#define ARM_SMMU_PRIQ_IRQ_CFG0 0xd0 -#define ARM_SMMU_PRIQ_IRQ_CFG1 0xd8 -#define ARM_SMMU_PRIQ_IRQ_CFG2 0xdc - -#define ARM_SMMU_REG_SZ 0xe00 - -/* Common MSI config fields */ -#define MSI_CFG0_ADDR_MASK GENMASK_ULL(51, 2) -#define MSI_CFG2_SH GENMASK(5, 4) -#define MSI_CFG2_MEMATTR GENMASK(3, 0) - -/* Common memory attribute values */ -#define ARM_SMMU_SH_NSH 0 -#define ARM_SMMU_SH_OSH 2 -#define ARM_SMMU_SH_ISH 3 -#define ARM_SMMU_MEMATTR_DEVICE_nGnRE 0x1 -#define ARM_SMMU_MEMATTR_OIWB 0xf - -#define Q_IDX(llq, p) ((p) & ((1 << (llq)->max_n_shift) - 1)) -#define Q_WRP(llq, p) ((p) & (1 << (llq)->max_n_shift)) -#define Q_OVERFLOW_FLAG (1U << 31) -#define Q_OVF(p) ((p) & Q_OVERFLOW_FLAG) -#define Q_ENT(q, p) ((q)->base + \ - Q_IDX(&((q)->llq), p) * \ - (q)->ent_dwords) - -#define Q_BASE_RWA (1UL << 62) -#define Q_BASE_ADDR_MASK GENMASK_ULL(51, 5) -#define Q_BASE_LOG2SIZE GENMASK(4, 0) - -/* Ensure DMA allocations are naturally aligned */ -#ifdef CONFIG_CMA_ALIGNMENT -#define Q_MAX_SZ_SHIFT (PAGE_SHIFT + CONFIG_CMA_ALIGNMENT) -#else -#define Q_MAX_SZ_SHIFT (PAGE_SHIFT + MAX_ORDER - 1) -#endif - -/* - * Stream table. - * - * Linear: Enough to cover 1 << IDR1.SIDSIZE entries - * 2lvl: 128k L1 entries, - * 256 lazy entries per table (each table covers a PCI bus) - */ -#define STRTAB_L1_SZ_SHIFT 20 -#define STRTAB_SPLIT 8 - -#define STRTAB_L1_DESC_DWORDS 1 -#define STRTAB_L1_DESC_SPAN GENMASK_ULL(4, 0) -#define STRTAB_L1_DESC_L2PTR_MASK GENMASK_ULL(51, 6) - -#define STRTAB_STE_DWORDS 8 -#define STRTAB_STE_0_V (1UL << 0) -#define STRTAB_STE_0_CFG GENMASK_ULL(3, 1) -#define STRTAB_STE_0_CFG_ABORT 0 -#define STRTAB_STE_0_CFG_BYPASS 4 -#define STRTAB_STE_0_CFG_S1_TRANS 5 -#define STRTAB_STE_0_CFG_S2_TRANS 6 - -#define STRTAB_STE_0_S1FMT GENMASK_ULL(5, 4) -#define STRTAB_STE_0_S1FMT_LINEAR 0 -#define STRTAB_STE_0_S1FMT_64K_L2 2 -#define STRTAB_STE_0_S1CTXPTR_MASK GENMASK_ULL(51, 6) -#define STRTAB_STE_0_S1CDMAX GENMASK_ULL(63, 59) - -#define STRTAB_STE_1_S1DSS GENMASK_ULL(1, 0) -#define STRTAB_STE_1_S1DSS_TERMINATE 0x0 -#define STRTAB_STE_1_S1DSS_BYPASS 0x1 -#define STRTAB_STE_1_S1DSS_SSID0 0x2 - -#define STRTAB_STE_1_S1C_CACHE_NC 0UL -#define STRTAB_STE_1_S1C_CACHE_WBRA 1UL -#define STRTAB_STE_1_S1C_CACHE_WT 2UL -#define STRTAB_STE_1_S1C_CACHE_WB 3UL -#define STRTAB_STE_1_S1CIR GENMASK_ULL(3, 2) -#define STRTAB_STE_1_S1COR GENMASK_ULL(5, 4) -#define STRTAB_STE_1_S1CSH GENMASK_ULL(7, 6) - -#define STRTAB_STE_1_S1STALLD (1UL << 27) - -#define STRTAB_STE_1_EATS GENMASK_ULL(29, 28) -#define STRTAB_STE_1_EATS_ABT 0UL -#define STRTAB_STE_1_EATS_TRANS 1UL -#define STRTAB_STE_1_EATS_S1CHK 2UL - -#define STRTAB_STE_1_STRW GENMASK_ULL(31, 30) -#define STRTAB_STE_1_STRW_NSEL1 0UL -#define STRTAB_STE_1_STRW_EL2 2UL - -#define STRTAB_STE_1_SHCFG GENMASK_ULL(45, 44) -#define STRTAB_STE_1_SHCFG_INCOMING 1UL - -#define STRTAB_STE_2_S2VMID GENMASK_ULL(15, 0) -#define STRTAB_STE_2_VTCR GENMASK_ULL(50, 32) -#define STRTAB_STE_2_VTCR_S2T0SZ GENMASK_ULL(5, 0) -#define STRTAB_STE_2_VTCR_S2SL0 GENMASK_ULL(7, 6) -#define STRTAB_STE_2_VTCR_S2IR0 GENMASK_ULL(9, 8) -#define STRTAB_STE_2_VTCR_S2OR0 GENMASK_ULL(11, 10) -#define STRTAB_STE_2_VTCR_S2SH0 GENMASK_ULL(13, 12) -#define STRTAB_STE_2_VTCR_S2TG GENMASK_ULL(15, 14) -#define STRTAB_STE_2_VTCR_S2PS GENMASK_ULL(18, 16) -#define STRTAB_STE_2_S2AA64 (1UL << 51) -#define STRTAB_STE_2_S2ENDI (1UL << 52) -#define STRTAB_STE_2_S2PTW (1UL << 54) -#define STRTAB_STE_2_S2R (1UL << 58) - -#define STRTAB_STE_3_S2TTB_MASK GENMASK_ULL(51, 4) - -/* - * Context descriptors. - * - * Linear: when less than 1024 SSIDs are supported - * 2lvl: at most 1024 L1 entries, - * 1024 lazy entries per table. - */ -#define CTXDESC_SPLIT 10 -#define CTXDESC_L2_ENTRIES (1 << CTXDESC_SPLIT) - -#define CTXDESC_L1_DESC_DWORDS 1 -#define CTXDESC_L1_DESC_V (1UL << 0) -#define CTXDESC_L1_DESC_L2PTR_MASK GENMASK_ULL(51, 12) - -#define CTXDESC_CD_DWORDS 8 -#define CTXDESC_CD_0_TCR_T0SZ GENMASK_ULL(5, 0) -#define CTXDESC_CD_0_TCR_TG0 GENMASK_ULL(7, 6) -#define CTXDESC_CD_0_TCR_IRGN0 GENMASK_ULL(9, 8) -#define CTXDESC_CD_0_TCR_ORGN0 GENMASK_ULL(11, 10) -#define CTXDESC_CD_0_TCR_SH0 GENMASK_ULL(13, 12) -#define CTXDESC_CD_0_TCR_EPD0 (1ULL << 14) -#define CTXDESC_CD_0_TCR_EPD1 (1ULL << 30) - -#define CTXDESC_CD_0_ENDI (1UL << 15) -#define CTXDESC_CD_0_V (1UL << 31) - -#define CTXDESC_CD_0_TCR_IPS GENMASK_ULL(34, 32) -#define CTXDESC_CD_0_TCR_TBI0 (1ULL << 38) - -#define CTXDESC_CD_0_AA64 (1UL << 41) -#define CTXDESC_CD_0_S (1UL << 44) -#define CTXDESC_CD_0_R (1UL << 45) -#define CTXDESC_CD_0_A (1UL << 46) -#define CTXDESC_CD_0_ASET (1UL << 47) -#define CTXDESC_CD_0_ASID GENMASK_ULL(63, 48) - -#define CTXDESC_CD_1_TTB0_MASK GENMASK_ULL(51, 4) - -/* - * When the SMMU only supports linear context descriptor tables, pick a - * reasonable size limit (64kB). - */ -#define CTXDESC_LINEAR_CDMAX ilog2(SZ_64K / (CTXDESC_CD_DWORDS << 3)) - -/* Command queue */ -#define CMDQ_ENT_SZ_SHIFT 4 -#define CMDQ_ENT_DWORDS ((1 << CMDQ_ENT_SZ_SHIFT) >> 3) -#define CMDQ_MAX_SZ_SHIFT (Q_MAX_SZ_SHIFT - CMDQ_ENT_SZ_SHIFT) - -#define CMDQ_CONS_ERR GENMASK(30, 24) -#define CMDQ_ERR_CERROR_NONE_IDX 0 -#define CMDQ_ERR_CERROR_ILL_IDX 1 -#define CMDQ_ERR_CERROR_ABT_IDX 2 -#define CMDQ_ERR_CERROR_ATC_INV_IDX 3 - -#define CMDQ_0_OP GENMASK_ULL(7, 0) -#define CMDQ_0_SSV (1UL << 11) - -#define CMDQ_PREFETCH_0_SID GENMASK_ULL(63, 32) -#define CMDQ_PREFETCH_1_SIZE GENMASK_ULL(4, 0) -#define CMDQ_PREFETCH_1_ADDR_MASK GENMASK_ULL(63, 12) - -#define CMDQ_CFGI_0_SSID GENMASK_ULL(31, 12) -#define CMDQ_CFGI_0_SID GENMASK_ULL(63, 32) -#define CMDQ_CFGI_1_LEAF (1UL << 0) -#define CMDQ_CFGI_1_RANGE GENMASK_ULL(4, 0) - -#define CMDQ_TLBI_0_VMID GENMASK_ULL(47, 32) -#define CMDQ_TLBI_0_ASID GENMASK_ULL(63, 48) -#define CMDQ_TLBI_1_LEAF (1UL << 0) -#define CMDQ_TLBI_1_VA_MASK GENMASK_ULL(63, 12) -#define CMDQ_TLBI_1_IPA_MASK GENMASK_ULL(51, 12) - -#define CMDQ_ATC_0_SSID GENMASK_ULL(31, 12) -#define CMDQ_ATC_0_SID GENMASK_ULL(63, 32) -#define CMDQ_ATC_0_GLOBAL (1UL << 9) -#define CMDQ_ATC_1_SIZE GENMASK_ULL(5, 0) -#define CMDQ_ATC_1_ADDR_MASK GENMASK_ULL(63, 12) - -#define CMDQ_PRI_0_SSID GENMASK_ULL(31, 12) -#define CMDQ_PRI_0_SID GENMASK_ULL(63, 32) -#define CMDQ_PRI_1_GRPID GENMASK_ULL(8, 0) -#define CMDQ_PRI_1_RESP GENMASK_ULL(13, 12) - -#define CMDQ_SYNC_0_CS GENMASK_ULL(13, 12) -#define CMDQ_SYNC_0_CS_NONE 0 -#define CMDQ_SYNC_0_CS_IRQ 1 -#define CMDQ_SYNC_0_CS_SEV 2 -#define CMDQ_SYNC_0_MSH GENMASK_ULL(23, 22) -#define CMDQ_SYNC_0_MSIATTR GENMASK_ULL(27, 24) -#define CMDQ_SYNC_0_MSIDATA GENMASK_ULL(63, 32) -#define CMDQ_SYNC_1_MSIADDR_MASK GENMASK_ULL(51, 2) - -/* Event queue */ -#define EVTQ_ENT_SZ_SHIFT 5 -#define EVTQ_ENT_DWORDS ((1 << EVTQ_ENT_SZ_SHIFT) >> 3) -#define EVTQ_MAX_SZ_SHIFT (Q_MAX_SZ_SHIFT - EVTQ_ENT_SZ_SHIFT) - -#define EVTQ_0_ID GENMASK_ULL(7, 0) - -/* PRI queue */ -#define PRIQ_ENT_SZ_SHIFT 4 -#define PRIQ_ENT_DWORDS ((1 << PRIQ_ENT_SZ_SHIFT) >> 3) -#define PRIQ_MAX_SZ_SHIFT (Q_MAX_SZ_SHIFT - PRIQ_ENT_SZ_SHIFT) - -#define PRIQ_0_SID GENMASK_ULL(31, 0) -#define PRIQ_0_SSID GENMASK_ULL(51, 32) -#define PRIQ_0_PERM_PRIV (1UL << 58) -#define PRIQ_0_PERM_EXEC (1UL << 59) -#define PRIQ_0_PERM_READ (1UL << 60) -#define PRIQ_0_PERM_WRITE (1UL << 61) -#define PRIQ_0_PRG_LAST (1UL << 62) -#define PRIQ_0_SSID_V (1UL << 63) - -#define PRIQ_1_PRG_IDX GENMASK_ULL(8, 0) -#define PRIQ_1_ADDR_MASK GENMASK_ULL(63, 12) - -/* High-level queue structures */ -#define ARM_SMMU_POLL_TIMEOUT_US 100 -#define ARM_SMMU_CMDQ_SYNC_TIMEOUT_US 1000000 /* 1s! */ -#define ARM_SMMU_CMDQ_SYNC_SPIN_COUNT 10 - static bool disable_bypass = 1; -enum pri_resp { - PRI_RESP_DENY = 0, - PRI_RESP_FAIL = 1, - PRI_RESP_SUCC = 2, -}; - -#ifdef CONFIG_MSI -enum arm_smmu_msi_index { - EVTQ_MSI_INDEX, - GERROR_MSI_INDEX, - PRIQ_MSI_INDEX, - ARM_SMMU_MAX_MSIS, -}; - -static phys_addr_t arm_smmu_msi_cfg[ARM_SMMU_MAX_MSIS][3] = { - [EVTQ_MSI_INDEX] = { - ARM_SMMU_EVTQ_IRQ_CFG0, - ARM_SMMU_EVTQ_IRQ_CFG1, - ARM_SMMU_EVTQ_IRQ_CFG2, - }, - [GERROR_MSI_INDEX] = { - ARM_SMMU_GERROR_IRQ_CFG0, - ARM_SMMU_GERROR_IRQ_CFG1, - ARM_SMMU_GERROR_IRQ_CFG2, - }, - [PRIQ_MSI_INDEX] = { - ARM_SMMU_PRIQ_IRQ_CFG0, - ARM_SMMU_PRIQ_IRQ_CFG1, - ARM_SMMU_PRIQ_IRQ_CFG2, - }, -}; -#endif /* CONFIG_MSI */ - -struct arm_smmu_cmdq_ent { - /* Common fields */ - u8 opcode; - bool substream_valid; - - /* Command-specific fields */ - union { - #define CMDQ_OP_PREFETCH_CFG 0x1 - struct { - u32 sid; - u8 size; - u64 addr; - } prefetch; - - #define CMDQ_OP_CFGI_STE 0x3 - #define CMDQ_OP_CFGI_ALL 0x4 - struct { - u32 sid; - union { - bool leaf; - u8 span; - }; - } cfgi; - - #define CMDQ_OP_TLBI_EL2_ALL 0x20 - #define CMDQ_OP_TLBI_S12_VMALL 0x28 - #define CMDQ_OP_TLBI_S2_IPA 0x2a - #define CMDQ_OP_TLBI_NSNH_ALL 0x30 - struct { - u16 asid; - u16 vmid; - bool leaf; - u64 addr; - } tlbi; - - #define CMDQ_OP_ATC_INV 0x40 - #define ATC_INV_SIZE_ALL 52 - struct { - u32 sid; - u32 ssid; - u64 addr; - u8 size; - bool global; - } atc; - - #define CMDQ_OP_PRI_RESP 0x41 - struct { - u32 sid; - u32 ssid; - u16 grpid; - enum pri_resp resp; - } pri; - - #define CMDQ_OP_CMD_SYNC 0x46 - struct { - u32 msidata; - u64 msiaddr; - } sync; - }; -}; - -struct arm_smmu_ll_queue { - u32 prod; - u32 cons; - u32 max_n_shift; -}; - -struct arm_smmu_queue { - struct arm_smmu_ll_queue llq; - int irq; /* Wired interrupt */ - - __le64 *base; - dma_addr_t base_dma; - u64 q_base; - - size_t ent_dwords; - - u32 __iomem *prod_reg; - u32 __iomem *cons_reg; -}; - -struct arm_smmu_cmdq { - struct arm_smmu_queue q; - spinlock_t lock; -}; - -struct arm_smmu_evtq { - struct arm_smmu_queue q; - u32 max_stalls; -}; - -struct arm_smmu_priq { - struct arm_smmu_queue q; -}; - -/* High-level stream table and context descriptor structures */ -struct arm_smmu_strtab_l1_desc { - u8 span; - - __le64 *l2ptr; - dma_addr_t l2ptr_dma; -}; - -struct arm_smmu_s2_cfg { - u16 vmid; - u64 vttbr; - u64 vtcr; -}; - -struct arm_smmu_strtab_cfg { - __le64 *strtab; - dma_addr_t strtab_dma; - struct arm_smmu_strtab_l1_desc *l1_desc; - unsigned int num_l1_ents; - - u64 strtab_base; - u32 strtab_base_cfg; -}; - -struct arm_lpae_s2_cfg { - u64 vttbr; - struct { - u32 ps:3; - u32 tg:2; - u32 sh:2; - u32 orgn:2; - u32 irgn:2; - u32 sl:2; - u32 tsz:6; - } vtcr; -}; - -/* An SMMUv3 instance */ -struct arm_smmu_device { - struct device *dev; - void __iomem *base; - void __iomem *page1; - -#define ARM_SMMU_FEAT_2_LVL_STRTAB (1 << 0) -#define ARM_SMMU_FEAT_2_LVL_CDTAB (1 << 1) -#define ARM_SMMU_FEAT_TT_LE (1 << 2) -#define ARM_SMMU_FEAT_TT_BE (1 << 3) -#define ARM_SMMU_FEAT_PRI (1 << 4) -#define ARM_SMMU_FEAT_ATS (1 << 5) -#define ARM_SMMU_FEAT_SEV (1 << 6) -#define ARM_SMMU_FEAT_MSI (1 << 7) -#define ARM_SMMU_FEAT_COHERENCY (1 << 8) -#define ARM_SMMU_FEAT_TRANS_S1 (1 << 9) -#define ARM_SMMU_FEAT_TRANS_S2 (1 << 10) -#define ARM_SMMU_FEAT_STALLS (1 << 11) -#define ARM_SMMU_FEAT_HYP (1 << 12) -#define ARM_SMMU_FEAT_STALL_FORCE (1 << 13) -#define ARM_SMMU_FEAT_VAX (1 << 14) - u32 features; - -#define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) -#define ARM_SMMU_OPT_PAGE0_REGS_ONLY (1 << 1) - u32 options; - - struct arm_smmu_cmdq cmdq; - struct arm_smmu_evtq evtq; - struct arm_smmu_priq priq; - - int gerr_irq; - int combined_irq; - u32 sync_nr; - u8 prev_cmd_opcode; - - unsigned long ias; /* IPA */ - unsigned long oas; /* PA */ - unsigned long pgsize_bitmap; - -#define ARM_SMMU_MAX_VMIDS (1 << 16) - unsigned int vmid_bits; - DECLARE_BITMAP(vmid_map, ARM_SMMU_MAX_VMIDS); - - unsigned int sid_bits; - - struct arm_smmu_strtab_cfg strtab_cfg; - - /* Hi16xx adds an extra 32 bits of goodness to its MSI payload */ - union { - u32 sync_count; - u64 padding; - }; - - /* Need to keep a list of SMMU devices */ - struct list_head devices; - - /* Tasklets for handling evts/faults and pci page request IRQs*/ - struct tasklet evtq_irq_tasklet; - struct tasklet priq_irq_tasklet; - struct tasklet combined_irq_tasklet; -}; - -/* SMMU private data for each master */ -struct arm_smmu_master { - struct arm_smmu_device *smmu; - struct device *dev; - struct arm_smmu_domain *domain; - struct list_head domain_head; - u32 *sids; - unsigned int num_sids; - bool ats_enabled; -}; - -/* SMMU private data for an IOMMU domain */ -enum arm_smmu_domain_stage { - ARM_SMMU_DOMAIN_S1 = 0, - ARM_SMMU_DOMAIN_S2, - ARM_SMMU_DOMAIN_NESTED, - ARM_SMMU_DOMAIN_BYPASS, -}; - -struct arm_smmu_domain { - struct arm_smmu_device *smmu; - struct mutex init_mutex; /* Protects smmu pointer */ - - bool non_strict; - atomic_t nr_ats_masters; - - enum arm_smmu_domain_stage stage; - struct arm_smmu_s2_cfg s2_cfg; - - /* Xen domain associated with this SMMU domain */ - struct domain *d; - - struct iommu_domain domain; - - struct list_head devices; - spinlock_t devices_lock; -}; - struct arm_smmu_option_prop { u32 opt; const char *prop; diff --git a/xen/drivers/passthrough/arm/smmu-v3.h b/xen/drivers/passthrough/arm/smmu-v3.h new file mode 100644 index 0000000000..c45d2f16c4 --- /dev/null +++ b/xen/drivers/passthrough/arm/smmu-v3.h @@ -0,0 +1,674 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * IOMMU API for ARM architected SMMUv3 implementations. + * + * Copyright (C) 2022 ARM Limited + */ + +#ifndef _ARM_SMMU_V3_H +#define _ARM_SMMU_V3_H + +/* MMIO registers */ +#define ARM_SMMU_IDR0 0x0 +#define IDR0_ST_LVL GENMASK(28, 27) +#define IDR0_ST_LVL_2LVL 1 +#define IDR0_STALL_MODEL GENMASK(25, 24) +#define IDR0_STALL_MODEL_STALL 0 +#define IDR0_STALL_MODEL_FORCE 2 +#define IDR0_TTENDIAN GENMASK(22, 21) +#define IDR0_TTENDIAN_MIXED 0 +#define IDR0_TTENDIAN_LE 2 +#define IDR0_TTENDIAN_BE 3 +#define IDR0_CD2L (1 << 19) +#define IDR0_VMID16 (1 << 18) +#define IDR0_PRI (1 << 16) +#define IDR0_SEV (1 << 14) +#define IDR0_MSI (1 << 13) +#define IDR0_ASID16 (1 << 12) +#define IDR0_ATS (1 << 10) +#define IDR0_HYP (1 << 9) +#define IDR0_COHACC (1 << 4) +#define IDR0_TTF GENMASK(3, 2) +#define IDR0_TTF_AARCH64 2 +#define IDR0_TTF_AARCH32_64 3 +#define IDR0_S1P (1 << 1) +#define IDR0_S2P (1 << 0) + +#define ARM_SMMU_IDR1 0x4 +#define IDR1_TABLES_PRESET (1 << 30) +#define IDR1_QUEUES_PRESET (1 << 29) +#define IDR1_REL (1 << 28) +#define IDR1_CMDQS GENMASK(25, 21) +#define IDR1_EVTQS GENMASK(20, 16) +#define IDR1_PRIQS GENMASK(15, 11) +#define IDR1_SSIDSIZE GENMASK(10, 6) +#define IDR1_SIDSIZE GENMASK(5, 0) + +#define ARM_SMMU_IDR5 0x14 +#define IDR5_STALL_MAX GENMASK(31, 16) +#define IDR5_GRAN64K (1 << 6) +#define IDR5_GRAN16K (1 << 5) +#define IDR5_GRAN4K (1 << 4) +#define IDR5_OAS GENMASK(2, 0) +#define IDR5_OAS_32_BIT 0 +#define IDR5_OAS_36_BIT 1 +#define IDR5_OAS_40_BIT 2 +#define IDR5_OAS_42_BIT 3 +#define IDR5_OAS_44_BIT 4 +#define IDR5_OAS_48_BIT 5 +#define IDR5_OAS_52_BIT 6 +#define IDR5_VAX GENMASK(11, 10) +#define IDR5_VAX_52_BIT 1 + +#define ARM_SMMU_CR0 0x20 +#define CR0_ATSCHK (1 << 4) +#define CR0_CMDQEN (1 << 3) +#define CR0_EVTQEN (1 << 2) +#define CR0_PRIQEN (1 << 1) +#define CR0_SMMUEN (1 << 0) + +#define ARM_SMMU_CR0ACK 0x24 + +#define ARM_SMMU_CR1 0x28 +#define CR1_TABLE_SH GENMASK(11, 10) +#define CR1_TABLE_OC GENMASK(9, 8) +#define CR1_TABLE_IC GENMASK(7, 6) +#define CR1_QUEUE_SH GENMASK(5, 4) +#define CR1_QUEUE_OC GENMASK(3, 2) +#define CR1_QUEUE_IC GENMASK(1, 0) +/* CR1 cacheability fields don't quite follow the usual TCR-style encoding */ +#define CR1_CACHE_NC 0 +#define CR1_CACHE_WB 1 +#define CR1_CACHE_WT 2 + +#define ARM_SMMU_CR2 0x2c +#define CR2_PTM (1 << 2) +#define CR2_RECINVSID (1 << 1) +#define CR2_E2H (1 << 0) + +#define ARM_SMMU_GBPA 0x44 +#define GBPA_UPDATE (1 << 31) +#define GBPA_ABORT (1 << 20) + +#define ARM_SMMU_IRQ_CTRL 0x50 +#define IRQ_CTRL_EVTQ_IRQEN (1 << 2) +#define IRQ_CTRL_PRIQ_IRQEN (1 << 1) +#define IRQ_CTRL_GERROR_IRQEN (1 << 0) + +#define ARM_SMMU_IRQ_CTRLACK 0x54 + +#define ARM_SMMU_GERROR 0x60 +#define GERROR_SFM_ERR (1 << 8) +#define GERROR_MSI_GERROR_ABT_ERR (1 << 7) +#define GERROR_MSI_PRIQ_ABT_ERR (1 << 6) +#define GERROR_MSI_EVTQ_ABT_ERR (1 << 5) +#define GERROR_MSI_CMDQ_ABT_ERR (1 << 4) +#define GERROR_PRIQ_ABT_ERR (1 << 3) +#define GERROR_EVTQ_ABT_ERR (1 << 2) +#define GERROR_CMDQ_ERR (1 << 0) +#define GERROR_ERR_MASK 0xfd + +#define ARM_SMMU_GERRORN 0x64 + +#define ARM_SMMU_GERROR_IRQ_CFG0 0x68 +#define ARM_SMMU_GERROR_IRQ_CFG1 0x70 +#define ARM_SMMU_GERROR_IRQ_CFG2 0x74 + +#define ARM_SMMU_STRTAB_BASE 0x80 +#define STRTAB_BASE_RA (1UL << 62) +#define STRTAB_BASE_ADDR_MASK GENMASK_ULL(51, 6) + +#define ARM_SMMU_STRTAB_BASE_CFG 0x88 +#define STRTAB_BASE_CFG_FMT GENMASK(17, 16) +#define STRTAB_BASE_CFG_FMT_LINEAR 0 +#define STRTAB_BASE_CFG_FMT_2LVL 1 +#define STRTAB_BASE_CFG_SPLIT GENMASK(10, 6) +#define STRTAB_BASE_CFG_LOG2SIZE GENMASK(5, 0) + +#define ARM_SMMU_CMDQ_BASE 0x90 +#define ARM_SMMU_CMDQ_PROD 0x98 +#define ARM_SMMU_CMDQ_CONS 0x9c + +#define ARM_SMMU_EVTQ_BASE 0xa0 +#define ARM_SMMU_EVTQ_PROD 0x100a8 +#define ARM_SMMU_EVTQ_CONS 0x100ac +#define ARM_SMMU_EVTQ_IRQ_CFG0 0xb0 +#define ARM_SMMU_EVTQ_IRQ_CFG1 0xb8 +#define ARM_SMMU_EVTQ_IRQ_CFG2 0xbc + +#define ARM_SMMU_PRIQ_BASE 0xc0 +#define ARM_SMMU_PRIQ_PROD 0x100c8 +#define ARM_SMMU_PRIQ_CONS 0x100cc +#define ARM_SMMU_PRIQ_IRQ_CFG0 0xd0 +#define ARM_SMMU_PRIQ_IRQ_CFG1 0xd8 +#define ARM_SMMU_PRIQ_IRQ_CFG2 0xdc + +#define ARM_SMMU_REG_SZ 0xe00 + +/* Common MSI config fields */ +#define MSI_CFG0_ADDR_MASK GENMASK_ULL(51, 2) +#define MSI_CFG2_SH GENMASK(5, 4) +#define MSI_CFG2_MEMATTR GENMASK(3, 0) + +/* Common memory attribute values */ +#define ARM_SMMU_SH_NSH 0 +#define ARM_SMMU_SH_OSH 2 +#define ARM_SMMU_SH_ISH 3 +#define ARM_SMMU_MEMATTR_DEVICE_nGnRE 0x1 +#define ARM_SMMU_MEMATTR_OIWB 0xf + +#define Q_IDX(llq, p) ((p) & ((1 << (llq)->max_n_shift) - 1)) +#define Q_WRP(llq, p) ((p) & (1 << (llq)->max_n_shift)) +#define Q_OVERFLOW_FLAG (1 << 31) +#define Q_OVF(p) ((p) & Q_OVERFLOW_FLAG) +#define Q_ENT(q, p) ((q)->base + \ + Q_IDX(&((q)->llq), p) * \ + (q)->ent_dwords) + +#define Q_BASE_RWA (1UL << 62) +#define Q_BASE_ADDR_MASK GENMASK_ULL(51, 5) +#define Q_BASE_LOG2SIZE GENMASK(4, 0) + +/* Ensure DMA allocations are naturally aligned */ +#ifdef CONFIG_CMA_ALIGNMENT +#define Q_MAX_SZ_SHIFT (PAGE_SHIFT + CONFIG_CMA_ALIGNMENT) +#else +#define Q_MAX_SZ_SHIFT (PAGE_SHIFT + MAX_ORDER - 1) +#endif + +/* + * Stream table. + * + * Linear: Enough to cover 1 << IDR1.SIDSIZE entries + * 2lvl: 128k L1 entries, + * 256 lazy entries per table (each table covers a PCI bus) + */ +#define STRTAB_L1_SZ_SHIFT 20 +#define STRTAB_SPLIT 8 + +#define STRTAB_L1_DESC_DWORDS 1 +#define STRTAB_L1_DESC_SPAN GENMASK_ULL(4, 0) +#define STRTAB_L1_DESC_L2PTR_MASK GENMASK_ULL(51, 6) + +#define STRTAB_STE_DWORDS 8 +#define STRTAB_STE_0_V (1UL << 0) +#define STRTAB_STE_0_CFG GENMASK_ULL(3, 1) +#define STRTAB_STE_0_CFG_ABORT 0 +#define STRTAB_STE_0_CFG_BYPASS 4 +#define STRTAB_STE_0_CFG_S1_TRANS 5 +#define STRTAB_STE_0_CFG_S2_TRANS 6 + +#define STRTAB_STE_0_S1FMT GENMASK_ULL(5, 4) +#define STRTAB_STE_0_S1FMT_LINEAR 0 +#define STRTAB_STE_0_S1FMT_64K_L2 2 +#define STRTAB_STE_0_S1CTXPTR_MASK GENMASK_ULL(51, 6) +#define STRTAB_STE_0_S1CDMAX GENMASK_ULL(63, 59) + +#define STRTAB_STE_1_S1DSS GENMASK_ULL(1, 0) +#define STRTAB_STE_1_S1DSS_TERMINATE 0x0 +#define STRTAB_STE_1_S1DSS_BYPASS 0x1 +#define STRTAB_STE_1_S1DSS_SSID0 0x2 + +#define STRTAB_STE_1_S1C_CACHE_NC 0UL +#define STRTAB_STE_1_S1C_CACHE_WBRA 1UL +#define STRTAB_STE_1_S1C_CACHE_WT 2UL +#define STRTAB_STE_1_S1C_CACHE_WB 3UL +#define STRTAB_STE_1_S1CIR GENMASK_ULL(3, 2) +#define STRTAB_STE_1_S1COR GENMASK_ULL(5, 4) +#define STRTAB_STE_1_S1CSH GENMASK_ULL(7, 6) + +#define STRTAB_STE_1_S1STALLD (1UL << 27) + +#define STRTAB_STE_1_EATS GENMASK_ULL(29, 28) +#define STRTAB_STE_1_EATS_ABT 0UL +#define STRTAB_STE_1_EATS_TRANS 1UL +#define STRTAB_STE_1_EATS_S1CHK 2UL + +#define STRTAB_STE_1_STRW GENMASK_ULL(31, 30) +#define STRTAB_STE_1_STRW_NSEL1 0UL +#define STRTAB_STE_1_STRW_EL2 2UL + +#define STRTAB_STE_1_SHCFG GENMASK_ULL(45, 44) +#define STRTAB_STE_1_SHCFG_INCOMING 1UL + +#define STRTAB_STE_2_S2VMID GENMASK_ULL(15, 0) +#define STRTAB_STE_2_VTCR GENMASK_ULL(50, 32) +#define STRTAB_STE_2_VTCR_S2T0SZ GENMASK_ULL(5, 0) +#define STRTAB_STE_2_VTCR_S2SL0 GENMASK_ULL(7, 6) +#define STRTAB_STE_2_VTCR_S2IR0 GENMASK_ULL(9, 8) +#define STRTAB_STE_2_VTCR_S2OR0 GENMASK_ULL(11, 10) +#define STRTAB_STE_2_VTCR_S2SH0 GENMASK_ULL(13, 12) +#define STRTAB_STE_2_VTCR_S2TG GENMASK_ULL(15, 14) +#define STRTAB_STE_2_VTCR_S2PS GENMASK_ULL(18, 16) +#define STRTAB_STE_2_S2AA64 (1UL << 51) +#define STRTAB_STE_2_S2ENDI (1UL << 52) +#define STRTAB_STE_2_S2PTW (1UL << 54) +#define STRTAB_STE_2_S2R (1UL << 58) + +#define STRTAB_STE_3_S2TTB_MASK GENMASK_ULL(51, 4) + +/* + * Context descriptors. + * + * Linear: when less than 1024 SSIDs are supported + * 2lvl: at most 1024 L1 entries, + * 1024 lazy entries per table. + */ +#define CTXDESC_SPLIT 10 +#define CTXDESC_L2_ENTRIES (1 << CTXDESC_SPLIT) + +#define CTXDESC_L1_DESC_DWORDS 1 +#define CTXDESC_L1_DESC_V (1UL << 0) +#define CTXDESC_L1_DESC_L2PTR_MASK GENMASK_ULL(51, 12) + +#define CTXDESC_CD_DWORDS 8 +#define CTXDESC_CD_0_TCR_T0SZ GENMASK_ULL(5, 0) +#define CTXDESC_CD_0_TCR_TG0 GENMASK_ULL(7, 6) +#define CTXDESC_CD_0_TCR_IRGN0 GENMASK_ULL(9, 8) +#define CTXDESC_CD_0_TCR_ORGN0 GENMASK_ULL(11, 10) +#define CTXDESC_CD_0_TCR_SH0 GENMASK_ULL(13, 12) +#define CTXDESC_CD_0_TCR_EPD0 (1ULL << 14) +#define CTXDESC_CD_0_TCR_EPD1 (1ULL << 30) + +#define CTXDESC_CD_0_ENDI (1UL << 15) +#define CTXDESC_CD_0_V (1UL << 31) + +#define CTXDESC_CD_0_TCR_IPS GENMASK_ULL(34, 32) +#define CTXDESC_CD_0_TCR_TBI0 (1ULL << 38) + +#define CTXDESC_CD_0_AA64 (1UL << 41) +#define CTXDESC_CD_0_S (1UL << 44) +#define CTXDESC_CD_0_R (1UL << 45) +#define CTXDESC_CD_0_A (1UL << 46) +#define CTXDESC_CD_0_ASET (1UL << 47) +#define CTXDESC_CD_0_ASID GENMASK_ULL(63, 48) + +#define CTXDESC_CD_1_TTB0_MASK GENMASK_ULL(51, 4) + +/* + * When the SMMU only supports linear context descriptor tables, pick a + * reasonable size limit (64kB). + */ +#define CTXDESC_LINEAR_CDMAX ilog2(SZ_64K / (CTXDESC_CD_DWORDS << 3)) + +/* Command queue */ +#define CMDQ_ENT_SZ_SHIFT 4 +#define CMDQ_ENT_DWORDS ((1 << CMDQ_ENT_SZ_SHIFT) >> 3) +#define CMDQ_MAX_SZ_SHIFT (Q_MAX_SZ_SHIFT - CMDQ_ENT_SZ_SHIFT) + +#define CMDQ_CONS_ERR GENMASK(30, 24) +#define CMDQ_ERR_CERROR_NONE_IDX 0 +#define CMDQ_ERR_CERROR_ILL_IDX 1 +#define CMDQ_ERR_CERROR_ABT_IDX 2 +#define CMDQ_ERR_CERROR_ATC_INV_IDX 3 + +#define CMDQ_0_OP GENMASK_ULL(7, 0) +#define CMDQ_0_SSV (1UL << 11) + +#define CMDQ_PREFETCH_0_SID GENMASK_ULL(63, 32) +#define CMDQ_PREFETCH_1_SIZE GENMASK_ULL(4, 0) +#define CMDQ_PREFETCH_1_ADDR_MASK GENMASK_ULL(63, 12) + +#define CMDQ_CFGI_0_SSID GENMASK_ULL(31, 12) +#define CMDQ_CFGI_0_SID GENMASK_ULL(63, 32) +#define CMDQ_CFGI_1_LEAF (1UL << 0) +#define CMDQ_CFGI_1_RANGE GENMASK_ULL(4, 0) + +#define CMDQ_TLBI_0_VMID GENMASK_ULL(47, 32) +#define CMDQ_TLBI_0_ASID GENMASK_ULL(63, 48) +#define CMDQ_TLBI_1_LEAF (1UL << 0) +#define CMDQ_TLBI_1_VA_MASK GENMASK_ULL(63, 12) +#define CMDQ_TLBI_1_IPA_MASK GENMASK_ULL(51, 12) + +#define CMDQ_ATC_0_SSID GENMASK_ULL(31, 12) +#define CMDQ_ATC_0_SID GENMASK_ULL(63, 32) +#define CMDQ_ATC_0_GLOBAL (1UL << 9) +#define CMDQ_ATC_1_SIZE GENMASK_ULL(5, 0) +#define CMDQ_ATC_1_ADDR_MASK GENMASK_ULL(63, 12) + +#define CMDQ_PRI_0_SSID GENMASK_ULL(31, 12) +#define CMDQ_PRI_0_SID GENMASK_ULL(63, 32) +#define CMDQ_PRI_1_GRPID GENMASK_ULL(8, 0) +#define CMDQ_PRI_1_RESP GENMASK_ULL(13, 12) + +#define CMDQ_SYNC_0_CS GENMASK_ULL(13, 12) +#define CMDQ_SYNC_0_CS_NONE 0 +#define CMDQ_SYNC_0_CS_IRQ 1 +#define CMDQ_SYNC_0_CS_SEV 2 +#define CMDQ_SYNC_0_MSH GENMASK_ULL(23, 22) +#define CMDQ_SYNC_0_MSIATTR GENMASK_ULL(27, 24) +#define CMDQ_SYNC_0_MSIDATA GENMASK_ULL(63, 32) +#define CMDQ_SYNC_1_MSIADDR_MASK GENMASK_ULL(51, 2) + +/* Event queue */ +#define EVTQ_ENT_SZ_SHIFT 5 +#define EVTQ_ENT_DWORDS ((1 << EVTQ_ENT_SZ_SHIFT) >> 3) +#define EVTQ_MAX_SZ_SHIFT (Q_MAX_SZ_SHIFT - EVTQ_ENT_SZ_SHIFT) + +#define EVTQ_0_ID GENMASK_ULL(7, 0) + +/* PRI queue */ +#define PRIQ_ENT_SZ_SHIFT 4 +#define PRIQ_ENT_DWORDS ((1 << PRIQ_ENT_SZ_SHIFT) >> 3) +#define PRIQ_MAX_SZ_SHIFT (Q_MAX_SZ_SHIFT - PRIQ_ENT_SZ_SHIFT) + +#define PRIQ_0_SID GENMASK_ULL(31, 0) +#define PRIQ_0_SSID GENMASK_ULL(51, 32) +#define PRIQ_0_PERM_PRIV (1UL << 58) +#define PRIQ_0_PERM_EXEC (1UL << 59) +#define PRIQ_0_PERM_READ (1UL << 60) +#define PRIQ_0_PERM_WRITE (1UL << 61) +#define PRIQ_0_PRG_LAST (1UL << 62) +#define PRIQ_0_SSID_V (1UL << 63) + +#define PRIQ_1_PRG_IDX GENMASK_ULL(8, 0) +#define PRIQ_1_ADDR_MASK GENMASK_ULL(63, 12) + +/* High-level queue structures */ +#define ARM_SMMU_POLL_TIMEOUT_US 100 +#define ARM_SMMU_CMDQ_SYNC_TIMEOUT_US 1000000 /* 1s! */ +#define ARM_SMMU_CMDQ_SYNC_SPIN_COUNT 10 + +#define FIELD_PREP(_mask, _val) \ + (((typeof(_mask))(_val) << (ffs64(_mask) - 1)) & (_mask)) + +#define FIELD_GET(_mask, _reg) \ + ((typeof(_mask))(((_reg) & (_mask)) >> (ffs64(_mask) - 1))) + +/* Linux compatibility functions. */ +typedef paddr_t dma_addr_t; +typedef paddr_t phys_addr_t; +typedef unsigned int gfp_t; + +/* Alias to Xen lock functions */ +#define mutex spinlock +#define mutex_init spin_lock_init +#define mutex_lock spin_lock +#define mutex_unlock spin_unlock + +/* SMMU private data for an IOMMU domain */ +enum arm_smmu_domain_stage { + ARM_SMMU_DOMAIN_S1 = 0, + ARM_SMMU_DOMAIN_S2, + ARM_SMMU_DOMAIN_NESTED, + ARM_SMMU_DOMAIN_BYPASS, +}; + +/* Xen specific code. */ +struct iommu_domain { + /* Runtime SMMU configuration for this iommu_domain */ + atomic_t ref; + /* + * Used to link iommu_domain contexts for a same domain. + * There is at least one per-SMMU to used by the domain. + */ + struct list_head list; +}; + +/* Describes information required for a Xen domain */ +struct arm_smmu_xen_domain { + spinlock_t lock; + + /* List of iommu domains associated to this domain */ + struct list_head contexts; +}; + +enum pri_resp { + PRI_RESP_DENY = 0, + PRI_RESP_FAIL = 1, + PRI_RESP_SUCC = 2, +}; + +#ifdef CONFIG_MSI +enum arm_smmu_msi_index { + EVTQ_MSI_INDEX, + GERROR_MSI_INDEX, + PRIQ_MSI_INDEX, + ARM_SMMU_MAX_MSIS, +}; + +static phys_addr_t arm_smmu_msi_cfg[ARM_SMMU_MAX_MSIS][3] = { + [EVTQ_MSI_INDEX] = { + ARM_SMMU_EVTQ_IRQ_CFG0, + ARM_SMMU_EVTQ_IRQ_CFG1, + ARM_SMMU_EVTQ_IRQ_CFG2, + }, + [GERROR_MSI_INDEX] = { + ARM_SMMU_GERROR_IRQ_CFG0, + ARM_SMMU_GERROR_IRQ_CFG1, + ARM_SMMU_GERROR_IRQ_CFG2, + }, + [PRIQ_MSI_INDEX] = { + ARM_SMMU_PRIQ_IRQ_CFG0, + ARM_SMMU_PRIQ_IRQ_CFG1, + ARM_SMMU_PRIQ_IRQ_CFG2, + }, +}; +#endif /* CONFIG_MSI */ + +struct arm_smmu_cmdq_ent { + /* Common fields */ + u8 opcode; + bool substream_valid; + + /* Command-specific fields */ + union { + #define CMDQ_OP_PREFETCH_CFG 0x1 + struct { + u32 sid; + u8 size; + u64 addr; + } prefetch; + + #define CMDQ_OP_CFGI_STE 0x3 + #define CMDQ_OP_CFGI_ALL 0x4 + struct { + u32 sid; + union { + bool leaf; + u8 span; + }; + } cfgi; + + #define CMDQ_OP_TLBI_EL2_ALL 0x20 + #define CMDQ_OP_TLBI_S12_VMALL 0x28 + #define CMDQ_OP_TLBI_S2_IPA 0x2a + #define CMDQ_OP_TLBI_NSNH_ALL 0x30 + struct { + u16 asid; + u16 vmid; + bool leaf; + u64 addr; + } tlbi; + + #define CMDQ_OP_ATC_INV 0x40 + #define ATC_INV_SIZE_ALL 52 + struct { + u32 sid; + u32 ssid; + u64 addr; + u8 size; + bool global; + } atc; + + #define CMDQ_OP_PRI_RESP 0x41 + struct { + u32 sid; + u32 ssid; + u16 grpid; + enum pri_resp resp; + } pri; + + #define CMDQ_OP_CMD_SYNC 0x46 + struct { + u32 msidata; + u64 msiaddr; + } sync; + }; +}; + +struct arm_smmu_ll_queue { + u32 prod; + u32 cons; + u32 max_n_shift; +}; + +struct arm_smmu_queue { + struct arm_smmu_ll_queue llq; + int irq; /* Wired interrupt */ + + __le64 *base; + dma_addr_t base_dma; + u64 q_base; + + size_t ent_dwords; + + u32 __iomem *prod_reg; + u32 __iomem *cons_reg; +}; + +struct arm_smmu_cmdq { + struct arm_smmu_queue q; + spinlock_t lock; +}; + +struct arm_smmu_evtq { + struct arm_smmu_queue q; + u32 max_stalls; +}; + +struct arm_smmu_priq { + struct arm_smmu_queue q; +}; + +/* High-level stream table and context descriptor structures */ +struct arm_smmu_strtab_l1_desc { + u8 span; + + __le64 *l2ptr; + dma_addr_t l2ptr_dma; +}; + +struct arm_smmu_s2_cfg { + u16 vmid; + u64 vttbr; + u64 vtcr; +}; + +struct arm_smmu_strtab_cfg { + __le64 *strtab; + dma_addr_t strtab_dma; + struct arm_smmu_strtab_l1_desc *l1_desc; + unsigned int num_l1_ents; + + u64 strtab_base; + u32 strtab_base_cfg; +}; + +struct arm_lpae_s2_cfg { + u64 vttbr; + struct { + u32 ps:3; + u32 tg:2; + u32 sh:2; + u32 orgn:2; + u32 irgn:2; + u32 sl:2; + u32 tsz:6; + } vtcr; +}; + +/* An SMMUv3 instance */ +struct arm_smmu_device { + struct device *dev; + void __iomem *base; + void __iomem *page1; + +#define ARM_SMMU_FEAT_2_LVL_STRTAB (1 << 0) +#define ARM_SMMU_FEAT_2_LVL_CDTAB (1 << 1) +#define ARM_SMMU_FEAT_TT_LE (1 << 2) +#define ARM_SMMU_FEAT_TT_BE (1 << 3) +#define ARM_SMMU_FEAT_PRI (1 << 4) +#define ARM_SMMU_FEAT_ATS (1 << 5) +#define ARM_SMMU_FEAT_SEV (1 << 6) +#define ARM_SMMU_FEAT_MSI (1 << 7) +#define ARM_SMMU_FEAT_COHERENCY (1 << 8) +#define ARM_SMMU_FEAT_TRANS_S1 (1 << 9) +#define ARM_SMMU_FEAT_TRANS_S2 (1 << 10) +#define ARM_SMMU_FEAT_STALLS (1 << 11) +#define ARM_SMMU_FEAT_HYP (1 << 12) +#define ARM_SMMU_FEAT_STALL_FORCE (1 << 13) +#define ARM_SMMU_FEAT_VAX (1 << 14) + u32 features; + +#define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) +#define ARM_SMMU_OPT_PAGE0_REGS_ONLY (1 << 1) + u32 options; + + struct arm_smmu_cmdq cmdq; + struct arm_smmu_evtq evtq; + struct arm_smmu_priq priq; + + int gerr_irq; + int combined_irq; + u32 sync_nr; + u8 prev_cmd_opcode; + + unsigned long ias; /* IPA */ + unsigned long oas; /* PA */ + unsigned long pgsize_bitmap; + +#define ARM_SMMU_MAX_VMIDS (1 << 16) + unsigned int vmid_bits; + DECLARE_BITMAP(vmid_map, ARM_SMMU_MAX_VMIDS); + + unsigned int sid_bits; + + struct arm_smmu_strtab_cfg strtab_cfg; + + /* Hi16xx adds an extra 32 bits of goodness to its MSI payload */ + union { + u32 sync_count; + u64 padding; + }; + + /* Need to keep a list of SMMU devices */ + struct list_head devices; + + /* Tasklets for handling evts/faults and pci page request IRQs*/ + struct tasklet evtq_irq_tasklet; + struct tasklet priq_irq_tasklet; + struct tasklet combined_irq_tasklet; +}; + +/* SMMU private data for each master */ +struct arm_smmu_master { + struct arm_smmu_device *smmu; + struct device *dev; + struct arm_smmu_domain *domain; + struct list_head domain_head; + u32 *sids; + unsigned int num_sids; + bool ats_enabled; +}; + +struct arm_smmu_domain { + struct arm_smmu_device *smmu; + struct mutex init_mutex; /* Protects smmu pointer */ + + bool non_strict; + atomic_t nr_ats_masters; + + enum arm_smmu_domain_stage stage; + struct arm_smmu_s2_cfg s2_cfg; + + /* Xen domain associated with this SMMU domain */ + struct domain *d; + + struct iommu_domain domain; + + struct list_head devices; + spinlock_t devices_lock; +}; + +#endif /* _ARM_SMMU_V3_H */ -- 2.25.1 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH v3 04/10] xen/arm: smmuv3: Move definitions to a header 2022-09-05 16:30 ` [PATCH v3 04/10] xen/arm: smmuv3: Move definitions to a header Rahul Singh @ 2022-09-05 22:20 ` Stefano Stabellini 0 siblings, 0 replies; 17+ messages in thread From: Stefano Stabellini @ 2022-09-05 22:20 UTC (permalink / raw) To: Rahul Singh Cc: xen-devel, Jean-Philippe Brucker, Bertrand Marquis, Stefano Stabellini, Julien Grall, Volodymyr Babchuk, Eric Auger, Jonathan Cameron, Will Deacon On Mon, 5 Sep 2022, Rahul Singh wrote: > From: Jean-Philippe Brucker <jean-philippe@linaro.org> > > Backport Linux commit e881e7839fba. Also, move Xen related struct > definition to header to get it compiled. > > Allow sharing structure definitions with the upcoming SVA support for > Arm SMMUv3, by moving them to a separate header. We could surgically > extract only what is needed but keeping all definitions in one place > looks nicer. > > Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> > Reviewed-by: Eric Auger <eric.auger@redhat.com> > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > Link: https://lore.kernel.org/r/20200918101852.582559-8-jean-philippe@linaro.org > Signed-off-by: Will Deacon <will@kernel.org> > Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git e881e7839fba > Signed-off-by: Rahul Singh <rahul.singh@arm.com> Acked-by: Stefano Stabellini <sstabellini@kernel.org> > --- > Changes in v3: > - remove clean backport msg in commit msg > Changes in v2: > - fix commit msg > - also move struct definition to header file to sync with Linux patch > --- > xen/drivers/passthrough/arm/smmu-v3.c | 665 +------------------------ > xen/drivers/passthrough/arm/smmu-v3.h | 674 ++++++++++++++++++++++++++ > 2 files changed, 675 insertions(+), 664 deletions(-) > create mode 100644 xen/drivers/passthrough/arm/smmu-v3.h > > diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthrough/arm/smmu-v3.c > index e632c75b21..e65b226b85 100644 > --- a/xen/drivers/passthrough/arm/smmu-v3.c > +++ b/xen/drivers/passthrough/arm/smmu-v3.c > @@ -90,6 +90,7 @@ > #include <asm/iommu_fwspec.h> > #include <asm/platform.h> > > +#include "smmu-v3.h" > > #define ARM_SMMU_VTCR_SH_IS 3 > #define ARM_SMMU_VTCR_RGN_WBWA 1 > @@ -103,22 +104,12 @@ > #define ARM_SMMU_VTCR_PS_52_BIT 0x6ULL > > /* Linux compatibility functions. */ > -typedef paddr_t dma_addr_t; > -typedef paddr_t phys_addr_t; > -typedef unsigned int gfp_t; > - > #define iomb() dmb(osh) > > #define platform_device device > > #define GFP_KERNEL 0 > > -/* Alias to Xen lock functions */ > -#define mutex spinlock > -#define mutex_init spin_lock_init > -#define mutex_lock spin_lock > -#define mutex_unlock spin_unlock > - > /* Device logger functions */ > #define dev_name(dev) dt_node_full_name(dev->of_node) > #define dev_dbg(dev, fmt, ...) \ > @@ -159,12 +150,6 @@ typedef unsigned int gfp_t; > #define readl_relaxed_poll_timeout(addr, val, cond, delay_us, timeout_us) \ > readx_poll_timeout(readl_relaxed, addr, val, cond, delay_us, timeout_us) > > -#define FIELD_PREP(_mask, _val) \ > - (((typeof(_mask))(_val) << (ffs64(_mask) - 1)) & (_mask)) > - > -#define FIELD_GET(_mask, _reg) \ > - ((typeof(_mask))(((_reg) & (_mask)) >> (ffs64(_mask) - 1))) > - > /* > * Helpers for DMA allocation. Just the function name is reused for > * porting code, these allocation are not managed allocations > @@ -197,27 +182,6 @@ static void *dmam_alloc_coherent(struct device *dev, size_t size, > return vaddr; > } > > - > -/* Xen specific code. */ > -struct iommu_domain { > - /* Runtime SMMU configuration for this iommu_domain */ > - atomic_t ref; > - /* > - * Used to link iommu_domain contexts for a same domain. > - * There is at least one per-SMMU to used by the domain. > - */ > - struct list_head list; > -}; > - > -/* Describes information required for a Xen domain */ > -struct arm_smmu_xen_domain { > - spinlock_t lock; > - > - /* List of iommu domains associated to this domain */ > - struct list_head contexts; > -}; > - > - > /* Keep a list of devices associated with this driver */ > static DEFINE_SPINLOCK(arm_smmu_devices_lock); > static LIST_HEAD(arm_smmu_devices); > @@ -261,635 +225,8 @@ static int platform_get_irq_byname_optional(struct device *dev, > } > > /* Start of Linux SMMUv3 code */ > -/* MMIO registers */ > -#define ARM_SMMU_IDR0 0x0 > -#define IDR0_ST_LVL GENMASK(28, 27) > -#define IDR0_ST_LVL_2LVL 1 > -#define IDR0_STALL_MODEL GENMASK(25, 24) > -#define IDR0_STALL_MODEL_STALL 0 > -#define IDR0_STALL_MODEL_FORCE 2 > -#define IDR0_TTENDIAN GENMASK(22, 21) > -#define IDR0_TTENDIAN_MIXED 0 > -#define IDR0_TTENDIAN_LE 2 > -#define IDR0_TTENDIAN_BE 3 > -#define IDR0_CD2L (1 << 19) > -#define IDR0_VMID16 (1 << 18) > -#define IDR0_PRI (1 << 16) > -#define IDR0_SEV (1 << 14) > -#define IDR0_MSI (1 << 13) > -#define IDR0_ASID16 (1 << 12) > -#define IDR0_ATS (1 << 10) > -#define IDR0_HYP (1 << 9) > -#define IDR0_COHACC (1 << 4) > -#define IDR0_TTF GENMASK(3, 2) > -#define IDR0_TTF_AARCH64 2 > -#define IDR0_TTF_AARCH32_64 3 > -#define IDR0_S1P (1 << 1) > -#define IDR0_S2P (1 << 0) > - > -#define ARM_SMMU_IDR1 0x4 > -#define IDR1_TABLES_PRESET (1 << 30) > -#define IDR1_QUEUES_PRESET (1 << 29) > -#define IDR1_REL (1 << 28) > -#define IDR1_CMDQS GENMASK(25, 21) > -#define IDR1_EVTQS GENMASK(20, 16) > -#define IDR1_PRIQS GENMASK(15, 11) > -#define IDR1_SSIDSIZE GENMASK(10, 6) > -#define IDR1_SIDSIZE GENMASK(5, 0) > - > -#define ARM_SMMU_IDR5 0x14 > -#define IDR5_STALL_MAX GENMASK(31, 16) > -#define IDR5_GRAN64K (1 << 6) > -#define IDR5_GRAN16K (1 << 5) > -#define IDR5_GRAN4K (1 << 4) > -#define IDR5_OAS GENMASK(2, 0) > -#define IDR5_OAS_32_BIT 0 > -#define IDR5_OAS_36_BIT 1 > -#define IDR5_OAS_40_BIT 2 > -#define IDR5_OAS_42_BIT 3 > -#define IDR5_OAS_44_BIT 4 > -#define IDR5_OAS_48_BIT 5 > -#define IDR5_OAS_52_BIT 6 > -#define IDR5_VAX GENMASK(11, 10) > -#define IDR5_VAX_52_BIT 1 > - > -#define ARM_SMMU_CR0 0x20 > -#define CR0_ATSCHK (1 << 4) > -#define CR0_CMDQEN (1 << 3) > -#define CR0_EVTQEN (1 << 2) > -#define CR0_PRIQEN (1 << 1) > -#define CR0_SMMUEN (1 << 0) > - > -#define ARM_SMMU_CR0ACK 0x24 > - > -#define ARM_SMMU_CR1 0x28 > -#define CR1_TABLE_SH GENMASK(11, 10) > -#define CR1_TABLE_OC GENMASK(9, 8) > -#define CR1_TABLE_IC GENMASK(7, 6) > -#define CR1_QUEUE_SH GENMASK(5, 4) > -#define CR1_QUEUE_OC GENMASK(3, 2) > -#define CR1_QUEUE_IC GENMASK(1, 0) > -/* CR1 cacheability fields don't quite follow the usual TCR-style encoding */ > -#define CR1_CACHE_NC 0 > -#define CR1_CACHE_WB 1 > -#define CR1_CACHE_WT 2 > - > -#define ARM_SMMU_CR2 0x2c > -#define CR2_PTM (1 << 2) > -#define CR2_RECINVSID (1 << 1) > -#define CR2_E2H (1 << 0) > - > -#define ARM_SMMU_GBPA 0x44 > -#define GBPA_UPDATE (1U << 31) > -#define GBPA_ABORT (1 << 20) > - > -#define ARM_SMMU_IRQ_CTRL 0x50 > -#define IRQ_CTRL_EVTQ_IRQEN (1 << 2) > -#define IRQ_CTRL_PRIQ_IRQEN (1 << 1) > -#define IRQ_CTRL_GERROR_IRQEN (1 << 0) > - > -#define ARM_SMMU_IRQ_CTRLACK 0x54 > - > -#define ARM_SMMU_GERROR 0x60 > -#define GERROR_SFM_ERR (1 << 8) > -#define GERROR_MSI_GERROR_ABT_ERR (1 << 7) > -#define GERROR_MSI_PRIQ_ABT_ERR (1 << 6) > -#define GERROR_MSI_EVTQ_ABT_ERR (1 << 5) > -#define GERROR_MSI_CMDQ_ABT_ERR (1 << 4) > -#define GERROR_PRIQ_ABT_ERR (1 << 3) > -#define GERROR_EVTQ_ABT_ERR (1 << 2) > -#define GERROR_CMDQ_ERR (1 << 0) > -#define GERROR_ERR_MASK 0xfd > - > -#define ARM_SMMU_GERRORN 0x64 > - > -#define ARM_SMMU_GERROR_IRQ_CFG0 0x68 > -#define ARM_SMMU_GERROR_IRQ_CFG1 0x70 > -#define ARM_SMMU_GERROR_IRQ_CFG2 0x74 > - > -#define ARM_SMMU_STRTAB_BASE 0x80 > -#define STRTAB_BASE_RA (1UL << 62) > -#define STRTAB_BASE_ADDR_MASK GENMASK_ULL(51, 6) > - > -#define ARM_SMMU_STRTAB_BASE_CFG 0x88 > -#define STRTAB_BASE_CFG_FMT GENMASK(17, 16) > -#define STRTAB_BASE_CFG_FMT_LINEAR 0 > -#define STRTAB_BASE_CFG_FMT_2LVL 1 > -#define STRTAB_BASE_CFG_SPLIT GENMASK(10, 6) > -#define STRTAB_BASE_CFG_LOG2SIZE GENMASK(5, 0) > - > -#define ARM_SMMU_CMDQ_BASE 0x90 > -#define ARM_SMMU_CMDQ_PROD 0x98 > -#define ARM_SMMU_CMDQ_CONS 0x9c > - > -#define ARM_SMMU_EVTQ_BASE 0xa0 > -#define ARM_SMMU_EVTQ_PROD 0x100a8 > -#define ARM_SMMU_EVTQ_CONS 0x100ac > -#define ARM_SMMU_EVTQ_IRQ_CFG0 0xb0 > -#define ARM_SMMU_EVTQ_IRQ_CFG1 0xb8 > -#define ARM_SMMU_EVTQ_IRQ_CFG2 0xbc > - > -#define ARM_SMMU_PRIQ_BASE 0xc0 > -#define ARM_SMMU_PRIQ_PROD 0x100c8 > -#define ARM_SMMU_PRIQ_CONS 0x100cc > -#define ARM_SMMU_PRIQ_IRQ_CFG0 0xd0 > -#define ARM_SMMU_PRIQ_IRQ_CFG1 0xd8 > -#define ARM_SMMU_PRIQ_IRQ_CFG2 0xdc > - > -#define ARM_SMMU_REG_SZ 0xe00 > - > -/* Common MSI config fields */ > -#define MSI_CFG0_ADDR_MASK GENMASK_ULL(51, 2) > -#define MSI_CFG2_SH GENMASK(5, 4) > -#define MSI_CFG2_MEMATTR GENMASK(3, 0) > - > -/* Common memory attribute values */ > -#define ARM_SMMU_SH_NSH 0 > -#define ARM_SMMU_SH_OSH 2 > -#define ARM_SMMU_SH_ISH 3 > -#define ARM_SMMU_MEMATTR_DEVICE_nGnRE 0x1 > -#define ARM_SMMU_MEMATTR_OIWB 0xf > - > -#define Q_IDX(llq, p) ((p) & ((1 << (llq)->max_n_shift) - 1)) > -#define Q_WRP(llq, p) ((p) & (1 << (llq)->max_n_shift)) > -#define Q_OVERFLOW_FLAG (1U << 31) > -#define Q_OVF(p) ((p) & Q_OVERFLOW_FLAG) > -#define Q_ENT(q, p) ((q)->base + \ > - Q_IDX(&((q)->llq), p) * \ > - (q)->ent_dwords) > - > -#define Q_BASE_RWA (1UL << 62) > -#define Q_BASE_ADDR_MASK GENMASK_ULL(51, 5) > -#define Q_BASE_LOG2SIZE GENMASK(4, 0) > - > -/* Ensure DMA allocations are naturally aligned */ > -#ifdef CONFIG_CMA_ALIGNMENT > -#define Q_MAX_SZ_SHIFT (PAGE_SHIFT + CONFIG_CMA_ALIGNMENT) > -#else > -#define Q_MAX_SZ_SHIFT (PAGE_SHIFT + MAX_ORDER - 1) > -#endif > - > -/* > - * Stream table. > - * > - * Linear: Enough to cover 1 << IDR1.SIDSIZE entries > - * 2lvl: 128k L1 entries, > - * 256 lazy entries per table (each table covers a PCI bus) > - */ > -#define STRTAB_L1_SZ_SHIFT 20 > -#define STRTAB_SPLIT 8 > - > -#define STRTAB_L1_DESC_DWORDS 1 > -#define STRTAB_L1_DESC_SPAN GENMASK_ULL(4, 0) > -#define STRTAB_L1_DESC_L2PTR_MASK GENMASK_ULL(51, 6) > - > -#define STRTAB_STE_DWORDS 8 > -#define STRTAB_STE_0_V (1UL << 0) > -#define STRTAB_STE_0_CFG GENMASK_ULL(3, 1) > -#define STRTAB_STE_0_CFG_ABORT 0 > -#define STRTAB_STE_0_CFG_BYPASS 4 > -#define STRTAB_STE_0_CFG_S1_TRANS 5 > -#define STRTAB_STE_0_CFG_S2_TRANS 6 > - > -#define STRTAB_STE_0_S1FMT GENMASK_ULL(5, 4) > -#define STRTAB_STE_0_S1FMT_LINEAR 0 > -#define STRTAB_STE_0_S1FMT_64K_L2 2 > -#define STRTAB_STE_0_S1CTXPTR_MASK GENMASK_ULL(51, 6) > -#define STRTAB_STE_0_S1CDMAX GENMASK_ULL(63, 59) > - > -#define STRTAB_STE_1_S1DSS GENMASK_ULL(1, 0) > -#define STRTAB_STE_1_S1DSS_TERMINATE 0x0 > -#define STRTAB_STE_1_S1DSS_BYPASS 0x1 > -#define STRTAB_STE_1_S1DSS_SSID0 0x2 > - > -#define STRTAB_STE_1_S1C_CACHE_NC 0UL > -#define STRTAB_STE_1_S1C_CACHE_WBRA 1UL > -#define STRTAB_STE_1_S1C_CACHE_WT 2UL > -#define STRTAB_STE_1_S1C_CACHE_WB 3UL > -#define STRTAB_STE_1_S1CIR GENMASK_ULL(3, 2) > -#define STRTAB_STE_1_S1COR GENMASK_ULL(5, 4) > -#define STRTAB_STE_1_S1CSH GENMASK_ULL(7, 6) > - > -#define STRTAB_STE_1_S1STALLD (1UL << 27) > - > -#define STRTAB_STE_1_EATS GENMASK_ULL(29, 28) > -#define STRTAB_STE_1_EATS_ABT 0UL > -#define STRTAB_STE_1_EATS_TRANS 1UL > -#define STRTAB_STE_1_EATS_S1CHK 2UL > - > -#define STRTAB_STE_1_STRW GENMASK_ULL(31, 30) > -#define STRTAB_STE_1_STRW_NSEL1 0UL > -#define STRTAB_STE_1_STRW_EL2 2UL > - > -#define STRTAB_STE_1_SHCFG GENMASK_ULL(45, 44) > -#define STRTAB_STE_1_SHCFG_INCOMING 1UL > - > -#define STRTAB_STE_2_S2VMID GENMASK_ULL(15, 0) > -#define STRTAB_STE_2_VTCR GENMASK_ULL(50, 32) > -#define STRTAB_STE_2_VTCR_S2T0SZ GENMASK_ULL(5, 0) > -#define STRTAB_STE_2_VTCR_S2SL0 GENMASK_ULL(7, 6) > -#define STRTAB_STE_2_VTCR_S2IR0 GENMASK_ULL(9, 8) > -#define STRTAB_STE_2_VTCR_S2OR0 GENMASK_ULL(11, 10) > -#define STRTAB_STE_2_VTCR_S2SH0 GENMASK_ULL(13, 12) > -#define STRTAB_STE_2_VTCR_S2TG GENMASK_ULL(15, 14) > -#define STRTAB_STE_2_VTCR_S2PS GENMASK_ULL(18, 16) > -#define STRTAB_STE_2_S2AA64 (1UL << 51) > -#define STRTAB_STE_2_S2ENDI (1UL << 52) > -#define STRTAB_STE_2_S2PTW (1UL << 54) > -#define STRTAB_STE_2_S2R (1UL << 58) > - > -#define STRTAB_STE_3_S2TTB_MASK GENMASK_ULL(51, 4) > - > -/* > - * Context descriptors. > - * > - * Linear: when less than 1024 SSIDs are supported > - * 2lvl: at most 1024 L1 entries, > - * 1024 lazy entries per table. > - */ > -#define CTXDESC_SPLIT 10 > -#define CTXDESC_L2_ENTRIES (1 << CTXDESC_SPLIT) > - > -#define CTXDESC_L1_DESC_DWORDS 1 > -#define CTXDESC_L1_DESC_V (1UL << 0) > -#define CTXDESC_L1_DESC_L2PTR_MASK GENMASK_ULL(51, 12) > - > -#define CTXDESC_CD_DWORDS 8 > -#define CTXDESC_CD_0_TCR_T0SZ GENMASK_ULL(5, 0) > -#define CTXDESC_CD_0_TCR_TG0 GENMASK_ULL(7, 6) > -#define CTXDESC_CD_0_TCR_IRGN0 GENMASK_ULL(9, 8) > -#define CTXDESC_CD_0_TCR_ORGN0 GENMASK_ULL(11, 10) > -#define CTXDESC_CD_0_TCR_SH0 GENMASK_ULL(13, 12) > -#define CTXDESC_CD_0_TCR_EPD0 (1ULL << 14) > -#define CTXDESC_CD_0_TCR_EPD1 (1ULL << 30) > - > -#define CTXDESC_CD_0_ENDI (1UL << 15) > -#define CTXDESC_CD_0_V (1UL << 31) > - > -#define CTXDESC_CD_0_TCR_IPS GENMASK_ULL(34, 32) > -#define CTXDESC_CD_0_TCR_TBI0 (1ULL << 38) > - > -#define CTXDESC_CD_0_AA64 (1UL << 41) > -#define CTXDESC_CD_0_S (1UL << 44) > -#define CTXDESC_CD_0_R (1UL << 45) > -#define CTXDESC_CD_0_A (1UL << 46) > -#define CTXDESC_CD_0_ASET (1UL << 47) > -#define CTXDESC_CD_0_ASID GENMASK_ULL(63, 48) > - > -#define CTXDESC_CD_1_TTB0_MASK GENMASK_ULL(51, 4) > - > -/* > - * When the SMMU only supports linear context descriptor tables, pick a > - * reasonable size limit (64kB). > - */ > -#define CTXDESC_LINEAR_CDMAX ilog2(SZ_64K / (CTXDESC_CD_DWORDS << 3)) > - > -/* Command queue */ > -#define CMDQ_ENT_SZ_SHIFT 4 > -#define CMDQ_ENT_DWORDS ((1 << CMDQ_ENT_SZ_SHIFT) >> 3) > -#define CMDQ_MAX_SZ_SHIFT (Q_MAX_SZ_SHIFT - CMDQ_ENT_SZ_SHIFT) > - > -#define CMDQ_CONS_ERR GENMASK(30, 24) > -#define CMDQ_ERR_CERROR_NONE_IDX 0 > -#define CMDQ_ERR_CERROR_ILL_IDX 1 > -#define CMDQ_ERR_CERROR_ABT_IDX 2 > -#define CMDQ_ERR_CERROR_ATC_INV_IDX 3 > - > -#define CMDQ_0_OP GENMASK_ULL(7, 0) > -#define CMDQ_0_SSV (1UL << 11) > - > -#define CMDQ_PREFETCH_0_SID GENMASK_ULL(63, 32) > -#define CMDQ_PREFETCH_1_SIZE GENMASK_ULL(4, 0) > -#define CMDQ_PREFETCH_1_ADDR_MASK GENMASK_ULL(63, 12) > - > -#define CMDQ_CFGI_0_SSID GENMASK_ULL(31, 12) > -#define CMDQ_CFGI_0_SID GENMASK_ULL(63, 32) > -#define CMDQ_CFGI_1_LEAF (1UL << 0) > -#define CMDQ_CFGI_1_RANGE GENMASK_ULL(4, 0) > - > -#define CMDQ_TLBI_0_VMID GENMASK_ULL(47, 32) > -#define CMDQ_TLBI_0_ASID GENMASK_ULL(63, 48) > -#define CMDQ_TLBI_1_LEAF (1UL << 0) > -#define CMDQ_TLBI_1_VA_MASK GENMASK_ULL(63, 12) > -#define CMDQ_TLBI_1_IPA_MASK GENMASK_ULL(51, 12) > - > -#define CMDQ_ATC_0_SSID GENMASK_ULL(31, 12) > -#define CMDQ_ATC_0_SID GENMASK_ULL(63, 32) > -#define CMDQ_ATC_0_GLOBAL (1UL << 9) > -#define CMDQ_ATC_1_SIZE GENMASK_ULL(5, 0) > -#define CMDQ_ATC_1_ADDR_MASK GENMASK_ULL(63, 12) > - > -#define CMDQ_PRI_0_SSID GENMASK_ULL(31, 12) > -#define CMDQ_PRI_0_SID GENMASK_ULL(63, 32) > -#define CMDQ_PRI_1_GRPID GENMASK_ULL(8, 0) > -#define CMDQ_PRI_1_RESP GENMASK_ULL(13, 12) > - > -#define CMDQ_SYNC_0_CS GENMASK_ULL(13, 12) > -#define CMDQ_SYNC_0_CS_NONE 0 > -#define CMDQ_SYNC_0_CS_IRQ 1 > -#define CMDQ_SYNC_0_CS_SEV 2 > -#define CMDQ_SYNC_0_MSH GENMASK_ULL(23, 22) > -#define CMDQ_SYNC_0_MSIATTR GENMASK_ULL(27, 24) > -#define CMDQ_SYNC_0_MSIDATA GENMASK_ULL(63, 32) > -#define CMDQ_SYNC_1_MSIADDR_MASK GENMASK_ULL(51, 2) > - > -/* Event queue */ > -#define EVTQ_ENT_SZ_SHIFT 5 > -#define EVTQ_ENT_DWORDS ((1 << EVTQ_ENT_SZ_SHIFT) >> 3) > -#define EVTQ_MAX_SZ_SHIFT (Q_MAX_SZ_SHIFT - EVTQ_ENT_SZ_SHIFT) > - > -#define EVTQ_0_ID GENMASK_ULL(7, 0) > - > -/* PRI queue */ > -#define PRIQ_ENT_SZ_SHIFT 4 > -#define PRIQ_ENT_DWORDS ((1 << PRIQ_ENT_SZ_SHIFT) >> 3) > -#define PRIQ_MAX_SZ_SHIFT (Q_MAX_SZ_SHIFT - PRIQ_ENT_SZ_SHIFT) > - > -#define PRIQ_0_SID GENMASK_ULL(31, 0) > -#define PRIQ_0_SSID GENMASK_ULL(51, 32) > -#define PRIQ_0_PERM_PRIV (1UL << 58) > -#define PRIQ_0_PERM_EXEC (1UL << 59) > -#define PRIQ_0_PERM_READ (1UL << 60) > -#define PRIQ_0_PERM_WRITE (1UL << 61) > -#define PRIQ_0_PRG_LAST (1UL << 62) > -#define PRIQ_0_SSID_V (1UL << 63) > - > -#define PRIQ_1_PRG_IDX GENMASK_ULL(8, 0) > -#define PRIQ_1_ADDR_MASK GENMASK_ULL(63, 12) > - > -/* High-level queue structures */ > -#define ARM_SMMU_POLL_TIMEOUT_US 100 > -#define ARM_SMMU_CMDQ_SYNC_TIMEOUT_US 1000000 /* 1s! */ > -#define ARM_SMMU_CMDQ_SYNC_SPIN_COUNT 10 > - > static bool disable_bypass = 1; > > -enum pri_resp { > - PRI_RESP_DENY = 0, > - PRI_RESP_FAIL = 1, > - PRI_RESP_SUCC = 2, > -}; > - > -#ifdef CONFIG_MSI > -enum arm_smmu_msi_index { > - EVTQ_MSI_INDEX, > - GERROR_MSI_INDEX, > - PRIQ_MSI_INDEX, > - ARM_SMMU_MAX_MSIS, > -}; > - > -static phys_addr_t arm_smmu_msi_cfg[ARM_SMMU_MAX_MSIS][3] = { > - [EVTQ_MSI_INDEX] = { > - ARM_SMMU_EVTQ_IRQ_CFG0, > - ARM_SMMU_EVTQ_IRQ_CFG1, > - ARM_SMMU_EVTQ_IRQ_CFG2, > - }, > - [GERROR_MSI_INDEX] = { > - ARM_SMMU_GERROR_IRQ_CFG0, > - ARM_SMMU_GERROR_IRQ_CFG1, > - ARM_SMMU_GERROR_IRQ_CFG2, > - }, > - [PRIQ_MSI_INDEX] = { > - ARM_SMMU_PRIQ_IRQ_CFG0, > - ARM_SMMU_PRIQ_IRQ_CFG1, > - ARM_SMMU_PRIQ_IRQ_CFG2, > - }, > -}; > -#endif /* CONFIG_MSI */ > - > -struct arm_smmu_cmdq_ent { > - /* Common fields */ > - u8 opcode; > - bool substream_valid; > - > - /* Command-specific fields */ > - union { > - #define CMDQ_OP_PREFETCH_CFG 0x1 > - struct { > - u32 sid; > - u8 size; > - u64 addr; > - } prefetch; > - > - #define CMDQ_OP_CFGI_STE 0x3 > - #define CMDQ_OP_CFGI_ALL 0x4 > - struct { > - u32 sid; > - union { > - bool leaf; > - u8 span; > - }; > - } cfgi; > - > - #define CMDQ_OP_TLBI_EL2_ALL 0x20 > - #define CMDQ_OP_TLBI_S12_VMALL 0x28 > - #define CMDQ_OP_TLBI_S2_IPA 0x2a > - #define CMDQ_OP_TLBI_NSNH_ALL 0x30 > - struct { > - u16 asid; > - u16 vmid; > - bool leaf; > - u64 addr; > - } tlbi; > - > - #define CMDQ_OP_ATC_INV 0x40 > - #define ATC_INV_SIZE_ALL 52 > - struct { > - u32 sid; > - u32 ssid; > - u64 addr; > - u8 size; > - bool global; > - } atc; > - > - #define CMDQ_OP_PRI_RESP 0x41 > - struct { > - u32 sid; > - u32 ssid; > - u16 grpid; > - enum pri_resp resp; > - } pri; > - > - #define CMDQ_OP_CMD_SYNC 0x46 > - struct { > - u32 msidata; > - u64 msiaddr; > - } sync; > - }; > -}; > - > -struct arm_smmu_ll_queue { > - u32 prod; > - u32 cons; > - u32 max_n_shift; > -}; > - > -struct arm_smmu_queue { > - struct arm_smmu_ll_queue llq; > - int irq; /* Wired interrupt */ > - > - __le64 *base; > - dma_addr_t base_dma; > - u64 q_base; > - > - size_t ent_dwords; > - > - u32 __iomem *prod_reg; > - u32 __iomem *cons_reg; > -}; > - > -struct arm_smmu_cmdq { > - struct arm_smmu_queue q; > - spinlock_t lock; > -}; > - > -struct arm_smmu_evtq { > - struct arm_smmu_queue q; > - u32 max_stalls; > -}; > - > -struct arm_smmu_priq { > - struct arm_smmu_queue q; > -}; > - > -/* High-level stream table and context descriptor structures */ > -struct arm_smmu_strtab_l1_desc { > - u8 span; > - > - __le64 *l2ptr; > - dma_addr_t l2ptr_dma; > -}; > - > -struct arm_smmu_s2_cfg { > - u16 vmid; > - u64 vttbr; > - u64 vtcr; > -}; > - > -struct arm_smmu_strtab_cfg { > - __le64 *strtab; > - dma_addr_t strtab_dma; > - struct arm_smmu_strtab_l1_desc *l1_desc; > - unsigned int num_l1_ents; > - > - u64 strtab_base; > - u32 strtab_base_cfg; > -}; > - > -struct arm_lpae_s2_cfg { > - u64 vttbr; > - struct { > - u32 ps:3; > - u32 tg:2; > - u32 sh:2; > - u32 orgn:2; > - u32 irgn:2; > - u32 sl:2; > - u32 tsz:6; > - } vtcr; > -}; > - > -/* An SMMUv3 instance */ > -struct arm_smmu_device { > - struct device *dev; > - void __iomem *base; > - void __iomem *page1; > - > -#define ARM_SMMU_FEAT_2_LVL_STRTAB (1 << 0) > -#define ARM_SMMU_FEAT_2_LVL_CDTAB (1 << 1) > -#define ARM_SMMU_FEAT_TT_LE (1 << 2) > -#define ARM_SMMU_FEAT_TT_BE (1 << 3) > -#define ARM_SMMU_FEAT_PRI (1 << 4) > -#define ARM_SMMU_FEAT_ATS (1 << 5) > -#define ARM_SMMU_FEAT_SEV (1 << 6) > -#define ARM_SMMU_FEAT_MSI (1 << 7) > -#define ARM_SMMU_FEAT_COHERENCY (1 << 8) > -#define ARM_SMMU_FEAT_TRANS_S1 (1 << 9) > -#define ARM_SMMU_FEAT_TRANS_S2 (1 << 10) > -#define ARM_SMMU_FEAT_STALLS (1 << 11) > -#define ARM_SMMU_FEAT_HYP (1 << 12) > -#define ARM_SMMU_FEAT_STALL_FORCE (1 << 13) > -#define ARM_SMMU_FEAT_VAX (1 << 14) > - u32 features; > - > -#define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) > -#define ARM_SMMU_OPT_PAGE0_REGS_ONLY (1 << 1) > - u32 options; > - > - struct arm_smmu_cmdq cmdq; > - struct arm_smmu_evtq evtq; > - struct arm_smmu_priq priq; > - > - int gerr_irq; > - int combined_irq; > - u32 sync_nr; > - u8 prev_cmd_opcode; > - > - unsigned long ias; /* IPA */ > - unsigned long oas; /* PA */ > - unsigned long pgsize_bitmap; > - > -#define ARM_SMMU_MAX_VMIDS (1 << 16) > - unsigned int vmid_bits; > - DECLARE_BITMAP(vmid_map, ARM_SMMU_MAX_VMIDS); > - > - unsigned int sid_bits; > - > - struct arm_smmu_strtab_cfg strtab_cfg; > - > - /* Hi16xx adds an extra 32 bits of goodness to its MSI payload */ > - union { > - u32 sync_count; > - u64 padding; > - }; > - > - /* Need to keep a list of SMMU devices */ > - struct list_head devices; > - > - /* Tasklets for handling evts/faults and pci page request IRQs*/ > - struct tasklet evtq_irq_tasklet; > - struct tasklet priq_irq_tasklet; > - struct tasklet combined_irq_tasklet; > -}; > - > -/* SMMU private data for each master */ > -struct arm_smmu_master { > - struct arm_smmu_device *smmu; > - struct device *dev; > - struct arm_smmu_domain *domain; > - struct list_head domain_head; > - u32 *sids; > - unsigned int num_sids; > - bool ats_enabled; > -}; > - > -/* SMMU private data for an IOMMU domain */ > -enum arm_smmu_domain_stage { > - ARM_SMMU_DOMAIN_S1 = 0, > - ARM_SMMU_DOMAIN_S2, > - ARM_SMMU_DOMAIN_NESTED, > - ARM_SMMU_DOMAIN_BYPASS, > -}; > - > -struct arm_smmu_domain { > - struct arm_smmu_device *smmu; > - struct mutex init_mutex; /* Protects smmu pointer */ > - > - bool non_strict; > - atomic_t nr_ats_masters; > - > - enum arm_smmu_domain_stage stage; > - struct arm_smmu_s2_cfg s2_cfg; > - > - /* Xen domain associated with this SMMU domain */ > - struct domain *d; > - > - struct iommu_domain domain; > - > - struct list_head devices; > - spinlock_t devices_lock; > -}; > - > struct arm_smmu_option_prop { > u32 opt; > const char *prop; > diff --git a/xen/drivers/passthrough/arm/smmu-v3.h b/xen/drivers/passthrough/arm/smmu-v3.h > new file mode 100644 > index 0000000000..c45d2f16c4 > --- /dev/null > +++ b/xen/drivers/passthrough/arm/smmu-v3.h > @@ -0,0 +1,674 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * IOMMU API for ARM architected SMMUv3 implementations. > + * > + * Copyright (C) 2022 ARM Limited > + */ > + > +#ifndef _ARM_SMMU_V3_H > +#define _ARM_SMMU_V3_H > + > +/* MMIO registers */ > +#define ARM_SMMU_IDR0 0x0 > +#define IDR0_ST_LVL GENMASK(28, 27) > +#define IDR0_ST_LVL_2LVL 1 > +#define IDR0_STALL_MODEL GENMASK(25, 24) > +#define IDR0_STALL_MODEL_STALL 0 > +#define IDR0_STALL_MODEL_FORCE 2 > +#define IDR0_TTENDIAN GENMASK(22, 21) > +#define IDR0_TTENDIAN_MIXED 0 > +#define IDR0_TTENDIAN_LE 2 > +#define IDR0_TTENDIAN_BE 3 > +#define IDR0_CD2L (1 << 19) > +#define IDR0_VMID16 (1 << 18) > +#define IDR0_PRI (1 << 16) > +#define IDR0_SEV (1 << 14) > +#define IDR0_MSI (1 << 13) > +#define IDR0_ASID16 (1 << 12) > +#define IDR0_ATS (1 << 10) > +#define IDR0_HYP (1 << 9) > +#define IDR0_COHACC (1 << 4) > +#define IDR0_TTF GENMASK(3, 2) > +#define IDR0_TTF_AARCH64 2 > +#define IDR0_TTF_AARCH32_64 3 > +#define IDR0_S1P (1 << 1) > +#define IDR0_S2P (1 << 0) > + > +#define ARM_SMMU_IDR1 0x4 > +#define IDR1_TABLES_PRESET (1 << 30) > +#define IDR1_QUEUES_PRESET (1 << 29) > +#define IDR1_REL (1 << 28) > +#define IDR1_CMDQS GENMASK(25, 21) > +#define IDR1_EVTQS GENMASK(20, 16) > +#define IDR1_PRIQS GENMASK(15, 11) > +#define IDR1_SSIDSIZE GENMASK(10, 6) > +#define IDR1_SIDSIZE GENMASK(5, 0) > + > +#define ARM_SMMU_IDR5 0x14 > +#define IDR5_STALL_MAX GENMASK(31, 16) > +#define IDR5_GRAN64K (1 << 6) > +#define IDR5_GRAN16K (1 << 5) > +#define IDR5_GRAN4K (1 << 4) > +#define IDR5_OAS GENMASK(2, 0) > +#define IDR5_OAS_32_BIT 0 > +#define IDR5_OAS_36_BIT 1 > +#define IDR5_OAS_40_BIT 2 > +#define IDR5_OAS_42_BIT 3 > +#define IDR5_OAS_44_BIT 4 > +#define IDR5_OAS_48_BIT 5 > +#define IDR5_OAS_52_BIT 6 > +#define IDR5_VAX GENMASK(11, 10) > +#define IDR5_VAX_52_BIT 1 > + > +#define ARM_SMMU_CR0 0x20 > +#define CR0_ATSCHK (1 << 4) > +#define CR0_CMDQEN (1 << 3) > +#define CR0_EVTQEN (1 << 2) > +#define CR0_PRIQEN (1 << 1) > +#define CR0_SMMUEN (1 << 0) > + > +#define ARM_SMMU_CR0ACK 0x24 > + > +#define ARM_SMMU_CR1 0x28 > +#define CR1_TABLE_SH GENMASK(11, 10) > +#define CR1_TABLE_OC GENMASK(9, 8) > +#define CR1_TABLE_IC GENMASK(7, 6) > +#define CR1_QUEUE_SH GENMASK(5, 4) > +#define CR1_QUEUE_OC GENMASK(3, 2) > +#define CR1_QUEUE_IC GENMASK(1, 0) > +/* CR1 cacheability fields don't quite follow the usual TCR-style encoding */ > +#define CR1_CACHE_NC 0 > +#define CR1_CACHE_WB 1 > +#define CR1_CACHE_WT 2 > + > +#define ARM_SMMU_CR2 0x2c > +#define CR2_PTM (1 << 2) > +#define CR2_RECINVSID (1 << 1) > +#define CR2_E2H (1 << 0) > + > +#define ARM_SMMU_GBPA 0x44 > +#define GBPA_UPDATE (1 << 31) > +#define GBPA_ABORT (1 << 20) > + > +#define ARM_SMMU_IRQ_CTRL 0x50 > +#define IRQ_CTRL_EVTQ_IRQEN (1 << 2) > +#define IRQ_CTRL_PRIQ_IRQEN (1 << 1) > +#define IRQ_CTRL_GERROR_IRQEN (1 << 0) > + > +#define ARM_SMMU_IRQ_CTRLACK 0x54 > + > +#define ARM_SMMU_GERROR 0x60 > +#define GERROR_SFM_ERR (1 << 8) > +#define GERROR_MSI_GERROR_ABT_ERR (1 << 7) > +#define GERROR_MSI_PRIQ_ABT_ERR (1 << 6) > +#define GERROR_MSI_EVTQ_ABT_ERR (1 << 5) > +#define GERROR_MSI_CMDQ_ABT_ERR (1 << 4) > +#define GERROR_PRIQ_ABT_ERR (1 << 3) > +#define GERROR_EVTQ_ABT_ERR (1 << 2) > +#define GERROR_CMDQ_ERR (1 << 0) > +#define GERROR_ERR_MASK 0xfd > + > +#define ARM_SMMU_GERRORN 0x64 > + > +#define ARM_SMMU_GERROR_IRQ_CFG0 0x68 > +#define ARM_SMMU_GERROR_IRQ_CFG1 0x70 > +#define ARM_SMMU_GERROR_IRQ_CFG2 0x74 > + > +#define ARM_SMMU_STRTAB_BASE 0x80 > +#define STRTAB_BASE_RA (1UL << 62) > +#define STRTAB_BASE_ADDR_MASK GENMASK_ULL(51, 6) > + > +#define ARM_SMMU_STRTAB_BASE_CFG 0x88 > +#define STRTAB_BASE_CFG_FMT GENMASK(17, 16) > +#define STRTAB_BASE_CFG_FMT_LINEAR 0 > +#define STRTAB_BASE_CFG_FMT_2LVL 1 > +#define STRTAB_BASE_CFG_SPLIT GENMASK(10, 6) > +#define STRTAB_BASE_CFG_LOG2SIZE GENMASK(5, 0) > + > +#define ARM_SMMU_CMDQ_BASE 0x90 > +#define ARM_SMMU_CMDQ_PROD 0x98 > +#define ARM_SMMU_CMDQ_CONS 0x9c > + > +#define ARM_SMMU_EVTQ_BASE 0xa0 > +#define ARM_SMMU_EVTQ_PROD 0x100a8 > +#define ARM_SMMU_EVTQ_CONS 0x100ac > +#define ARM_SMMU_EVTQ_IRQ_CFG0 0xb0 > +#define ARM_SMMU_EVTQ_IRQ_CFG1 0xb8 > +#define ARM_SMMU_EVTQ_IRQ_CFG2 0xbc > + > +#define ARM_SMMU_PRIQ_BASE 0xc0 > +#define ARM_SMMU_PRIQ_PROD 0x100c8 > +#define ARM_SMMU_PRIQ_CONS 0x100cc > +#define ARM_SMMU_PRIQ_IRQ_CFG0 0xd0 > +#define ARM_SMMU_PRIQ_IRQ_CFG1 0xd8 > +#define ARM_SMMU_PRIQ_IRQ_CFG2 0xdc > + > +#define ARM_SMMU_REG_SZ 0xe00 > + > +/* Common MSI config fields */ > +#define MSI_CFG0_ADDR_MASK GENMASK_ULL(51, 2) > +#define MSI_CFG2_SH GENMASK(5, 4) > +#define MSI_CFG2_MEMATTR GENMASK(3, 0) > + > +/* Common memory attribute values */ > +#define ARM_SMMU_SH_NSH 0 > +#define ARM_SMMU_SH_OSH 2 > +#define ARM_SMMU_SH_ISH 3 > +#define ARM_SMMU_MEMATTR_DEVICE_nGnRE 0x1 > +#define ARM_SMMU_MEMATTR_OIWB 0xf > + > +#define Q_IDX(llq, p) ((p) & ((1 << (llq)->max_n_shift) - 1)) > +#define Q_WRP(llq, p) ((p) & (1 << (llq)->max_n_shift)) > +#define Q_OVERFLOW_FLAG (1 << 31) > +#define Q_OVF(p) ((p) & Q_OVERFLOW_FLAG) > +#define Q_ENT(q, p) ((q)->base + \ > + Q_IDX(&((q)->llq), p) * \ > + (q)->ent_dwords) > + > +#define Q_BASE_RWA (1UL << 62) > +#define Q_BASE_ADDR_MASK GENMASK_ULL(51, 5) > +#define Q_BASE_LOG2SIZE GENMASK(4, 0) > + > +/* Ensure DMA allocations are naturally aligned */ > +#ifdef CONFIG_CMA_ALIGNMENT > +#define Q_MAX_SZ_SHIFT (PAGE_SHIFT + CONFIG_CMA_ALIGNMENT) > +#else > +#define Q_MAX_SZ_SHIFT (PAGE_SHIFT + MAX_ORDER - 1) > +#endif > + > +/* > + * Stream table. > + * > + * Linear: Enough to cover 1 << IDR1.SIDSIZE entries > + * 2lvl: 128k L1 entries, > + * 256 lazy entries per table (each table covers a PCI bus) > + */ > +#define STRTAB_L1_SZ_SHIFT 20 > +#define STRTAB_SPLIT 8 > + > +#define STRTAB_L1_DESC_DWORDS 1 > +#define STRTAB_L1_DESC_SPAN GENMASK_ULL(4, 0) > +#define STRTAB_L1_DESC_L2PTR_MASK GENMASK_ULL(51, 6) > + > +#define STRTAB_STE_DWORDS 8 > +#define STRTAB_STE_0_V (1UL << 0) > +#define STRTAB_STE_0_CFG GENMASK_ULL(3, 1) > +#define STRTAB_STE_0_CFG_ABORT 0 > +#define STRTAB_STE_0_CFG_BYPASS 4 > +#define STRTAB_STE_0_CFG_S1_TRANS 5 > +#define STRTAB_STE_0_CFG_S2_TRANS 6 > + > +#define STRTAB_STE_0_S1FMT GENMASK_ULL(5, 4) > +#define STRTAB_STE_0_S1FMT_LINEAR 0 > +#define STRTAB_STE_0_S1FMT_64K_L2 2 > +#define STRTAB_STE_0_S1CTXPTR_MASK GENMASK_ULL(51, 6) > +#define STRTAB_STE_0_S1CDMAX GENMASK_ULL(63, 59) > + > +#define STRTAB_STE_1_S1DSS GENMASK_ULL(1, 0) > +#define STRTAB_STE_1_S1DSS_TERMINATE 0x0 > +#define STRTAB_STE_1_S1DSS_BYPASS 0x1 > +#define STRTAB_STE_1_S1DSS_SSID0 0x2 > + > +#define STRTAB_STE_1_S1C_CACHE_NC 0UL > +#define STRTAB_STE_1_S1C_CACHE_WBRA 1UL > +#define STRTAB_STE_1_S1C_CACHE_WT 2UL > +#define STRTAB_STE_1_S1C_CACHE_WB 3UL > +#define STRTAB_STE_1_S1CIR GENMASK_ULL(3, 2) > +#define STRTAB_STE_1_S1COR GENMASK_ULL(5, 4) > +#define STRTAB_STE_1_S1CSH GENMASK_ULL(7, 6) > + > +#define STRTAB_STE_1_S1STALLD (1UL << 27) > + > +#define STRTAB_STE_1_EATS GENMASK_ULL(29, 28) > +#define STRTAB_STE_1_EATS_ABT 0UL > +#define STRTAB_STE_1_EATS_TRANS 1UL > +#define STRTAB_STE_1_EATS_S1CHK 2UL > + > +#define STRTAB_STE_1_STRW GENMASK_ULL(31, 30) > +#define STRTAB_STE_1_STRW_NSEL1 0UL > +#define STRTAB_STE_1_STRW_EL2 2UL > + > +#define STRTAB_STE_1_SHCFG GENMASK_ULL(45, 44) > +#define STRTAB_STE_1_SHCFG_INCOMING 1UL > + > +#define STRTAB_STE_2_S2VMID GENMASK_ULL(15, 0) > +#define STRTAB_STE_2_VTCR GENMASK_ULL(50, 32) > +#define STRTAB_STE_2_VTCR_S2T0SZ GENMASK_ULL(5, 0) > +#define STRTAB_STE_2_VTCR_S2SL0 GENMASK_ULL(7, 6) > +#define STRTAB_STE_2_VTCR_S2IR0 GENMASK_ULL(9, 8) > +#define STRTAB_STE_2_VTCR_S2OR0 GENMASK_ULL(11, 10) > +#define STRTAB_STE_2_VTCR_S2SH0 GENMASK_ULL(13, 12) > +#define STRTAB_STE_2_VTCR_S2TG GENMASK_ULL(15, 14) > +#define STRTAB_STE_2_VTCR_S2PS GENMASK_ULL(18, 16) > +#define STRTAB_STE_2_S2AA64 (1UL << 51) > +#define STRTAB_STE_2_S2ENDI (1UL << 52) > +#define STRTAB_STE_2_S2PTW (1UL << 54) > +#define STRTAB_STE_2_S2R (1UL << 58) > + > +#define STRTAB_STE_3_S2TTB_MASK GENMASK_ULL(51, 4) > + > +/* > + * Context descriptors. > + * > + * Linear: when less than 1024 SSIDs are supported > + * 2lvl: at most 1024 L1 entries, > + * 1024 lazy entries per table. > + */ > +#define CTXDESC_SPLIT 10 > +#define CTXDESC_L2_ENTRIES (1 << CTXDESC_SPLIT) > + > +#define CTXDESC_L1_DESC_DWORDS 1 > +#define CTXDESC_L1_DESC_V (1UL << 0) > +#define CTXDESC_L1_DESC_L2PTR_MASK GENMASK_ULL(51, 12) > + > +#define CTXDESC_CD_DWORDS 8 > +#define CTXDESC_CD_0_TCR_T0SZ GENMASK_ULL(5, 0) > +#define CTXDESC_CD_0_TCR_TG0 GENMASK_ULL(7, 6) > +#define CTXDESC_CD_0_TCR_IRGN0 GENMASK_ULL(9, 8) > +#define CTXDESC_CD_0_TCR_ORGN0 GENMASK_ULL(11, 10) > +#define CTXDESC_CD_0_TCR_SH0 GENMASK_ULL(13, 12) > +#define CTXDESC_CD_0_TCR_EPD0 (1ULL << 14) > +#define CTXDESC_CD_0_TCR_EPD1 (1ULL << 30) > + > +#define CTXDESC_CD_0_ENDI (1UL << 15) > +#define CTXDESC_CD_0_V (1UL << 31) > + > +#define CTXDESC_CD_0_TCR_IPS GENMASK_ULL(34, 32) > +#define CTXDESC_CD_0_TCR_TBI0 (1ULL << 38) > + > +#define CTXDESC_CD_0_AA64 (1UL << 41) > +#define CTXDESC_CD_0_S (1UL << 44) > +#define CTXDESC_CD_0_R (1UL << 45) > +#define CTXDESC_CD_0_A (1UL << 46) > +#define CTXDESC_CD_0_ASET (1UL << 47) > +#define CTXDESC_CD_0_ASID GENMASK_ULL(63, 48) > + > +#define CTXDESC_CD_1_TTB0_MASK GENMASK_ULL(51, 4) > + > +/* > + * When the SMMU only supports linear context descriptor tables, pick a > + * reasonable size limit (64kB). > + */ > +#define CTXDESC_LINEAR_CDMAX ilog2(SZ_64K / (CTXDESC_CD_DWORDS << 3)) > + > +/* Command queue */ > +#define CMDQ_ENT_SZ_SHIFT 4 > +#define CMDQ_ENT_DWORDS ((1 << CMDQ_ENT_SZ_SHIFT) >> 3) > +#define CMDQ_MAX_SZ_SHIFT (Q_MAX_SZ_SHIFT - CMDQ_ENT_SZ_SHIFT) > + > +#define CMDQ_CONS_ERR GENMASK(30, 24) > +#define CMDQ_ERR_CERROR_NONE_IDX 0 > +#define CMDQ_ERR_CERROR_ILL_IDX 1 > +#define CMDQ_ERR_CERROR_ABT_IDX 2 > +#define CMDQ_ERR_CERROR_ATC_INV_IDX 3 > + > +#define CMDQ_0_OP GENMASK_ULL(7, 0) > +#define CMDQ_0_SSV (1UL << 11) > + > +#define CMDQ_PREFETCH_0_SID GENMASK_ULL(63, 32) > +#define CMDQ_PREFETCH_1_SIZE GENMASK_ULL(4, 0) > +#define CMDQ_PREFETCH_1_ADDR_MASK GENMASK_ULL(63, 12) > + > +#define CMDQ_CFGI_0_SSID GENMASK_ULL(31, 12) > +#define CMDQ_CFGI_0_SID GENMASK_ULL(63, 32) > +#define CMDQ_CFGI_1_LEAF (1UL << 0) > +#define CMDQ_CFGI_1_RANGE GENMASK_ULL(4, 0) > + > +#define CMDQ_TLBI_0_VMID GENMASK_ULL(47, 32) > +#define CMDQ_TLBI_0_ASID GENMASK_ULL(63, 48) > +#define CMDQ_TLBI_1_LEAF (1UL << 0) > +#define CMDQ_TLBI_1_VA_MASK GENMASK_ULL(63, 12) > +#define CMDQ_TLBI_1_IPA_MASK GENMASK_ULL(51, 12) > + > +#define CMDQ_ATC_0_SSID GENMASK_ULL(31, 12) > +#define CMDQ_ATC_0_SID GENMASK_ULL(63, 32) > +#define CMDQ_ATC_0_GLOBAL (1UL << 9) > +#define CMDQ_ATC_1_SIZE GENMASK_ULL(5, 0) > +#define CMDQ_ATC_1_ADDR_MASK GENMASK_ULL(63, 12) > + > +#define CMDQ_PRI_0_SSID GENMASK_ULL(31, 12) > +#define CMDQ_PRI_0_SID GENMASK_ULL(63, 32) > +#define CMDQ_PRI_1_GRPID GENMASK_ULL(8, 0) > +#define CMDQ_PRI_1_RESP GENMASK_ULL(13, 12) > + > +#define CMDQ_SYNC_0_CS GENMASK_ULL(13, 12) > +#define CMDQ_SYNC_0_CS_NONE 0 > +#define CMDQ_SYNC_0_CS_IRQ 1 > +#define CMDQ_SYNC_0_CS_SEV 2 > +#define CMDQ_SYNC_0_MSH GENMASK_ULL(23, 22) > +#define CMDQ_SYNC_0_MSIATTR GENMASK_ULL(27, 24) > +#define CMDQ_SYNC_0_MSIDATA GENMASK_ULL(63, 32) > +#define CMDQ_SYNC_1_MSIADDR_MASK GENMASK_ULL(51, 2) > + > +/* Event queue */ > +#define EVTQ_ENT_SZ_SHIFT 5 > +#define EVTQ_ENT_DWORDS ((1 << EVTQ_ENT_SZ_SHIFT) >> 3) > +#define EVTQ_MAX_SZ_SHIFT (Q_MAX_SZ_SHIFT - EVTQ_ENT_SZ_SHIFT) > + > +#define EVTQ_0_ID GENMASK_ULL(7, 0) > + > +/* PRI queue */ > +#define PRIQ_ENT_SZ_SHIFT 4 > +#define PRIQ_ENT_DWORDS ((1 << PRIQ_ENT_SZ_SHIFT) >> 3) > +#define PRIQ_MAX_SZ_SHIFT (Q_MAX_SZ_SHIFT - PRIQ_ENT_SZ_SHIFT) > + > +#define PRIQ_0_SID GENMASK_ULL(31, 0) > +#define PRIQ_0_SSID GENMASK_ULL(51, 32) > +#define PRIQ_0_PERM_PRIV (1UL << 58) > +#define PRIQ_0_PERM_EXEC (1UL << 59) > +#define PRIQ_0_PERM_READ (1UL << 60) > +#define PRIQ_0_PERM_WRITE (1UL << 61) > +#define PRIQ_0_PRG_LAST (1UL << 62) > +#define PRIQ_0_SSID_V (1UL << 63) > + > +#define PRIQ_1_PRG_IDX GENMASK_ULL(8, 0) > +#define PRIQ_1_ADDR_MASK GENMASK_ULL(63, 12) > + > +/* High-level queue structures */ > +#define ARM_SMMU_POLL_TIMEOUT_US 100 > +#define ARM_SMMU_CMDQ_SYNC_TIMEOUT_US 1000000 /* 1s! */ > +#define ARM_SMMU_CMDQ_SYNC_SPIN_COUNT 10 > + > +#define FIELD_PREP(_mask, _val) \ > + (((typeof(_mask))(_val) << (ffs64(_mask) - 1)) & (_mask)) > + > +#define FIELD_GET(_mask, _reg) \ > + ((typeof(_mask))(((_reg) & (_mask)) >> (ffs64(_mask) - 1))) > + > +/* Linux compatibility functions. */ > +typedef paddr_t dma_addr_t; > +typedef paddr_t phys_addr_t; > +typedef unsigned int gfp_t; > + > +/* Alias to Xen lock functions */ > +#define mutex spinlock > +#define mutex_init spin_lock_init > +#define mutex_lock spin_lock > +#define mutex_unlock spin_unlock > + > +/* SMMU private data for an IOMMU domain */ > +enum arm_smmu_domain_stage { > + ARM_SMMU_DOMAIN_S1 = 0, > + ARM_SMMU_DOMAIN_S2, > + ARM_SMMU_DOMAIN_NESTED, > + ARM_SMMU_DOMAIN_BYPASS, > +}; > + > +/* Xen specific code. */ > +struct iommu_domain { > + /* Runtime SMMU configuration for this iommu_domain */ > + atomic_t ref; > + /* > + * Used to link iommu_domain contexts for a same domain. > + * There is at least one per-SMMU to used by the domain. > + */ > + struct list_head list; > +}; > + > +/* Describes information required for a Xen domain */ > +struct arm_smmu_xen_domain { > + spinlock_t lock; > + > + /* List of iommu domains associated to this domain */ > + struct list_head contexts; > +}; > + > +enum pri_resp { > + PRI_RESP_DENY = 0, > + PRI_RESP_FAIL = 1, > + PRI_RESP_SUCC = 2, > +}; > + > +#ifdef CONFIG_MSI > +enum arm_smmu_msi_index { > + EVTQ_MSI_INDEX, > + GERROR_MSI_INDEX, > + PRIQ_MSI_INDEX, > + ARM_SMMU_MAX_MSIS, > +}; > + > +static phys_addr_t arm_smmu_msi_cfg[ARM_SMMU_MAX_MSIS][3] = { > + [EVTQ_MSI_INDEX] = { > + ARM_SMMU_EVTQ_IRQ_CFG0, > + ARM_SMMU_EVTQ_IRQ_CFG1, > + ARM_SMMU_EVTQ_IRQ_CFG2, > + }, > + [GERROR_MSI_INDEX] = { > + ARM_SMMU_GERROR_IRQ_CFG0, > + ARM_SMMU_GERROR_IRQ_CFG1, > + ARM_SMMU_GERROR_IRQ_CFG2, > + }, > + [PRIQ_MSI_INDEX] = { > + ARM_SMMU_PRIQ_IRQ_CFG0, > + ARM_SMMU_PRIQ_IRQ_CFG1, > + ARM_SMMU_PRIQ_IRQ_CFG2, > + }, > +}; > +#endif /* CONFIG_MSI */ > + > +struct arm_smmu_cmdq_ent { > + /* Common fields */ > + u8 opcode; > + bool substream_valid; > + > + /* Command-specific fields */ > + union { > + #define CMDQ_OP_PREFETCH_CFG 0x1 > + struct { > + u32 sid; > + u8 size; > + u64 addr; > + } prefetch; > + > + #define CMDQ_OP_CFGI_STE 0x3 > + #define CMDQ_OP_CFGI_ALL 0x4 > + struct { > + u32 sid; > + union { > + bool leaf; > + u8 span; > + }; > + } cfgi; > + > + #define CMDQ_OP_TLBI_EL2_ALL 0x20 > + #define CMDQ_OP_TLBI_S12_VMALL 0x28 > + #define CMDQ_OP_TLBI_S2_IPA 0x2a > + #define CMDQ_OP_TLBI_NSNH_ALL 0x30 > + struct { > + u16 asid; > + u16 vmid; > + bool leaf; > + u64 addr; > + } tlbi; > + > + #define CMDQ_OP_ATC_INV 0x40 > + #define ATC_INV_SIZE_ALL 52 > + struct { > + u32 sid; > + u32 ssid; > + u64 addr; > + u8 size; > + bool global; > + } atc; > + > + #define CMDQ_OP_PRI_RESP 0x41 > + struct { > + u32 sid; > + u32 ssid; > + u16 grpid; > + enum pri_resp resp; > + } pri; > + > + #define CMDQ_OP_CMD_SYNC 0x46 > + struct { > + u32 msidata; > + u64 msiaddr; > + } sync; > + }; > +}; > + > +struct arm_smmu_ll_queue { > + u32 prod; > + u32 cons; > + u32 max_n_shift; > +}; > + > +struct arm_smmu_queue { > + struct arm_smmu_ll_queue llq; > + int irq; /* Wired interrupt */ > + > + __le64 *base; > + dma_addr_t base_dma; > + u64 q_base; > + > + size_t ent_dwords; > + > + u32 __iomem *prod_reg; > + u32 __iomem *cons_reg; > +}; > + > +struct arm_smmu_cmdq { > + struct arm_smmu_queue q; > + spinlock_t lock; > +}; > + > +struct arm_smmu_evtq { > + struct arm_smmu_queue q; > + u32 max_stalls; > +}; > + > +struct arm_smmu_priq { > + struct arm_smmu_queue q; > +}; > + > +/* High-level stream table and context descriptor structures */ > +struct arm_smmu_strtab_l1_desc { > + u8 span; > + > + __le64 *l2ptr; > + dma_addr_t l2ptr_dma; > +}; > + > +struct arm_smmu_s2_cfg { > + u16 vmid; > + u64 vttbr; > + u64 vtcr; > +}; > + > +struct arm_smmu_strtab_cfg { > + __le64 *strtab; > + dma_addr_t strtab_dma; > + struct arm_smmu_strtab_l1_desc *l1_desc; > + unsigned int num_l1_ents; > + > + u64 strtab_base; > + u32 strtab_base_cfg; > +}; > + > +struct arm_lpae_s2_cfg { > + u64 vttbr; > + struct { > + u32 ps:3; > + u32 tg:2; > + u32 sh:2; > + u32 orgn:2; > + u32 irgn:2; > + u32 sl:2; > + u32 tsz:6; > + } vtcr; > +}; > + > +/* An SMMUv3 instance */ > +struct arm_smmu_device { > + struct device *dev; > + void __iomem *base; > + void __iomem *page1; > + > +#define ARM_SMMU_FEAT_2_LVL_STRTAB (1 << 0) > +#define ARM_SMMU_FEAT_2_LVL_CDTAB (1 << 1) > +#define ARM_SMMU_FEAT_TT_LE (1 << 2) > +#define ARM_SMMU_FEAT_TT_BE (1 << 3) > +#define ARM_SMMU_FEAT_PRI (1 << 4) > +#define ARM_SMMU_FEAT_ATS (1 << 5) > +#define ARM_SMMU_FEAT_SEV (1 << 6) > +#define ARM_SMMU_FEAT_MSI (1 << 7) > +#define ARM_SMMU_FEAT_COHERENCY (1 << 8) > +#define ARM_SMMU_FEAT_TRANS_S1 (1 << 9) > +#define ARM_SMMU_FEAT_TRANS_S2 (1 << 10) > +#define ARM_SMMU_FEAT_STALLS (1 << 11) > +#define ARM_SMMU_FEAT_HYP (1 << 12) > +#define ARM_SMMU_FEAT_STALL_FORCE (1 << 13) > +#define ARM_SMMU_FEAT_VAX (1 << 14) > + u32 features; > + > +#define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) > +#define ARM_SMMU_OPT_PAGE0_REGS_ONLY (1 << 1) > + u32 options; > + > + struct arm_smmu_cmdq cmdq; > + struct arm_smmu_evtq evtq; > + struct arm_smmu_priq priq; > + > + int gerr_irq; > + int combined_irq; > + u32 sync_nr; > + u8 prev_cmd_opcode; > + > + unsigned long ias; /* IPA */ > + unsigned long oas; /* PA */ > + unsigned long pgsize_bitmap; > + > +#define ARM_SMMU_MAX_VMIDS (1 << 16) > + unsigned int vmid_bits; > + DECLARE_BITMAP(vmid_map, ARM_SMMU_MAX_VMIDS); > + > + unsigned int sid_bits; > + > + struct arm_smmu_strtab_cfg strtab_cfg; > + > + /* Hi16xx adds an extra 32 bits of goodness to its MSI payload */ > + union { > + u32 sync_count; > + u64 padding; > + }; > + > + /* Need to keep a list of SMMU devices */ > + struct list_head devices; > + > + /* Tasklets for handling evts/faults and pci page request IRQs*/ > + struct tasklet evtq_irq_tasklet; > + struct tasklet priq_irq_tasklet; > + struct tasklet combined_irq_tasklet; > +}; > + > +/* SMMU private data for each master */ > +struct arm_smmu_master { > + struct arm_smmu_device *smmu; > + struct device *dev; > + struct arm_smmu_domain *domain; > + struct list_head domain_head; > + u32 *sids; > + unsigned int num_sids; > + bool ats_enabled; > +}; > + > +struct arm_smmu_domain { > + struct arm_smmu_device *smmu; > + struct mutex init_mutex; /* Protects smmu pointer */ > + > + bool non_strict; > + atomic_t nr_ats_masters; > + > + enum arm_smmu_domain_stage stage; > + struct arm_smmu_s2_cfg s2_cfg; > + > + /* Xen domain associated with this SMMU domain */ > + struct domain *d; > + > + struct iommu_domain domain; > + > + struct list_head devices; > + spinlock_t devices_lock; > +}; > + > +#endif /* _ARM_SMMU_V3_H */ > -- > 2.25.1 > ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v3 05/10] xen/arm: smmuv3: Remove the page 1 fixup 2022-09-05 16:30 [PATCH v3 00/10] xen/arm: smmuv3: Merge Linux fixes to Xen Rahul Singh ` (3 preceding siblings ...) 2022-09-05 16:30 ` [PATCH v3 04/10] xen/arm: smmuv3: Move definitions to a header Rahul Singh @ 2022-09-05 16:30 ` Rahul Singh 2022-09-05 22:19 ` Stefano Stabellini 2022-09-05 16:30 ` [PATCH v3 06/10] xen/arm: smmuv3: Remove the unused fields for PREFETCH_CONFIG command Rahul Singh ` (4 subsequent siblings) 9 siblings, 1 reply; 17+ messages in thread From: Rahul Singh @ 2022-09-05 16:30 UTC (permalink / raw) To: xen-devel Cc: Robin Murphy, Bertrand Marquis, Stefano Stabellini, Julien Grall, Volodymyr Babchuk, Will Deacon From: Robin Murphy <robin.murphy@arm.com> Backport Linux commit 86d2d9214880. This is the clean backport without any changes. Since we now keep track of page 1 via a separate pointer that already encapsulates aliasing to page 0 as necessary, we can remove the clunky fixup routine and simply use the relevant bases directly. The current architecture spec (IHI0070D.a) defines SMMU_{EVENTQ,PRIQ}_{PROD,CONS} as offsets relative to page 1, so the cleanup represents a little bit of convergence as well as just lines of code saved. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will@kernel.org> Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 86d2d9214880 Signed-off-by: Rahul Singh <rahul.singh@arm.com> --- Changes in v3: - fix "q->cons_reg = page + cons_off" Changes in v2: - fix commit msg. --- xen/drivers/passthrough/arm/smmu-v3.c | 42 ++++++++++----------------- xen/drivers/passthrough/arm/smmu-v3.h | 8 ++--- 2 files changed, 20 insertions(+), 30 deletions(-) diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthrough/arm/smmu-v3.c index e65b226b85..272adebb0b 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.c +++ b/xen/drivers/passthrough/arm/smmu-v3.c @@ -238,15 +238,6 @@ static struct arm_smmu_option_prop arm_smmu_options[] = { { 0, NULL}, }; -static inline void __iomem *arm_smmu_page1_fixup(unsigned long offset, - struct arm_smmu_device *smmu) -{ - if (offset > SZ_64K) - return smmu->page1 + offset - SZ_64K; - - return smmu->base + offset; -} - static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom) { return container_of(dom, struct arm_smmu_domain, domain); @@ -1581,6 +1572,7 @@ static int arm_smmu_dt_xlate(struct device *dev, /* Probing and initialisation functions */ static int arm_smmu_init_one_queue(struct arm_smmu_device *smmu, struct arm_smmu_queue *q, + void __iomem *page, unsigned long prod_off, unsigned long cons_off, size_t dwords, const char *name) @@ -1609,8 +1601,8 @@ static int arm_smmu_init_one_queue(struct arm_smmu_device *smmu, 1 << q->llq.max_n_shift, name); } - q->prod_reg = arm_smmu_page1_fixup(prod_off, smmu); - q->cons_reg = arm_smmu_page1_fixup(cons_off, smmu); + q->prod_reg = page + prod_off; + q->cons_reg = page + cons_off; q->ent_dwords = dwords; q->q_base = Q_BASE_RWA; @@ -1627,16 +1619,16 @@ static int arm_smmu_init_queues(struct arm_smmu_device *smmu) /* cmdq */ spin_lock_init(&smmu->cmdq.lock); - ret = arm_smmu_init_one_queue(smmu, &smmu->cmdq.q, ARM_SMMU_CMDQ_PROD, - ARM_SMMU_CMDQ_CONS, CMDQ_ENT_DWORDS, - "cmdq"); + ret = arm_smmu_init_one_queue(smmu, &smmu->cmdq.q, smmu->base, + ARM_SMMU_CMDQ_PROD, ARM_SMMU_CMDQ_CONS, + CMDQ_ENT_DWORDS, "cmdq"); if (ret) return ret; /* evtq */ - ret = arm_smmu_init_one_queue(smmu, &smmu->evtq.q, ARM_SMMU_EVTQ_PROD, - ARM_SMMU_EVTQ_CONS, EVTQ_ENT_DWORDS, - "evtq"); + ret = arm_smmu_init_one_queue(smmu, &smmu->evtq.q, smmu->page1, + ARM_SMMU_EVTQ_PROD, ARM_SMMU_EVTQ_CONS, + EVTQ_ENT_DWORDS, "evtq"); if (ret) return ret; @@ -1644,9 +1636,9 @@ static int arm_smmu_init_queues(struct arm_smmu_device *smmu) if (!(smmu->features & ARM_SMMU_FEAT_PRI)) return 0; - return arm_smmu_init_one_queue(smmu, &smmu->priq.q, ARM_SMMU_PRIQ_PROD, - ARM_SMMU_PRIQ_CONS, PRIQ_ENT_DWORDS, - "priq"); + return arm_smmu_init_one_queue(smmu, &smmu->priq.q, smmu->page1, + ARM_SMMU_PRIQ_PROD, ARM_SMMU_PRIQ_CONS, + PRIQ_ENT_DWORDS, "priq"); } static int arm_smmu_init_l1_strtab(struct arm_smmu_device *smmu) @@ -2090,10 +2082,8 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu) /* Event queue */ writeq_relaxed(smmu->evtq.q.q_base, smmu->base + ARM_SMMU_EVTQ_BASE); - writel_relaxed(smmu->evtq.q.llq.prod, - arm_smmu_page1_fixup(ARM_SMMU_EVTQ_PROD, smmu)); - writel_relaxed(smmu->evtq.q.llq.cons, - arm_smmu_page1_fixup(ARM_SMMU_EVTQ_CONS, smmu)); + writel_relaxed(smmu->evtq.q.llq.prod, smmu->page1 + ARM_SMMU_EVTQ_PROD); + writel_relaxed(smmu->evtq.q.llq.cons, smmu->page1 + ARM_SMMU_EVTQ_CONS); enables |= CR0_EVTQEN; ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, @@ -2108,9 +2098,9 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu) writeq_relaxed(smmu->priq.q.q_base, smmu->base + ARM_SMMU_PRIQ_BASE); writel_relaxed(smmu->priq.q.llq.prod, - arm_smmu_page1_fixup(ARM_SMMU_PRIQ_PROD, smmu)); + smmu->page1 + ARM_SMMU_PRIQ_PROD); writel_relaxed(smmu->priq.q.llq.cons, - arm_smmu_page1_fixup(ARM_SMMU_PRIQ_CONS, smmu)); + smmu->page1 + ARM_SMMU_PRIQ_CONS); enables |= CR0_PRIQEN; ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, diff --git a/xen/drivers/passthrough/arm/smmu-v3.h b/xen/drivers/passthrough/arm/smmu-v3.h index c45d2f16c4..0742bc393f 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.h +++ b/xen/drivers/passthrough/arm/smmu-v3.h @@ -130,15 +130,15 @@ #define ARM_SMMU_CMDQ_CONS 0x9c #define ARM_SMMU_EVTQ_BASE 0xa0 -#define ARM_SMMU_EVTQ_PROD 0x100a8 -#define ARM_SMMU_EVTQ_CONS 0x100ac +#define ARM_SMMU_EVTQ_PROD 0xa8 +#define ARM_SMMU_EVTQ_CONS 0xac #define ARM_SMMU_EVTQ_IRQ_CFG0 0xb0 #define ARM_SMMU_EVTQ_IRQ_CFG1 0xb8 #define ARM_SMMU_EVTQ_IRQ_CFG2 0xbc #define ARM_SMMU_PRIQ_BASE 0xc0 -#define ARM_SMMU_PRIQ_PROD 0x100c8 -#define ARM_SMMU_PRIQ_CONS 0x100cc +#define ARM_SMMU_PRIQ_PROD 0xc8 +#define ARM_SMMU_PRIQ_CONS 0xcc #define ARM_SMMU_PRIQ_IRQ_CFG0 0xd0 #define ARM_SMMU_PRIQ_IRQ_CFG1 0xd8 #define ARM_SMMU_PRIQ_IRQ_CFG2 0xdc -- 2.25.1 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH v3 05/10] xen/arm: smmuv3: Remove the page 1 fixup 2022-09-05 16:30 ` [PATCH v3 05/10] xen/arm: smmuv3: Remove the page 1 fixup Rahul Singh @ 2022-09-05 22:19 ` Stefano Stabellini 0 siblings, 0 replies; 17+ messages in thread From: Stefano Stabellini @ 2022-09-05 22:19 UTC (permalink / raw) To: Rahul Singh Cc: xen-devel, Robin Murphy, Bertrand Marquis, Stefano Stabellini, Julien Grall, Volodymyr Babchuk, Will Deacon On Mon, 5 Sep 2022, Rahul Singh wrote: > From: Robin Murphy <robin.murphy@arm.com> > > Backport Linux commit 86d2d9214880. This is the clean backport without > any changes. > > Since we now keep track of page 1 via a separate pointer that > already encapsulates aliasing to page 0 as necessary, we can remove > the clunky fixup routine and simply use the relevant bases directly. > The current architecture spec (IHI0070D.a) defines > SMMU_{EVENTQ,PRIQ}_{PROD,CONS} as offsets relative to page 1, so the > cleanup represents a little bit of convergence as well as just > lines of code saved. > > Signed-off-by: Robin Murphy <robin.murphy@arm.com> > Signed-off-by: Will Deacon <will@kernel.org> > Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 86d2d9214880 > Signed-off-by: Rahul Singh <rahul.singh@arm.com> Acked-by: Stefano Stabellini <sstabellini@kernel.org> > --- > Changes in v3: > - fix "q->cons_reg = page + cons_off" > Changes in v2: > - fix commit msg. > --- > xen/drivers/passthrough/arm/smmu-v3.c | 42 ++++++++++----------------- > xen/drivers/passthrough/arm/smmu-v3.h | 8 ++--- > 2 files changed, 20 insertions(+), 30 deletions(-) > > diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthrough/arm/smmu-v3.c > index e65b226b85..272adebb0b 100644 > --- a/xen/drivers/passthrough/arm/smmu-v3.c > +++ b/xen/drivers/passthrough/arm/smmu-v3.c > @@ -238,15 +238,6 @@ static struct arm_smmu_option_prop arm_smmu_options[] = { > { 0, NULL}, > }; > > -static inline void __iomem *arm_smmu_page1_fixup(unsigned long offset, > - struct arm_smmu_device *smmu) > -{ > - if (offset > SZ_64K) > - return smmu->page1 + offset - SZ_64K; > - > - return smmu->base + offset; > -} > - > static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom) > { > return container_of(dom, struct arm_smmu_domain, domain); > @@ -1581,6 +1572,7 @@ static int arm_smmu_dt_xlate(struct device *dev, > /* Probing and initialisation functions */ > static int arm_smmu_init_one_queue(struct arm_smmu_device *smmu, > struct arm_smmu_queue *q, > + void __iomem *page, > unsigned long prod_off, > unsigned long cons_off, > size_t dwords, const char *name) > @@ -1609,8 +1601,8 @@ static int arm_smmu_init_one_queue(struct arm_smmu_device *smmu, > 1 << q->llq.max_n_shift, name); > } > > - q->prod_reg = arm_smmu_page1_fixup(prod_off, smmu); > - q->cons_reg = arm_smmu_page1_fixup(cons_off, smmu); > + q->prod_reg = page + prod_off; > + q->cons_reg = page + cons_off; > q->ent_dwords = dwords; > > q->q_base = Q_BASE_RWA; > @@ -1627,16 +1619,16 @@ static int arm_smmu_init_queues(struct arm_smmu_device *smmu) > > /* cmdq */ > spin_lock_init(&smmu->cmdq.lock); > - ret = arm_smmu_init_one_queue(smmu, &smmu->cmdq.q, ARM_SMMU_CMDQ_PROD, > - ARM_SMMU_CMDQ_CONS, CMDQ_ENT_DWORDS, > - "cmdq"); > + ret = arm_smmu_init_one_queue(smmu, &smmu->cmdq.q, smmu->base, > + ARM_SMMU_CMDQ_PROD, ARM_SMMU_CMDQ_CONS, > + CMDQ_ENT_DWORDS, "cmdq"); > if (ret) > return ret; > > /* evtq */ > - ret = arm_smmu_init_one_queue(smmu, &smmu->evtq.q, ARM_SMMU_EVTQ_PROD, > - ARM_SMMU_EVTQ_CONS, EVTQ_ENT_DWORDS, > - "evtq"); > + ret = arm_smmu_init_one_queue(smmu, &smmu->evtq.q, smmu->page1, > + ARM_SMMU_EVTQ_PROD, ARM_SMMU_EVTQ_CONS, > + EVTQ_ENT_DWORDS, "evtq"); > if (ret) > return ret; > > @@ -1644,9 +1636,9 @@ static int arm_smmu_init_queues(struct arm_smmu_device *smmu) > if (!(smmu->features & ARM_SMMU_FEAT_PRI)) > return 0; > > - return arm_smmu_init_one_queue(smmu, &smmu->priq.q, ARM_SMMU_PRIQ_PROD, > - ARM_SMMU_PRIQ_CONS, PRIQ_ENT_DWORDS, > - "priq"); > + return arm_smmu_init_one_queue(smmu, &smmu->priq.q, smmu->page1, > + ARM_SMMU_PRIQ_PROD, ARM_SMMU_PRIQ_CONS, > + PRIQ_ENT_DWORDS, "priq"); > } > > static int arm_smmu_init_l1_strtab(struct arm_smmu_device *smmu) > @@ -2090,10 +2082,8 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu) > > /* Event queue */ > writeq_relaxed(smmu->evtq.q.q_base, smmu->base + ARM_SMMU_EVTQ_BASE); > - writel_relaxed(smmu->evtq.q.llq.prod, > - arm_smmu_page1_fixup(ARM_SMMU_EVTQ_PROD, smmu)); > - writel_relaxed(smmu->evtq.q.llq.cons, > - arm_smmu_page1_fixup(ARM_SMMU_EVTQ_CONS, smmu)); > + writel_relaxed(smmu->evtq.q.llq.prod, smmu->page1 + ARM_SMMU_EVTQ_PROD); > + writel_relaxed(smmu->evtq.q.llq.cons, smmu->page1 + ARM_SMMU_EVTQ_CONS); > > enables |= CR0_EVTQEN; > ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, > @@ -2108,9 +2098,9 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu) > writeq_relaxed(smmu->priq.q.q_base, > smmu->base + ARM_SMMU_PRIQ_BASE); > writel_relaxed(smmu->priq.q.llq.prod, > - arm_smmu_page1_fixup(ARM_SMMU_PRIQ_PROD, smmu)); > + smmu->page1 + ARM_SMMU_PRIQ_PROD); > writel_relaxed(smmu->priq.q.llq.cons, > - arm_smmu_page1_fixup(ARM_SMMU_PRIQ_CONS, smmu)); > + smmu->page1 + ARM_SMMU_PRIQ_CONS); > > enables |= CR0_PRIQEN; > ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, > diff --git a/xen/drivers/passthrough/arm/smmu-v3.h b/xen/drivers/passthrough/arm/smmu-v3.h > index c45d2f16c4..0742bc393f 100644 > --- a/xen/drivers/passthrough/arm/smmu-v3.h > +++ b/xen/drivers/passthrough/arm/smmu-v3.h > @@ -130,15 +130,15 @@ > #define ARM_SMMU_CMDQ_CONS 0x9c > > #define ARM_SMMU_EVTQ_BASE 0xa0 > -#define ARM_SMMU_EVTQ_PROD 0x100a8 > -#define ARM_SMMU_EVTQ_CONS 0x100ac > +#define ARM_SMMU_EVTQ_PROD 0xa8 > +#define ARM_SMMU_EVTQ_CONS 0xac > #define ARM_SMMU_EVTQ_IRQ_CFG0 0xb0 > #define ARM_SMMU_EVTQ_IRQ_CFG1 0xb8 > #define ARM_SMMU_EVTQ_IRQ_CFG2 0xbc > > #define ARM_SMMU_PRIQ_BASE 0xc0 > -#define ARM_SMMU_PRIQ_PROD 0x100c8 > -#define ARM_SMMU_PRIQ_CONS 0x100cc > +#define ARM_SMMU_PRIQ_PROD 0xc8 > +#define ARM_SMMU_PRIQ_CONS 0xcc > #define ARM_SMMU_PRIQ_IRQ_CFG0 0xd0 > #define ARM_SMMU_PRIQ_IRQ_CFG1 0xd8 > #define ARM_SMMU_PRIQ_IRQ_CFG2 0xdc > -- > 2.25.1 > ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v3 06/10] xen/arm: smmuv3: Remove the unused fields for PREFETCH_CONFIG command 2022-09-05 16:30 [PATCH v3 00/10] xen/arm: smmuv3: Merge Linux fixes to Xen Rahul Singh ` (4 preceding siblings ...) 2022-09-05 16:30 ` [PATCH v3 05/10] xen/arm: smmuv3: Remove the page 1 fixup Rahul Singh @ 2022-09-05 16:30 ` Rahul Singh 2022-09-05 16:30 ` [PATCH v3 07/10] xen/arm: smmuv3: Change *array into *const array Rahul Singh ` (3 subsequent siblings) 9 siblings, 0 replies; 17+ messages in thread From: Rahul Singh @ 2022-09-05 16:30 UTC (permalink / raw) To: xen-devel Cc: Zenghui Yu, Bertrand Marquis, Stefano Stabellini, Julien Grall, Volodymyr Babchuk, Will Deacon From: Zenghui Yu <yuzenghui@huawei.com> Backport Linux commit e0bb4b735404. This is the clean backport without any changes. Per SMMUv3 spec, there is no Size and Addr field in the PREFETCH_CONFIG command and they're not used by the driver. Remove them. We can add them back if we're going to use PREFETCH_ADDR in the future. Signed-off-by: Zenghui Yu <yuzenghui@huawei.com> Link: https://lore.kernel.org/r/20210407084448.1838-1-yuzenghui@huawei.com Signed-off-by: Will Deacon <will@kernel.org> Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git e0bb4b735404 Acked-by: Stefano Stabellini <sstabellini@kernel.org> Signed-off-by: Rahul Singh <rahul.singh@arm.com> --- Changes in v3: - Added Stefano Acked-by Changes in v2: - fix commit msg --- --- xen/drivers/passthrough/arm/smmu-v3.c | 2 -- xen/drivers/passthrough/arm/smmu-v3.h | 2 -- 2 files changed, 4 deletions(-) diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthrough/arm/smmu-v3.c index 272adebb0b..512a3617a2 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.c +++ b/xen/drivers/passthrough/arm/smmu-v3.c @@ -405,8 +405,6 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) break; case CMDQ_OP_PREFETCH_CFG: cmd[0] |= FIELD_PREP(CMDQ_PREFETCH_0_SID, ent->prefetch.sid); - cmd[1] |= FIELD_PREP(CMDQ_PREFETCH_1_SIZE, ent->prefetch.size); - cmd[1] |= ent->prefetch.addr & CMDQ_PREFETCH_1_ADDR_MASK; break; case CMDQ_OP_CFGI_STE: cmd[0] |= FIELD_PREP(CMDQ_CFGI_0_SID, ent->cfgi.sid); diff --git a/xen/drivers/passthrough/arm/smmu-v3.h b/xen/drivers/passthrough/arm/smmu-v3.h index 0742bc393f..b381ad3738 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.h +++ b/xen/drivers/passthrough/arm/smmu-v3.h @@ -456,8 +456,6 @@ struct arm_smmu_cmdq_ent { #define CMDQ_OP_PREFETCH_CFG 0x1 struct { u32 sid; - u8 size; - u64 addr; } prefetch; #define CMDQ_OP_CFGI_STE 0x3 -- 2.25.1 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v3 07/10] xen/arm: smmuv3: Change *array into *const array 2022-09-05 16:30 [PATCH v3 00/10] xen/arm: smmuv3: Merge Linux fixes to Xen Rahul Singh ` (5 preceding siblings ...) 2022-09-05 16:30 ` [PATCH v3 06/10] xen/arm: smmuv3: Remove the unused fields for PREFETCH_CONFIG command Rahul Singh @ 2022-09-05 16:30 ` Rahul Singh 2022-09-05 16:30 ` [PATCH v3 08/10] xen/arm: smmuv3: Remove unnecessary oom message Rahul Singh ` (2 subsequent siblings) 9 siblings, 0 replies; 17+ messages in thread From: Rahul Singh @ 2022-09-05 16:30 UTC (permalink / raw) To: xen-devel Cc: Bixuan Cui, Bertrand Marquis, Stefano Stabellini, Julien Grall, Volodymyr Babchuk, Will Deacon From: Bixuan Cui <cuibixuan@huawei.com> Backport Linux commit d56d5162e317. This is the clean backport without any changes. Fix checkpatch warning in arm-smmu-v3.c: static const char * array should probably be static const char * const Signed-off-by: Bixuan Cui <cuibixuan@huawei.com> Signed-off-by: Will Deacon <will@kernel.org> Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git d56d5162e317 Acked-by: Stefano Stabellini <sstabellini@kernel.org> Signed-off-by: Rahul Singh <rahul.singh@arm.com> --- Changes in v3: - Added Stefano Acked-by Changes in v2: - fix commit msg --- xen/drivers/passthrough/arm/smmu-v3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthrough/arm/smmu-v3.c index 512a3617a2..ef1604d863 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.c +++ b/xen/drivers/passthrough/arm/smmu-v3.c @@ -470,7 +470,7 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) static void arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu) { - static const char *cerror_str[] = { + static const char * const cerror_str[] = { [CMDQ_ERR_CERROR_NONE_IDX] = "No error", [CMDQ_ERR_CERROR_ILL_IDX] = "Illegal command", [CMDQ_ERR_CERROR_ABT_IDX] = "Abort on command fetch", -- 2.25.1 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v3 08/10] xen/arm: smmuv3: Remove unnecessary oom message 2022-09-05 16:30 [PATCH v3 00/10] xen/arm: smmuv3: Merge Linux fixes to Xen Rahul Singh ` (6 preceding siblings ...) 2022-09-05 16:30 ` [PATCH v3 07/10] xen/arm: smmuv3: Change *array into *const array Rahul Singh @ 2022-09-05 16:30 ` Rahul Singh 2022-09-05 16:30 ` [PATCH v3 09/10] xen/arm: smmuv3: Fix fall-through warning for Clang Rahul Singh 2022-09-05 16:30 ` [PATCH v3 10/10] xen/arm: smmuv3: Avoid open coded arithmetic in memory allocation Rahul Singh 9 siblings, 0 replies; 17+ messages in thread From: Rahul Singh @ 2022-09-05 16:30 UTC (permalink / raw) To: xen-devel Cc: Zhen Lei, Bertrand Marquis, Stefano Stabellini, Julien Grall, Volodymyr Babchuk, Will Deacon From: Zhen Lei <thunder.leizhen@huawei.com> Backport Linux commit affa909571b0. This is the clean backport without any changes. Fixes scripts/checkpatch.pl warning: WARNING: Possible unnecessary 'out of memory' message Remove it can help us save a bit of memory. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Link: https://lore.kernel.org/r/20210609125438.14369-1-thunder.leizhen@huawei.com Signed-off-by: Will Deacon <will@kernel.org> Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git affa909571b0 Acked-by: Stefano Stabellini <sstabellini@kernel.org> Signed-off-by: Rahul Singh <rahul.singh@arm.com> --- Changes in v3: - Added Stefano Acked-by Changes in v2: - fix commit msg --- --- xen/drivers/passthrough/arm/smmu-v3.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthrough/arm/smmu-v3.c index ef1604d863..6f551cfede 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.c +++ b/xen/drivers/passthrough/arm/smmu-v3.c @@ -1647,10 +1647,8 @@ static int arm_smmu_init_l1_strtab(struct arm_smmu_device *smmu) void *strtab = smmu->strtab_cfg.strtab; cfg->l1_desc = _xzalloc(size, sizeof(void *)); - if (!cfg->l1_desc) { - dev_err(smmu->dev, "failed to allocate l1 stream table desc\n"); + if (!cfg->l1_desc) return -ENOMEM; - } for (i = 0; i < cfg->num_l1_ents; ++i) { arm_smmu_write_strtab_l1_desc(strtab, &cfg->l1_desc[i]); @@ -2435,10 +2433,8 @@ static int arm_smmu_device_probe(struct platform_device *pdev) struct arm_smmu_device *smmu; smmu = xzalloc(struct arm_smmu_device); - if (!smmu) { - dev_err(pdev, "failed to allocate arm_smmu_device\n"); + if (!smmu) return -ENOMEM; - } smmu->dev = pdev; if (pdev->of_node) { -- 2.25.1 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v3 09/10] xen/arm: smmuv3: Fix fall-through warning for Clang 2022-09-05 16:30 [PATCH v3 00/10] xen/arm: smmuv3: Merge Linux fixes to Xen Rahul Singh ` (7 preceding siblings ...) 2022-09-05 16:30 ` [PATCH v3 08/10] xen/arm: smmuv3: Remove unnecessary oom message Rahul Singh @ 2022-09-05 16:30 ` Rahul Singh 2022-09-05 16:30 ` [PATCH v3 10/10] xen/arm: smmuv3: Avoid open coded arithmetic in memory allocation Rahul Singh 9 siblings, 0 replies; 17+ messages in thread From: Rahul Singh @ 2022-09-05 16:30 UTC (permalink / raw) To: xen-devel Cc: Gustavo A. R. Silva, Bertrand Marquis, Stefano Stabellini, Julien Grall, Volodymyr Babchuk, kernel test robot From: "Gustavo A. R. Silva" <gustavoars@kernel.org> Backport Linux commit 5a1ab5c0299a. This is the clean backport without any changes. Fix the following fallthrough warning (arm64-randconfig with Clang): drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c:382:2: warning: unannotated fall-through between switch labels [-Wimplicit-fallthrough] Reported-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/lkml/60edca25.k00ut905IFBjPyt5%25lkp@intel.com/ Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org> Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 5a1ab5c0299a Acked-by: Stefano Stabellini <sstabellini@kernel.org> Signed-off-by: Rahul Singh <rahul.singh@arm.com> --- Changes in v3: - Added Stefano Acked-by. Changes in v2: - fix commit msg. --- xen/drivers/passthrough/arm/smmu-v3.c | 1 + 1 file changed, 1 insertion(+) diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthrough/arm/smmu-v3.c index 6f551cfede..e8f2f2dbe1 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.c +++ b/xen/drivers/passthrough/arm/smmu-v3.c @@ -492,6 +492,7 @@ static void arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu) switch (idx) { case CMDQ_ERR_CERROR_ABT_IDX: dev_err(smmu->dev, "retrying command fetch\n"); + return; case CMDQ_ERR_CERROR_NONE_IDX: return; case CMDQ_ERR_CERROR_ATC_INV_IDX: -- 2.25.1 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v3 10/10] xen/arm: smmuv3: Avoid open coded arithmetic in memory allocation 2022-09-05 16:30 [PATCH v3 00/10] xen/arm: smmuv3: Merge Linux fixes to Xen Rahul Singh ` (8 preceding siblings ...) 2022-09-05 16:30 ` [PATCH v3 09/10] xen/arm: smmuv3: Fix fall-through warning for Clang Rahul Singh @ 2022-09-05 16:30 ` Rahul Singh 9 siblings, 0 replies; 17+ messages in thread From: Rahul Singh @ 2022-09-05 16:30 UTC (permalink / raw) To: xen-devel Cc: Christophe JAILLET, Bertrand Marquis, Stefano Stabellini, Julien Grall, Volodymyr Babchuk, Robin Murphy, Will Deacon From: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Backport Linux commit 98b64741d611. This is the clean backport without any changes kmalloc_array()/kcalloc() should be used to avoid potential overflow when a multiplication is needed to compute the size of the requested memory. So turn a devm_kzalloc()+explicit size computation into an equivalent devm_kcalloc(). Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Acked-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/3f7b9b202c6b6f5edc234ab7af5f208fbf8bc944.1644274051.git.christophe.jaillet@wanadoo.fr Signed-off-by: Will Deacon <will@kernel.org> Origin: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 98b64741d611 Acked-by: Stefano Stabellini <sstabellini@kernel.org> Signed-off-by: Rahul Singh <rahul.singh@arm.com> --- Changes in v3: - Added Stefano Acked-by Changes in v2: - fix commit msg --- --- xen/drivers/passthrough/arm/smmu-v3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthrough/arm/smmu-v3.c index e8f2f2dbe1..a3d5f53137 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.c +++ b/xen/drivers/passthrough/arm/smmu-v3.c @@ -1644,10 +1644,10 @@ static int arm_smmu_init_l1_strtab(struct arm_smmu_device *smmu) { unsigned int i; struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; - size_t size = sizeof(*cfg->l1_desc) * cfg->num_l1_ents; void *strtab = smmu->strtab_cfg.strtab; - cfg->l1_desc = _xzalloc(size, sizeof(void *)); + cfg->l1_desc = _xzalloc_array(sizeof(*cfg->l1_desc), sizeof(void *), + cfg->num_l1_ents); if (!cfg->l1_desc) return -ENOMEM; -- 2.25.1 ^ permalink raw reply related [flat|nested] 17+ messages in thread
end of thread, other threads:[~2022-09-06 7:20 UTC | newest] Thread overview: 17+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-09-05 16:30 [PATCH v3 00/10] xen/arm: smmuv3: Merge Linux fixes to Xen Rahul Singh 2022-09-05 16:30 ` [PATCH v3 01/10] xen/arm: smmuv3: Fix l1 stream table size in the error message Rahul Singh 2022-09-05 16:30 ` [PATCH v3 02/10] xen/arm: smmuv3: Fix endianness annotations Rahul Singh 2022-09-05 16:30 ` [PATCH v3 03/10] xen/arm: smmuv3: Ensure queue is read after updating prod pointer Rahul Singh 2022-09-05 16:37 ` Julien Grall 2022-09-05 16:49 ` Rahul Singh 2022-09-05 16:55 ` Julien Grall 2022-09-06 7:19 ` Bertrand Marquis 2022-09-05 16:30 ` [PATCH v3 04/10] xen/arm: smmuv3: Move definitions to a header Rahul Singh 2022-09-05 22:20 ` Stefano Stabellini 2022-09-05 16:30 ` [PATCH v3 05/10] xen/arm: smmuv3: Remove the page 1 fixup Rahul Singh 2022-09-05 22:19 ` Stefano Stabellini 2022-09-05 16:30 ` [PATCH v3 06/10] xen/arm: smmuv3: Remove the unused fields for PREFETCH_CONFIG command Rahul Singh 2022-09-05 16:30 ` [PATCH v3 07/10] xen/arm: smmuv3: Change *array into *const array Rahul Singh 2022-09-05 16:30 ` [PATCH v3 08/10] xen/arm: smmuv3: Remove unnecessary oom message Rahul Singh 2022-09-05 16:30 ` [PATCH v3 09/10] xen/arm: smmuv3: Fix fall-through warning for Clang Rahul Singh 2022-09-05 16:30 ` [PATCH v3 10/10] xen/arm: smmuv3: Avoid open coded arithmetic in memory allocation Rahul Singh
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