[PATCH 0/5] arm64: dts: renesas: r8a779g0: CPU topology improvements

[Geert Uytterhoeven <geert+renesas@glider.be>]

        Hi all,

Currently, the R-Car V4H DTS describes a single Cortex-A76 CPU core
only.  This patch series completes the description of the Cortex-A76
clusters by describing L3 caches, CPU cores 1-3, CPU map, PSCI for CPU
bring up, CPUIdle, CPU core clocks, and CPU core operating points.

This has been tested on the White-Hawk development board, where now all
4 Cortex-A76 CPU cores are available after boot.  All but the first CPU
core can be controlled from sysfs (/sys/*/*/cpu/cpu[0-3]/online).
CPU core performance follows the CPU core clocks, when changing the
frequency of the latter.

I plan to queue this in renesas-devel for v6.2.

Thanks for your comments!

Geert Uytterhoeven (5):
  arm64: dts: renesas: r8a779g0: Add L3 cache controller
  arm64: dts: renesas: r8a779g0: Add secondary CA76 CPU cores
  arm64: dts: renesas: r8a779g0: Add CPUIdle support
  arm64: dts: renesas: r8a779g0: Add CPU core clocks
  arm64: dts: renesas: r8a779g0: Add CA76 operating points

 arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 130 +++++++++++++++++++++-
 1 file changed, 125 insertions(+), 5 deletions(-)

-- 
2.25.1

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds