From: Nicolin Chen <nicolinc@nvidia.com>
To: <will@kernel.org>, <robin.murphy@arm.com>, <jgg@nvidia.com>
Cc: <joro@8bytes.org>, <jean-philippe@linaro.org>,
<mshavit@google.com>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <iommu@lists.linux.dev>
Subject: [PATCH v4 0/2] iommu/arm-smmu-v3: Allow default substream bypass with a pasid support
Date: Wed, 20 Sep 2023 13:52:02 -0700 [thread overview]
Message-ID: <cover.1695242337.git.nicolinc@nvidia.com> (raw)
(This series is rebased on top of Michael's refactor series [1])
When an iommu_domain is set to IOMMU_DOMAIN_IDENTITY, the driver sets the
arm_smmu_domain->stage to ARM_SMMU_DOMAIN_BYPASS and skips the allocation
of a CD table, and then sets STRTAB_STE_0_CFG_BYPASS to the CONFIG field
of the STE. This works well for devices that only have one substream, i.e.
pasid disabled.
With a pasid-capable device, however, there could be a use case where it
allows an IDENTITY domain attachment without disabling its pasid feature.
This requires the driver to allocate a multi-entry CD table to attach the
IDENTITY domain to its default substream and to configure the S1DSS filed
of the STE to STRTAB_STE_1_S1DSS_BYPASS. So, there is a missing link here
between the STE setup and an IDENTITY domain attachment.
This series fills the gap for the use case above. The first patch corrects
the conditions at ats_enabled capability and arm_smmu_alloc_cd_tables() so
that the use case above could set the ats_enabled and allocate a CD table
correctly. The second patch reworks the arm_smmu_write_strtab_ent() in a
fashion of all possible configurations of STE.Config fields.
[1]
https://lore.kernel.org/all/20230915132051.2646055-1-mshavit@google.com/
---
Changelog
v4:
* Rebased on top of v6.6-rc2 and Michael's refactor series v8 [1]
v3: https://lore.kernel.org/all/cover.1692959239.git.nicolinc@nvidia.com/
* Replaced ARM_SMMU_DOMAIN_BYPASS_S1DSS with two boolean flags to correct
conditions of STE bypass and CD table allocation.
* Reworked arm_smmu_write_strtab_ent() with four helper functions
v2: https://lore.kernel.org/all/20230817042135.32822-1-nicolinc@nvidia.com/
* Rebased on top of Michael's series reworking CD table ownership
* Added a new ARM_SMMU_DOMAIN_BYPASS_S1DSS stage to tag the use case
v1: https://lore.kernel.org/all/20230627033326.5236-1-nicolinc@nvidia.com/
Nicolin Chen (2):
iommu/arm-smmu-v3: Add boolean bypass_ste and skip_cdtab flags
iommu/arm-smmu-v3: Refactor arm_smmu_write_strtab_ent()
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 232 ++++++++++++--------
1 file changed, 137 insertions(+), 95 deletions(-)
base-commit: 8bab08e86afa9e0afd25887c0c273c1506d16c0f
--
2.42.0
WARNING: multiple messages have this Message-ID (diff)
From: Nicolin Chen <nicolinc@nvidia.com>
To: <will@kernel.org>, <robin.murphy@arm.com>, <jgg@nvidia.com>
Cc: <joro@8bytes.org>, <jean-philippe@linaro.org>,
<mshavit@google.com>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <iommu@lists.linux.dev>
Subject: [PATCH v4 0/2] iommu/arm-smmu-v3: Allow default substream bypass with a pasid support
Date: Wed, 20 Sep 2023 13:52:02 -0700 [thread overview]
Message-ID: <cover.1695242337.git.nicolinc@nvidia.com> (raw)
(This series is rebased on top of Michael's refactor series [1])
When an iommu_domain is set to IOMMU_DOMAIN_IDENTITY, the driver sets the
arm_smmu_domain->stage to ARM_SMMU_DOMAIN_BYPASS and skips the allocation
of a CD table, and then sets STRTAB_STE_0_CFG_BYPASS to the CONFIG field
of the STE. This works well for devices that only have one substream, i.e.
pasid disabled.
With a pasid-capable device, however, there could be a use case where it
allows an IDENTITY domain attachment without disabling its pasid feature.
This requires the driver to allocate a multi-entry CD table to attach the
IDENTITY domain to its default substream and to configure the S1DSS filed
of the STE to STRTAB_STE_1_S1DSS_BYPASS. So, there is a missing link here
between the STE setup and an IDENTITY domain attachment.
This series fills the gap for the use case above. The first patch corrects
the conditions at ats_enabled capability and arm_smmu_alloc_cd_tables() so
that the use case above could set the ats_enabled and allocate a CD table
correctly. The second patch reworks the arm_smmu_write_strtab_ent() in a
fashion of all possible configurations of STE.Config fields.
[1]
https://lore.kernel.org/all/20230915132051.2646055-1-mshavit@google.com/
---
Changelog
v4:
* Rebased on top of v6.6-rc2 and Michael's refactor series v8 [1]
v3: https://lore.kernel.org/all/cover.1692959239.git.nicolinc@nvidia.com/
* Replaced ARM_SMMU_DOMAIN_BYPASS_S1DSS with two boolean flags to correct
conditions of STE bypass and CD table allocation.
* Reworked arm_smmu_write_strtab_ent() with four helper functions
v2: https://lore.kernel.org/all/20230817042135.32822-1-nicolinc@nvidia.com/
* Rebased on top of Michael's series reworking CD table ownership
* Added a new ARM_SMMU_DOMAIN_BYPASS_S1DSS stage to tag the use case
v1: https://lore.kernel.org/all/20230627033326.5236-1-nicolinc@nvidia.com/
Nicolin Chen (2):
iommu/arm-smmu-v3: Add boolean bypass_ste and skip_cdtab flags
iommu/arm-smmu-v3: Refactor arm_smmu_write_strtab_ent()
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 232 ++++++++++++--------
1 file changed, 137 insertions(+), 95 deletions(-)
base-commit: 8bab08e86afa9e0afd25887c0c273c1506d16c0f
--
2.42.0
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next reply other threads:[~2023-09-20 20:52 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-20 20:52 Nicolin Chen [this message]
2023-09-20 20:52 ` [PATCH v4 0/2] iommu/arm-smmu-v3: Allow default substream bypass with a pasid support Nicolin Chen
2023-09-20 20:52 ` [PATCH v4 1/2] iommu/arm-smmu-v3: Add boolean bypass_ste and skip_cdtab flags Nicolin Chen
2023-09-20 20:52 ` Nicolin Chen
2023-09-25 17:57 ` Jason Gunthorpe
2023-09-25 17:57 ` Jason Gunthorpe
2023-09-25 18:38 ` Nicolin Chen
2023-09-25 18:38 ` Nicolin Chen
2023-09-20 20:52 ` [PATCH v4 2/2] iommu/arm-smmu-v3: Refactor arm_smmu_write_strtab_ent() Nicolin Chen
2023-09-20 20:52 ` Nicolin Chen
2023-09-25 18:35 ` Jason Gunthorpe
2023-09-25 18:35 ` Jason Gunthorpe
2023-09-25 20:03 ` Nicolin Chen
2023-09-25 20:03 ` Nicolin Chen
2023-09-26 0:12 ` Jason Gunthorpe
2023-09-26 0:12 ` Jason Gunthorpe
2023-09-26 1:52 ` Nicolin Chen
2023-09-26 1:52 ` Nicolin Chen
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