* [XEN PATCH v7 1/4] x86/vmx: address violations of MISRA C:2012 Rule 7.2
2023-09-28 15:23 [XEN PATCH v7 0/4] xen/x86: address violations of MISRA C:2012 Rule 7.2 Simone Ballarin
@ 2023-09-28 15:23 ` Simone Ballarin
2023-09-28 15:23 ` [XEN PATCH v7 2/4] x86/hvm: " Simone Ballarin
` (2 subsequent siblings)
3 siblings, 0 replies; 9+ messages in thread
From: Simone Ballarin @ 2023-09-28 15:23 UTC (permalink / raw)
To: xen-devel
Cc: consulting, sstabellini, jbeulich, Gianluca Luparini,
Jun Nakajima, Kevin Tian, Andrew Cooper, Roger Pau Monné,
Wei Liu, Simone Ballarin
From: Gianluca Luparini <gianluca.luparini@bugseng.com>
The xen sources contains violations of MISRA C:2012 Rule 7.2 whose
headline states:
"A 'u' or 'U' suffix shall be applied to all integer constants
that are represented in an unsigned type".
Add the 'U' suffix to integers literals with unsigned type.
For the sake of uniformity, the following changes are made:
- add the 'U' suffix to macros near
'CPU_BASED_ACTIVATE_SECONDARY_CONTROLS' and
'SECONDARY_EXEC_NOTIFY_VM_EXITING' macros in 'vmcs.h'
- add the 'U' suffix to macros near 'INTR_INFO_VALID_MASK'
macro in 'vmx.h'
Signed-off-by: Gianluca Luparini <gianluca.luparini@bugseng.com>
Signed-off-by: Simone Ballarin <simone.ballarin@bugseng.com>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
---
No changes in v5, v6 and v7.
Changes in v4:
- change commit headline
Changes in v3:
- change 'Signed-off-by' ordering
- change commit message
- remove unnecessary changes in 'vvmx.c'
- add 'uint32_t' casts in 'vvmx.c'
- add missing 'U' in 'vmcs.h' macros
- change macro to '(1u << 31)' in 'vmx.h'
- remove unnecessary changes to 'vmx.h'
Changes in v2:
- minor change to commit title
- change commit message
- remove unnecessary changes in 'vpmu_intel.c' and 'vmx.h'
- add 'ULL' suffix in 'vpmu_intel.c'
- add zero-padding to constants in 'vmx.h'
- add missing 'U' in 'vmx.h'
---
xen/arch/x86/cpu/vpmu_intel.c | 2 +-
xen/arch/x86/hvm/vmx/vmcs.c | 6 +-
xen/arch/x86/hvm/vmx/vvmx.c | 8 +--
xen/arch/x86/include/asm/hvm/vmx/vmcs.h | 84 ++++++++++++-------------
xen/arch/x86/include/asm/hvm/vmx/vmx.h | 16 ++---
5 files changed, 58 insertions(+), 58 deletions(-)
diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c
index fa5b40c65c..6330c89b47 100644
--- a/xen/arch/x86/cpu/vpmu_intel.c
+++ b/xen/arch/x86/cpu/vpmu_intel.c
@@ -945,7 +945,7 @@ const struct arch_vpmu_ops *__init core2_vpmu_init(void)
fixed_counters_mask = ~((1ull << core2_get_bitwidth_fix_count()) - 1);
global_ctrl_mask = ~((((1ULL << fixed_pmc_cnt) - 1) << 32) |
((1ULL << arch_pmc_cnt) - 1));
- global_ovf_ctrl_mask = ~(0xC000000000000000 |
+ global_ovf_ctrl_mask = ~(0xC000000000000000ULL |
(((1ULL << fixed_pmc_cnt) - 1) << 32) |
((1ULL << arch_pmc_cnt) - 1));
if ( version > 2 )
diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c
index 13719cc923..6cefb88aec 100644
--- a/xen/arch/x86/hvm/vmx/vmcs.c
+++ b/xen/arch/x86/hvm/vmx/vmcs.c
@@ -911,7 +911,7 @@ void vmx_clear_msr_intercept(struct vcpu *v, unsigned int msr,
if ( type & VMX_MSR_W )
clear_bit(msr, msr_bitmap->write_low);
}
- else if ( (msr >= 0xc0000000) && (msr <= 0xc0001fff) )
+ else if ( (msr >= 0xc0000000U) && (msr <= 0xc0001fffU) )
{
msr &= 0x1fff;
if ( type & VMX_MSR_R )
@@ -939,7 +939,7 @@ void vmx_set_msr_intercept(struct vcpu *v, unsigned int msr,
if ( type & VMX_MSR_W )
set_bit(msr, msr_bitmap->write_low);
}
- else if ( (msr >= 0xc0000000) && (msr <= 0xc0001fff) )
+ else if ( (msr >= 0xc0000000U) && (msr <= 0xc0001fffU) )
{
msr &= 0x1fff;
if ( type & VMX_MSR_R )
@@ -957,7 +957,7 @@ bool vmx_msr_is_intercepted(struct vmx_msr_bitmap *msr_bitmap,
if ( msr <= 0x1fff )
return test_bit(msr, is_write ? msr_bitmap->write_low
: msr_bitmap->read_low);
- else if ( (msr >= 0xc0000000) && (msr <= 0xc0001fff) )
+ else if ( (msr >= 0xc0000000U) && (msr <= 0xc0001fffU) )
return test_bit(msr & 0x1fff, is_write ? msr_bitmap->write_high
: msr_bitmap->read_high);
else
diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c
index 16b0ef82b6..b7be424afb 100644
--- a/xen/arch/x86/hvm/vmx/vvmx.c
+++ b/xen/arch/x86/hvm/vmx/vvmx.c
@@ -263,7 +263,7 @@ uint64_t get_vvmcs_virtual(void *vvmcs, uint32_t vmcs_encoding)
res >>= 32;
break;
case VVMCS_WIDTH_32:
- res &= 0xffffffff;
+ res = (uint32_t)res;
break;
case VVMCS_WIDTH_NATURAL:
default:
@@ -315,14 +315,14 @@ void set_vvmcs_virtual(void *vvmcs, uint32_t vmcs_encoding, uint64_t val)
case VVMCS_WIDTH_64:
if ( enc.access_type )
{
- res &= 0xffffffff;
+ res = (uint32_t)res;
res |= val << 32;
}
else
res = val;
break;
case VVMCS_WIDTH_32:
- res = val & 0xffffffff;
+ res = (uint32_t)val;
break;
case VVMCS_WIDTH_NATURAL:
default:
@@ -2306,7 +2306,7 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content)
break;
case MSR_IA32_VMX_CR0_FIXED1:
/* allow 0-settings for all bits */
- data = 0xffffffff;
+ data = 0xffffffffU;
break;
case MSR_IA32_VMX_CR4_FIXED0:
/* VMXE bit must be 1 in VMX operation */
diff --git a/xen/arch/x86/include/asm/hvm/vmx/vmcs.h b/xen/arch/x86/include/asm/hvm/vmx/vmcs.h
index d07fcb2bc9..e056643993 100644
--- a/xen/arch/x86/include/asm/hvm/vmx/vmcs.h
+++ b/xen/arch/x86/include/asm/hvm/vmx/vmcs.h
@@ -187,27 +187,27 @@ bool_t __must_check vmx_vmcs_try_enter(struct vcpu *v);
void vmx_vmcs_exit(struct vcpu *v);
void vmx_vmcs_reload(struct vcpu *v);
-#define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
-#define CPU_BASED_USE_TSC_OFFSETING 0x00000008
-#define CPU_BASED_HLT_EXITING 0x00000080
-#define CPU_BASED_INVLPG_EXITING 0x00000200
-#define CPU_BASED_MWAIT_EXITING 0x00000400
-#define CPU_BASED_RDPMC_EXITING 0x00000800
-#define CPU_BASED_RDTSC_EXITING 0x00001000
-#define CPU_BASED_CR3_LOAD_EXITING 0x00008000
-#define CPU_BASED_CR3_STORE_EXITING 0x00010000
-#define CPU_BASED_CR8_LOAD_EXITING 0x00080000
-#define CPU_BASED_CR8_STORE_EXITING 0x00100000
-#define CPU_BASED_TPR_SHADOW 0x00200000
-#define CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000
-#define CPU_BASED_MOV_DR_EXITING 0x00800000
-#define CPU_BASED_UNCOND_IO_EXITING 0x01000000
-#define CPU_BASED_ACTIVATE_IO_BITMAP 0x02000000
-#define CPU_BASED_MONITOR_TRAP_FLAG 0x08000000
-#define CPU_BASED_ACTIVATE_MSR_BITMAP 0x10000000
-#define CPU_BASED_MONITOR_EXITING 0x20000000
-#define CPU_BASED_PAUSE_EXITING 0x40000000
-#define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000
+#define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004U
+#define CPU_BASED_USE_TSC_OFFSETING 0x00000008U
+#define CPU_BASED_HLT_EXITING 0x00000080U
+#define CPU_BASED_INVLPG_EXITING 0x00000200U
+#define CPU_BASED_MWAIT_EXITING 0x00000400U
+#define CPU_BASED_RDPMC_EXITING 0x00000800U
+#define CPU_BASED_RDTSC_EXITING 0x00001000U
+#define CPU_BASED_CR3_LOAD_EXITING 0x00008000U
+#define CPU_BASED_CR3_STORE_EXITING 0x00010000U
+#define CPU_BASED_CR8_LOAD_EXITING 0x00080000U
+#define CPU_BASED_CR8_STORE_EXITING 0x00100000U
+#define CPU_BASED_TPR_SHADOW 0x00200000U
+#define CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000U
+#define CPU_BASED_MOV_DR_EXITING 0x00800000U
+#define CPU_BASED_UNCOND_IO_EXITING 0x01000000U
+#define CPU_BASED_ACTIVATE_IO_BITMAP 0x02000000U
+#define CPU_BASED_MONITOR_TRAP_FLAG 0x08000000U
+#define CPU_BASED_ACTIVATE_MSR_BITMAP 0x10000000U
+#define CPU_BASED_MONITOR_EXITING 0x20000000U
+#define CPU_BASED_PAUSE_EXITING 0x40000000U
+#define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000U
extern u32 vmx_cpu_based_exec_control;
#define PIN_BASED_EXT_INTR_MASK 0x00000001
@@ -238,26 +238,26 @@ extern u32 vmx_vmexit_control;
#define VM_ENTRY_LOAD_BNDCFGS 0x00010000
extern u32 vmx_vmentry_control;
-#define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
-#define SECONDARY_EXEC_ENABLE_EPT 0x00000002
-#define SECONDARY_EXEC_DESCRIPTOR_TABLE_EXITING 0x00000004
-#define SECONDARY_EXEC_ENABLE_RDTSCP 0x00000008
-#define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010
-#define SECONDARY_EXEC_ENABLE_VPID 0x00000020
-#define SECONDARY_EXEC_WBINVD_EXITING 0x00000040
-#define SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080
-#define SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100
-#define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200
-#define SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400
-#define SECONDARY_EXEC_ENABLE_INVPCID 0x00001000
-#define SECONDARY_EXEC_ENABLE_VM_FUNCTIONS 0x00002000
-#define SECONDARY_EXEC_ENABLE_VMCS_SHADOWING 0x00004000
-#define SECONDARY_EXEC_ENABLE_PML 0x00020000
-#define SECONDARY_EXEC_ENABLE_VIRT_EXCEPTIONS 0x00040000
-#define SECONDARY_EXEC_XSAVES 0x00100000
-#define SECONDARY_EXEC_TSC_SCALING 0x02000000
-#define SECONDARY_EXEC_BUS_LOCK_DETECTION 0x40000000
-#define SECONDARY_EXEC_NOTIFY_VM_EXITING 0x80000000
+#define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001U
+#define SECONDARY_EXEC_ENABLE_EPT 0x00000002U
+#define SECONDARY_EXEC_DESCRIPTOR_TABLE_EXITING 0x00000004U
+#define SECONDARY_EXEC_ENABLE_RDTSCP 0x00000008U
+#define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010U
+#define SECONDARY_EXEC_ENABLE_VPID 0x00000020U
+#define SECONDARY_EXEC_WBINVD_EXITING 0x00000040U
+#define SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080U
+#define SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100U
+#define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200U
+#define SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400U
+#define SECONDARY_EXEC_ENABLE_INVPCID 0x00001000U
+#define SECONDARY_EXEC_ENABLE_VM_FUNCTIONS 0x00002000U
+#define SECONDARY_EXEC_ENABLE_VMCS_SHADOWING 0x00004000U
+#define SECONDARY_EXEC_ENABLE_PML 0x00020000U
+#define SECONDARY_EXEC_ENABLE_VIRT_EXCEPTIONS 0x00040000U
+#define SECONDARY_EXEC_XSAVES 0x00100000U
+#define SECONDARY_EXEC_TSC_SCALING 0x02000000U
+#define SECONDARY_EXEC_BUS_LOCK_DETECTION 0x40000000U
+#define SECONDARY_EXEC_NOTIFY_VM_EXITING 0x80000000U
extern u32 vmx_secondary_exec_control;
#define VMX_EPT_EXEC_ONLY_SUPPORTED 0x00000001
@@ -346,7 +346,7 @@ extern u64 vmx_ept_vpid_cap;
#define cpu_has_vmx_notify_vm_exiting \
(vmx_secondary_exec_control & SECONDARY_EXEC_NOTIFY_VM_EXITING)
-#define VMCS_RID_TYPE_MASK 0x80000000
+#define VMCS_RID_TYPE_MASK 0x80000000U
/* GUEST_INTERRUPTIBILITY_INFO flags. */
#define VMX_INTR_SHADOW_STI 0x00000001
diff --git a/xen/arch/x86/include/asm/hvm/vmx/vmx.h b/xen/arch/x86/include/asm/hvm/vmx/vmx.h
index c84acc221d..d4b335a2bc 100644
--- a/xen/arch/x86/include/asm/hvm/vmx/vmx.h
+++ b/xen/arch/x86/include/asm/hvm/vmx/vmx.h
@@ -137,7 +137,7 @@ static inline void pi_clear_sn(struct pi_desc *pi_desc)
/*
* Exit Reasons
*/
-#define VMX_EXIT_REASONS_FAILED_VMENTRY 0x80000000
+#define VMX_EXIT_REASONS_FAILED_VMENTRY (1u << 31)
#define VMX_EXIT_REASONS_BUS_LOCK (1u << 26)
#define EXIT_REASON_EXCEPTION_NMI 0
@@ -209,12 +209,12 @@ static inline void pi_clear_sn(struct pi_desc *pi_desc)
* Note INTR_INFO_NMI_UNBLOCKED_BY_IRET is also used with Exit Qualification
* field for EPT violations, PML full and SPP-related event vmexits.
*/
-#define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */
-#define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */
-#define INTR_INFO_DELIVER_CODE_MASK 0x800 /* 11 */
-#define INTR_INFO_NMI_UNBLOCKED_BY_IRET 0x1000 /* 12 */
-#define INTR_INFO_VALID_MASK 0x80000000 /* 31 */
-#define INTR_INFO_RESVD_BITS_MASK 0x7ffff000
+#define INTR_INFO_VECTOR_MASK 0x000000ffU /* 7:0 */
+#define INTR_INFO_INTR_TYPE_MASK 0x00000700U /* 10:8 */
+#define INTR_INFO_DELIVER_CODE_MASK 0x00000800U /* 11 */
+#define INTR_INFO_NMI_UNBLOCKED_BY_IRET 0x00001000U /* 12 */
+#define INTR_INFO_VALID_MASK 0x80000000U /* 31 */
+#define INTR_INFO_RESVD_BITS_MASK 0x7ffff000U
/*
* Exit Qualifications for NOTIFY VM EXIT
@@ -607,7 +607,7 @@ static inline void vmx_pi_hooks_assign(struct domain *d) {}
static inline void vmx_pi_hooks_deassign(struct domain *d) {}
#endif
-#define APIC_INVALID_DEST 0xffffffff
+#define APIC_INVALID_DEST 0xffffffffU
/* EPT violation qualifications definitions */
typedef union ept_qual {
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [XEN PATCH v7 2/4] x86/hvm: address violations of MISRA C:2012 Rule 7.2
2023-09-28 15:23 [XEN PATCH v7 0/4] xen/x86: address violations of MISRA C:2012 Rule 7.2 Simone Ballarin
2023-09-28 15:23 ` [XEN PATCH v7 1/4] x86/vmx: " Simone Ballarin
@ 2023-09-28 15:23 ` Simone Ballarin
2023-09-28 15:23 ` [XEN PATCH v7 3/4] x86/include: " Simone Ballarin
2023-09-28 15:23 ` [XEN PATCH v7 4/4] xen/x86: " Simone Ballarin
3 siblings, 0 replies; 9+ messages in thread
From: Simone Ballarin @ 2023-09-28 15:23 UTC (permalink / raw)
To: xen-devel
Cc: consulting, sstabellini, jbeulich, Simone Ballarin, Andrew Cooper,
Roger Pau Monné, Wei Liu, Gianluca Luparini
The xen sources contains violations of MISRA C:2012 Rule 7.2 whose
headline states:
"A 'u' or 'U' suffix shall be applied to all integer constants
that are represented in an unsigned type".
Add the 'U' suffix to integers literals with unsigned type.
For the sake of uniformity, the following change is made:
- add 'U' suffixes to 'mask16' in 'stdvga.c'
Signed-off-by: Gianluca Luparini <gianluca.luparini@bugseng.com>
Signed-off-by: Simone Ballarin <simone.ballarin@bugseng.com>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
---
Changes in v7:
- add Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
- switch order of Signed-off-by tags
Changes in v6:
- new patch obtained by splitting HVM related changes from
"xen/x86: address violations of MISRA C:2012 Rule 7.2 (v5)"
- fix inadvertent changes to "sr_mask"
---
xen/arch/x86/hvm/hypercall.c | 2 +-
xen/arch/x86/hvm/pmtimer.c | 4 ++--
xen/arch/x86/hvm/stdvga.c | 32 +++++++++++++-------------
xen/arch/x86/hvm/vlapic.c | 6 ++---
xen/arch/x86/include/asm/hvm/trace.h | 4 ++--
xen/arch/x86/include/asm/hvm/vioapic.h | 2 +-
6 files changed, 25 insertions(+), 25 deletions(-)
diff --git a/xen/arch/x86/hvm/hypercall.c b/xen/arch/x86/hvm/hypercall.c
index 20d266ffd5..eeb73e1aa5 100644
--- a/xen/arch/x86/hvm/hypercall.c
+++ b/xen/arch/x86/hvm/hypercall.c
@@ -129,7 +129,7 @@ int hvm_hypercall(struct cpu_user_regs *regs)
break;
}
- if ( (eax & 0x80000000) && is_viridian_domain(currd) )
+ if ( (eax & 0x80000000U) && is_viridian_domain(currd) )
{
int ret;
diff --git a/xen/arch/x86/hvm/pmtimer.c b/xen/arch/x86/hvm/pmtimer.c
index 2145c531b6..eb4a455763 100644
--- a/xen/arch/x86/hvm/pmtimer.c
+++ b/xen/arch/x86/hvm/pmtimer.c
@@ -40,8 +40,8 @@
#define SCI_IRQ 9
/* We provide a 32-bit counter (must match the TMR_VAL_EXT bit in the FADT) */
-#define TMR_VAL_MASK (0xffffffff)
-#define TMR_VAL_MSB (0x80000000)
+#define TMR_VAL_MASK (0xffffffffU)
+#define TMR_VAL_MSB (0x80000000U)
/* Dispatch SCIs based on the PM1a_STS and PM1a_EN registers */
static void pmt_update_sci(PMTState *s)
diff --git a/xen/arch/x86/hvm/stdvga.c b/xen/arch/x86/hvm/stdvga.c
index 2586891863..8da07ff8a2 100644
--- a/xen/arch/x86/hvm/stdvga.c
+++ b/xen/arch/x86/hvm/stdvga.c
@@ -39,22 +39,22 @@
#define PAT(x) (x)
static const uint32_t mask16[16] = {
- PAT(0x00000000),
- PAT(0x000000ff),
- PAT(0x0000ff00),
- PAT(0x0000ffff),
- PAT(0x00ff0000),
- PAT(0x00ff00ff),
- PAT(0x00ffff00),
- PAT(0x00ffffff),
- PAT(0xff000000),
- PAT(0xff0000ff),
- PAT(0xff00ff00),
- PAT(0xff00ffff),
- PAT(0xffff0000),
- PAT(0xffff00ff),
- PAT(0xffffff00),
- PAT(0xffffffff),
+ PAT(0x00000000U),
+ PAT(0x000000ffU),
+ PAT(0x0000ff00U),
+ PAT(0x0000ffffU),
+ PAT(0x00ff0000U),
+ PAT(0x00ff00ffU),
+ PAT(0x00ffff00U),
+ PAT(0x00ffffffU),
+ PAT(0xff000000U),
+ PAT(0xff0000ffU),
+ PAT(0xff00ff00U),
+ PAT(0xff00ffffU),
+ PAT(0xffff0000U),
+ PAT(0xffff00ffU),
+ PAT(0xffffff00U),
+ PAT(0xffffffffU),
};
/* force some bits to zero */
diff --git a/xen/arch/x86/hvm/vlapic.c b/xen/arch/x86/hvm/vlapic.c
index c7ce82d064..a8e87c4446 100644
--- a/xen/arch/x86/hvm/vlapic.c
+++ b/xen/arch/x86/hvm/vlapic.c
@@ -237,7 +237,7 @@ bool_t vlapic_match_dest(
case APIC_DEST_NOSHORT:
if ( dest_mode )
return vlapic_match_logical_addr(target, dest);
- return (dest == _VLAPIC_ID(target, 0xffffffff)) ||
+ return (dest == _VLAPIC_ID(target, 0xffffffffU)) ||
(dest == VLAPIC_ID(target));
case APIC_DEST_SELF:
@@ -467,7 +467,7 @@ static bool_t is_multicast_dest(struct vlapic *vlapic, unsigned int short_hand,
return short_hand != APIC_DEST_SELF;
if ( vlapic_x2apic_mode(vlapic) )
- return dest_mode ? hweight16(dest) > 1 : dest == 0xffffffff;
+ return dest_mode ? hweight16(dest) > 1 : dest == 0xffffffffU;
if ( dest_mode )
return hweight8(dest &
@@ -831,7 +831,7 @@ void vlapic_reg_write(struct vcpu *v, unsigned int reg, uint32_t val)
break;
case APIC_ICR2:
- vlapic_set_reg(vlapic, APIC_ICR2, val & 0xff000000);
+ vlapic_set_reg(vlapic, APIC_ICR2, val & 0xff000000U);
break;
case APIC_LVTT: /* LVT Timer Reg */
diff --git a/xen/arch/x86/include/asm/hvm/trace.h b/xen/arch/x86/include/asm/hvm/trace.h
index 696e42eb94..22eadbdd47 100644
--- a/xen/arch/x86/include/asm/hvm/trace.h
+++ b/xen/arch/x86/include/asm/hvm/trace.h
@@ -58,7 +58,7 @@
#define DO_TRC_HVM_VLAPIC DEFAULT_HVM_MISC
-#define TRC_PAR_LONG(par) ((par)&0xFFFFFFFF),((par)>>32)
+#define TRC_PAR_LONG(par) ((uint32_t)(par)), ((par) >> 32)
#define TRACE_2_LONG_2D(_e, d1, d2, ...) \
TRACE_4D(_e, d1, d2)
@@ -93,7 +93,7 @@
HVMTRACE_ND(evt, 0, 0)
#define HVMTRACE_LONG_1D(evt, d1) \
- HVMTRACE_2D(evt ## 64, (d1) & 0xFFFFFFFF, (d1) >> 32)
+ HVMTRACE_2D(evt ## 64, (uint32_t)(d1), (d1) >> 32)
#define HVMTRACE_LONG_2D(evt, d1, d2, ...) \
HVMTRACE_3D(evt ## 64, d1, d2)
#define HVMTRACE_LONG_3D(evt, d1, d2, d3, ...) \
diff --git a/xen/arch/x86/include/asm/hvm/vioapic.h b/xen/arch/x86/include/asm/hvm/vioapic.h
index 2944ec20dd..68af6dce79 100644
--- a/xen/arch/x86/include/asm/hvm/vioapic.h
+++ b/xen/arch/x86/include/asm/hvm/vioapic.h
@@ -32,7 +32,7 @@
#define VIOAPIC_EDGE_TRIG 0
#define VIOAPIC_LEVEL_TRIG 1
-#define VIOAPIC_DEFAULT_BASE_ADDRESS 0xfec00000
+#define VIOAPIC_DEFAULT_BASE_ADDRESS 0xfec00000U
#define VIOAPIC_MEM_LENGTH 0x100
/* Direct registers. */
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [XEN PATCH v7 3/4] x86/include: address violations of MISRA C:2012 Rule 7.2
2023-09-28 15:23 [XEN PATCH v7 0/4] xen/x86: address violations of MISRA C:2012 Rule 7.2 Simone Ballarin
2023-09-28 15:23 ` [XEN PATCH v7 1/4] x86/vmx: " Simone Ballarin
2023-09-28 15:23 ` [XEN PATCH v7 2/4] x86/hvm: " Simone Ballarin
@ 2023-09-28 15:23 ` Simone Ballarin
2023-09-28 22:58 ` Stefano Stabellini
2023-09-28 15:23 ` [XEN PATCH v7 4/4] xen/x86: " Simone Ballarin
3 siblings, 1 reply; 9+ messages in thread
From: Simone Ballarin @ 2023-09-28 15:23 UTC (permalink / raw)
To: xen-devel
Cc: consulting, sstabellini, jbeulich, Simone Ballarin, Andrew Cooper,
Roger Pau Monné, Wei Liu, Gianluca Luparini
The xen sources contains violations of MISRA C:2012 Rule 7.2 whose
headline states:
"A 'u' or 'U' suffix shall be applied to all integer constants
that are represented in an unsigned type".
Add the 'U' suffix to integers literals with unsigned type.
Use _AC() for macro costants that are used also in assembly files.
For the sake of uniformity, the following changes are made:
- add the 'U' suffix to macros in 'pci.h'
- use _AC() for macros near 'X86_CR0_PG'
Signed-off-by: Gianluca Luparini <gianluca.luparini@bugseng.com>
Signed-off-by: Simone Ballarin <simone.ballarin@bugseng.com>
---
Changes in v7:
- switch order of Signed-off-by tags
- change tag from x86/arm to x86/include
Changes in v6:
- new patch obtained by splitting ASM related changes from
"xen/x86: address violations of MISRA C:2012 Rule 7.2 (v5)"
- use UL suffix for X86_CR0_* macros
---
xen/arch/x86/include/asm/apicdef.h | 2 +-
xen/arch/x86/include/asm/config.h | 2 +-
xen/arch/x86/include/asm/hpet.h | 2 +-
xen/arch/x86/include/asm/msi.h | 2 +-
xen/arch/x86/include/asm/msr-index.h | 182 +++++++++++++--------------
xen/arch/x86/include/asm/pci.h | 8 +-
xen/arch/x86/include/asm/x86-defns.h | 22 ++--
7 files changed, 110 insertions(+), 110 deletions(-)
diff --git a/xen/arch/x86/include/asm/apicdef.h b/xen/arch/x86/include/asm/apicdef.h
index a261436993..8d1b0087d4 100644
--- a/xen/arch/x86/include/asm/apicdef.h
+++ b/xen/arch/x86/include/asm/apicdef.h
@@ -8,7 +8,7 @@
* Ingo Molnar <mingo@redhat.com>, 1999, 2000
*/
-#define APIC_DEFAULT_PHYS_BASE 0xfee00000
+#define APIC_DEFAULT_PHYS_BASE 0xfee00000U
#define APIC_ID 0x20
#define APIC_ID_MASK (0xFFu<<24)
diff --git a/xen/arch/x86/include/asm/config.h b/xen/arch/x86/include/asm/config.h
index fbc4bb3416..bbced338be 100644
--- a/xen/arch/x86/include/asm/config.h
+++ b/xen/arch/x86/include/asm/config.h
@@ -257,7 +257,7 @@ extern unsigned char boot_edid_info[128];
#endif /* CONFIG_PV32 */
#define MACH2PHYS_COMPAT_VIRT_START HYPERVISOR_COMPAT_VIRT_START
-#define MACH2PHYS_COMPAT_VIRT_END 0xFFE00000
+#define MACH2PHYS_COMPAT_VIRT_END 0xFFE00000U
#define MACH2PHYS_COMPAT_NR_ENTRIES(d) \
((MACH2PHYS_COMPAT_VIRT_END-MACH2PHYS_COMPAT_VIRT_START(d))>>2)
diff --git a/xen/arch/x86/include/asm/hpet.h b/xen/arch/x86/include/asm/hpet.h
index 9919f74730..c5e8e9c8db 100644
--- a/xen/arch/x86/include/asm/hpet.h
+++ b/xen/arch/x86/include/asm/hpet.h
@@ -41,7 +41,7 @@
#define HPET_TN_ROUTE 0x3e00
#define HPET_TN_FSB 0x4000
#define HPET_TN_FSB_CAP 0x8000
-#define HPET_TN_RESERVED 0xffff0081
+#define HPET_TN_RESERVED 0xffff0081U
#define HPET_TN_INT_ROUTE_CAP (0xffffffffULL << 32)
diff --git a/xen/arch/x86/include/asm/msi.h b/xen/arch/x86/include/asm/msi.h
index a53ade95c9..d89723d009 100644
--- a/xen/arch/x86/include/asm/msi.h
+++ b/xen/arch/x86/include/asm/msi.h
@@ -37,7 +37,7 @@
*/
#define MSI_ADDR_BASE_HI 0
-#define MSI_ADDR_BASE_LO 0xfee00000
+#define MSI_ADDR_BASE_LO 0xfee00000U
#define MSI_ADDR_BASE_MASK (~0xfffff)
#define MSI_ADDR_HEADER MSI_ADDR_BASE_LO
diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h
index 11ffed543a..718f8f860d 100644
--- a/xen/arch/x86/include/asm/msr-index.h
+++ b/xen/arch/x86/include/asm/msr-index.h
@@ -22,7 +22,7 @@
#define APIC_BASE_BSP (_AC(1, ULL) << 8)
#define APIC_BASE_EXTD (_AC(1, ULL) << 10)
#define APIC_BASE_ENABLE (_AC(1, ULL) << 11)
-#define APIC_BASE_ADDR_MASK 0x000ffffffffff000ULL
+#define APIC_BASE_ADDR_MASK _AC(0x000ffffffffff000, ULL)
#define MSR_TEST_CTRL 0x00000033
#define TEST_CTRL_SPLITLOCK_DETECT (_AC(1, ULL) << 29)
@@ -30,7 +30,7 @@
#define MSR_INTEL_CORE_THREAD_COUNT 0x00000035
#define MSR_CTC_THREAD_MASK 0x0000ffff
-#define MSR_CTC_CORE_MASK 0xffff0000
+#define MSR_CTC_CORE_MASK _AC(0xffff0000, U)
#define MSR_SPEC_CTRL 0x00000048
#define SPEC_CTRL_IBRS (_AC(1, ULL) << 0)
@@ -186,7 +186,7 @@
#define MSR_UARCH_MISC_CTRL 0x00001b01
#define UARCH_CTRL_DOITM (_AC(1, ULL) << 0)
-#define MSR_EFER 0xc0000080 /* Extended Feature Enable Register */
+#define MSR_EFER _AC(0xc0000080, U) /* Extended Feature Enable Register */
#define EFER_SCE (_AC(1, ULL) << 0) /* SYSCALL Enable */
#define EFER_LME (_AC(1, ULL) << 8) /* Long Mode Enable */
#define EFER_LMA (_AC(1, ULL) << 10) /* Long Mode Active */
@@ -199,35 +199,35 @@
(EFER_SCE | EFER_LME | EFER_LMA | EFER_NXE | EFER_SVME | EFER_FFXSE | \
EFER_AIBRSE)
-#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
-#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
-#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
-#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
-#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
-#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
-#define MSR_SHADOW_GS_BASE 0xc0000102 /* SwapGS GS shadow */
-#define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */
+#define MSR_STAR _AC(0xc0000081, U) /* legacy mode SYSCALL target */
+#define MSR_LSTAR _AC(0xc0000082, U) /* long mode SYSCALL target */
+#define MSR_CSTAR _AC(0xc0000083, U) /* compat mode SYSCALL target */
+#define MSR_SYSCALL_MASK _AC(0xc0000084, U) /* EFLAGS mask for syscall */
+#define MSR_FS_BASE _AC(0xc0000100, U) /* 64bit FS base */
+#define MSR_GS_BASE _AC(0xc0000101, U) /* 64bit GS base */
+#define MSR_SHADOW_GS_BASE _AC(0xc0000102, U) /* SwapGS GS shadow */
+#define MSR_TSC_AUX _AC(0xc0000103, U) /* Auxiliary TSC */
-#define MSR_K8_SYSCFG 0xc0010010
+#define MSR_K8_SYSCFG _AC(0xc0010010, U)
#define SYSCFG_MTRR_FIX_DRAM_EN (_AC(1, ULL) << 18)
#define SYSCFG_MTRR_FIX_DRAM_MOD_EN (_AC(1, ULL) << 19)
#define SYSCFG_MTRR_VAR_DRAM_EN (_AC(1, ULL) << 20)
#define SYSCFG_MTRR_TOM2_EN (_AC(1, ULL) << 21)
#define SYSCFG_TOM2_FORCE_WB (_AC(1, ULL) << 22)
-#define MSR_K8_IORR_BASE0 0xc0010016
-#define MSR_K8_IORR_MASK0 0xc0010017
-#define MSR_K8_IORR_BASE1 0xc0010018
-#define MSR_K8_IORR_MASK1 0xc0010019
+#define MSR_K8_IORR_BASE0 _AC(0xc0010016, U)
+#define MSR_K8_IORR_MASK0 _AC(0xc0010017, U)
+#define MSR_K8_IORR_BASE1 _AC(0xc0010018, U)
+#define MSR_K8_IORR_MASK1 _AC(0xc0010019, U)
-#define MSR_K8_TSEG_BASE 0xc0010112 /* AMD doc: SMMAddr */
-#define MSR_K8_TSEG_MASK 0xc0010113 /* AMD doc: SMMMask */
+#define MSR_K8_TSEG_BASE _AC(0xc0010112, U) /* AMD doc: SMMAddr */
+#define MSR_K8_TSEG_MASK _AC(0xc0010113, U) /* AMD doc: SMMMask */
-#define MSR_K8_VM_CR 0xc0010114
+#define MSR_K8_VM_CR _AC(0xc0010114, U)
#define VM_CR_INIT_REDIRECTION (_AC(1, ULL) << 1)
#define VM_CR_SVM_DISABLE (_AC(1, ULL) << 4)
-#define MSR_VIRT_SPEC_CTRL 0xc001011f /* Layout matches MSR_SPEC_CTRL */
+#define MSR_VIRT_SPEC_CTRL _AC(0xc001011f, U) /* Layout matches MSR_SPEC_CTRL */
#define MSR_AMD_CSTATE_CFG 0xc0010296
@@ -313,7 +313,7 @@
#define CMCI_EN (1UL<<30)
#define CMCI_THRESHOLD_MASK 0x7FFF
-#define MSR_AMD64_MC0_MASK 0xc0010044
+#define MSR_AMD64_MC0_MASK 0xc0010044U
#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
#define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x))
@@ -345,82 +345,82 @@
/* K7/K8 MSRs. Not complete. See the architecture manual for a more
complete list. */
-#define MSR_K7_EVNTSEL0 0xc0010000
-#define MSR_K7_PERFCTR0 0xc0010004
-#define MSR_K7_EVNTSEL1 0xc0010001
-#define MSR_K7_PERFCTR1 0xc0010005
-#define MSR_K7_EVNTSEL2 0xc0010002
-#define MSR_K7_PERFCTR2 0xc0010006
-#define MSR_K7_EVNTSEL3 0xc0010003
-#define MSR_K7_PERFCTR3 0xc0010007
-#define MSR_K8_TOP_MEM1 0xc001001a
-#define MSR_K8_TOP_MEM2 0xc001001d
-
-#define MSR_K8_HWCR 0xc0010015
+#define MSR_K7_EVNTSEL0 0xc0010000U
+#define MSR_K7_PERFCTR0 0xc0010004U
+#define MSR_K7_EVNTSEL1 0xc0010001U
+#define MSR_K7_PERFCTR1 0xc0010005U
+#define MSR_K7_EVNTSEL2 0xc0010002U
+#define MSR_K7_PERFCTR2 0xc0010006U
+#define MSR_K7_EVNTSEL3 0xc0010003U
+#define MSR_K7_PERFCTR3 0xc0010007U
+#define MSR_K8_TOP_MEM1 0xc001001aU
+#define MSR_K8_TOP_MEM2 0xc001001dU
+
+#define MSR_K8_HWCR 0xc0010015U
#define K8_HWCR_TSC_FREQ_SEL (1ULL << 24)
#define K8_HWCR_CPUID_USER_DIS (1ULL << 35)
-#define MSR_K7_FID_VID_CTL 0xc0010041
-#define MSR_K7_FID_VID_STATUS 0xc0010042
-#define MSR_K8_PSTATE_LIMIT 0xc0010061
-#define MSR_K8_PSTATE_CTRL 0xc0010062
-#define MSR_K8_PSTATE_STATUS 0xc0010063
-#define MSR_K8_PSTATE0 0xc0010064
-#define MSR_K8_PSTATE1 0xc0010065
-#define MSR_K8_PSTATE2 0xc0010066
-#define MSR_K8_PSTATE3 0xc0010067
-#define MSR_K8_PSTATE4 0xc0010068
-#define MSR_K8_PSTATE5 0xc0010069
-#define MSR_K8_PSTATE6 0xc001006A
-#define MSR_K8_PSTATE7 0xc001006B
-#define MSR_K8_ENABLE_C1E 0xc0010055
-#define MSR_K8_VM_HSAVE_PA 0xc0010117
-
-#define MSR_AMD_FAM15H_EVNTSEL0 0xc0010200
-#define MSR_AMD_FAM15H_PERFCTR0 0xc0010201
-#define MSR_AMD_FAM15H_EVNTSEL1 0xc0010202
-#define MSR_AMD_FAM15H_PERFCTR1 0xc0010203
-#define MSR_AMD_FAM15H_EVNTSEL2 0xc0010204
-#define MSR_AMD_FAM15H_PERFCTR2 0xc0010205
-#define MSR_AMD_FAM15H_EVNTSEL3 0xc0010206
-#define MSR_AMD_FAM15H_PERFCTR3 0xc0010207
-#define MSR_AMD_FAM15H_EVNTSEL4 0xc0010208
-#define MSR_AMD_FAM15H_PERFCTR4 0xc0010209
-#define MSR_AMD_FAM15H_EVNTSEL5 0xc001020a
-#define MSR_AMD_FAM15H_PERFCTR5 0xc001020b
-
-#define MSR_AMD_L7S0_FEATURE_MASK 0xc0011002
-#define MSR_AMD_THRM_FEATURE_MASK 0xc0011003
-#define MSR_K8_FEATURE_MASK 0xc0011004
-#define MSR_K8_EXT_FEATURE_MASK 0xc0011005
+#define MSR_K7_FID_VID_CTL 0xc0010041U
+#define MSR_K7_FID_VID_STATUS 0xc0010042U
+#define MSR_K8_PSTATE_LIMIT 0xc0010061U
+#define MSR_K8_PSTATE_CTRL 0xc0010062U
+#define MSR_K8_PSTATE_STATUS 0xc0010063U
+#define MSR_K8_PSTATE0 0xc0010064U
+#define MSR_K8_PSTATE1 0xc0010065U
+#define MSR_K8_PSTATE2 0xc0010066U
+#define MSR_K8_PSTATE3 0xc0010067U
+#define MSR_K8_PSTATE4 0xc0010068U
+#define MSR_K8_PSTATE5 0xc0010069U
+#define MSR_K8_PSTATE6 0xc001006AU
+#define MSR_K8_PSTATE7 0xc001006BU
+#define MSR_K8_ENABLE_C1E 0xc0010055U
+#define MSR_K8_VM_HSAVE_PA 0xc0010117U
+
+#define MSR_AMD_FAM15H_EVNTSEL0 0xc0010200U
+#define MSR_AMD_FAM15H_PERFCTR0 0xc0010201U
+#define MSR_AMD_FAM15H_EVNTSEL1 0xc0010202U
+#define MSR_AMD_FAM15H_PERFCTR1 0xc0010203U
+#define MSR_AMD_FAM15H_EVNTSEL2 0xc0010204U
+#define MSR_AMD_FAM15H_PERFCTR2 0xc0010205U
+#define MSR_AMD_FAM15H_EVNTSEL3 0xc0010206U
+#define MSR_AMD_FAM15H_PERFCTR3 0xc0010207U
+#define MSR_AMD_FAM15H_EVNTSEL4 0xc0010208U
+#define MSR_AMD_FAM15H_PERFCTR4 0xc0010209U
+#define MSR_AMD_FAM15H_EVNTSEL5 0xc001020aU
+#define MSR_AMD_FAM15H_PERFCTR5 0xc001020bU
+
+#define MSR_AMD_L7S0_FEATURE_MASK 0xc0011002U
+#define MSR_AMD_THRM_FEATURE_MASK 0xc0011003U
+#define MSR_K8_FEATURE_MASK 0xc0011004U
+#define MSR_K8_EXT_FEATURE_MASK 0xc0011005U
/* AMD64 MSRs */
-#define MSR_AMD64_NB_CFG 0xc001001f
+#define MSR_AMD64_NB_CFG 0xc001001fU
#define AMD64_NB_CFG_CF8_EXT_ENABLE_BIT 46
-#define MSR_AMD64_LS_CFG 0xc0011020
-#define MSR_AMD64_IC_CFG 0xc0011021
-#define MSR_AMD64_DC_CFG 0xc0011022
-#define MSR_AMD64_DE_CFG 0xc0011029
+#define MSR_AMD64_LS_CFG 0xc0011020U
+#define MSR_AMD64_IC_CFG 0xc0011021U
+#define MSR_AMD64_DC_CFG 0xc0011022U
+#define MSR_AMD64_DE_CFG 0xc0011029U
#define AMD64_DE_CFG_LFENCE_SERIALISE (_AC(1, ULL) << 1)
-#define MSR_AMD64_EX_CFG 0xc001102c
-#define MSR_AMD64_DE_CFG2 0xc00110e3
+#define MSR_AMD64_EX_CFG 0xc001102cU
+#define MSR_AMD64_DE_CFG2 0xc00110e3U
-#define MSR_AMD64_DR0_ADDRESS_MASK 0xc0011027
-#define MSR_AMD64_DR1_ADDRESS_MASK 0xc0011019
-#define MSR_AMD64_DR2_ADDRESS_MASK 0xc001101a
-#define MSR_AMD64_DR3_ADDRESS_MASK 0xc001101b
+#define MSR_AMD64_DR0_ADDRESS_MASK 0xc0011027U
+#define MSR_AMD64_DR1_ADDRESS_MASK 0xc0011019U
+#define MSR_AMD64_DR2_ADDRESS_MASK 0xc001101aU
+#define MSR_AMD64_DR3_ADDRESS_MASK 0xc001101bU
/* AMD Family10h machine check MSRs */
-#define MSR_F10_MC4_MISC1 0xc0000408
-#define MSR_F10_MC4_MISC2 0xc0000409
-#define MSR_F10_MC4_MISC3 0xc000040A
+#define MSR_F10_MC4_MISC1 0xc0000408U
+#define MSR_F10_MC4_MISC2 0xc0000409U
+#define MSR_F10_MC4_MISC3 0xc000040AU
/* AMD Family10h Bus Unit MSRs */
-#define MSR_F10_BU_CFG 0xc0011023
-#define MSR_F10_BU_CFG2 0xc001102a
+#define MSR_F10_BU_CFG 0xc0011023U
+#define MSR_F10_BU_CFG2 0xc001102aU
/* Other AMD Fam10h MSRs */
-#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
+#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058U
#define FAM10H_MMIO_CONF_ENABLE (1<<0)
#define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf
#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
@@ -429,22 +429,22 @@
/* AMD Microcode MSRs */
#define MSR_AMD_PATCHLEVEL 0x0000008b
-#define MSR_AMD_PATCHLOADER 0xc0010020
+#define MSR_AMD_PATCHLOADER 0xc0010020U
/* AMD TSC RATE MSR */
-#define MSR_AMD64_TSC_RATIO 0xc0000104
+#define MSR_AMD64_TSC_RATIO 0xc0000104U
/* AMD Lightweight Profiling MSRs */
-#define MSR_AMD64_LWP_CFG 0xc0000105
-#define MSR_AMD64_LWP_CBADDR 0xc0000106
+#define MSR_AMD64_LWP_CFG 0xc0000105U
+#define MSR_AMD64_LWP_CBADDR 0xc0000106U
/* AMD OS Visible Workaround MSRs */
-#define MSR_AMD_OSVW_ID_LENGTH 0xc0010140
-#define MSR_AMD_OSVW_STATUS 0xc0010141
+#define MSR_AMD_OSVW_ID_LENGTH 0xc0010140U
+#define MSR_AMD_OSVW_STATUS 0xc0010141U
/* AMD Protected Processor Inventory Number */
-#define MSR_AMD_PPIN_CTL 0xc00102f0
-#define MSR_AMD_PPIN 0xc00102f1
+#define MSR_AMD_PPIN_CTL 0xc00102f0U
+#define MSR_AMD_PPIN 0xc00102f1U
/* VIA Cyrix defined MSRs*/
#define MSR_VIA_FCR 0x00001107
diff --git a/xen/arch/x86/include/asm/pci.h b/xen/arch/x86/include/asm/pci.h
index f4a58c8acf..e1dd12eb19 100644
--- a/xen/arch/x86/include/asm/pci.h
+++ b/xen/arch/x86/include/asm/pci.h
@@ -3,10 +3,10 @@
#include <xen/mm.h>
-#define CF8_BDF(cf8) ( ((cf8) & 0x00ffff00) >> 8)
-#define CF8_ADDR_LO(cf8) ( (cf8) & 0x000000fc)
-#define CF8_ADDR_HI(cf8) ( ((cf8) & 0x0f000000) >> 16)
-#define CF8_ENABLED(cf8) (!!((cf8) & 0x80000000))
+#define CF8_BDF(cf8) ( ((cf8) & 0x00ffff00U) >> 8)
+#define CF8_ADDR_LO(cf8) ( (cf8) & 0x000000fcU)
+#define CF8_ADDR_HI(cf8) ( ((cf8) & 0x0f000000U) >> 16)
+#define CF8_ENABLED(cf8) (!!((cf8) & 0x80000000U))
#define IS_SNB_GFX(id) (id == 0x01068086 || id == 0x01168086 \
|| id == 0x01268086 || id == 0x01028086 \
diff --git a/xen/arch/x86/include/asm/x86-defns.h b/xen/arch/x86/include/asm/x86-defns.h
index 5838631ef6..48d7a3b7af 100644
--- a/xen/arch/x86/include/asm/x86-defns.h
+++ b/xen/arch/x86/include/asm/x86-defns.h
@@ -30,17 +30,17 @@
/*
* Intel CPU flags in CR0
*/
-#define X86_CR0_PE 0x00000001 /* Enable Protected Mode (RW) */
-#define X86_CR0_MP 0x00000002 /* Monitor Coprocessor (RW) */
-#define X86_CR0_EM 0x00000004 /* Require FPU Emulation (RO) */
-#define X86_CR0_TS 0x00000008 /* Task Switched (RW) */
-#define X86_CR0_ET 0x00000010 /* Extension type (RO) */
-#define X86_CR0_NE 0x00000020 /* Numeric Error Reporting (RW) */
-#define X86_CR0_WP 0x00010000 /* Supervisor Write Protect (RW) */
-#define X86_CR0_AM 0x00040000 /* Alignment Checking (RW) */
-#define X86_CR0_NW 0x20000000 /* Not Write-Through (RW) */
-#define X86_CR0_CD 0x40000000 /* Cache Disable (RW) */
-#define X86_CR0_PG 0x80000000 /* Paging (RW) */
+#define X86_CR0_PE _AC(0x00000001, UL) /* Enable Protected Mode (RW) */
+#define X86_CR0_MP _AC(0x00000002, UL) /* Monitor Coprocessor (RW) */
+#define X86_CR0_EM _AC(0x00000004, UL) /* Require FPU Emulation (RO) */
+#define X86_CR0_TS _AC(0x00000008, UL) /* Task Switched (RW) */
+#define X86_CR0_ET _AC(0x00000010, UL) /* Extension type (RO) */
+#define X86_CR0_NE _AC(0x00000020, UL) /* Numeric Error Reporting (RW) */
+#define X86_CR0_WP _AC(0x00010000, UL) /* Supervisor Write Protect (RW) */
+#define X86_CR0_AM _AC(0x00040000, UL) /* Alignment Checking (RW) */
+#define X86_CR0_NW _AC(0x20000000, UL) /* Not Write-Through (RW) */
+#define X86_CR0_CD _AC(0x40000000, UL) /* Cache Disable (RW) */
+#define X86_CR0_PG _AC(0x80000000, UL) /* Paging (RW) */
/*
* Intel CPU flags in CR3
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [XEN PATCH v7 3/4] x86/include: address violations of MISRA C:2012 Rule 7.2
2023-09-28 15:23 ` [XEN PATCH v7 3/4] x86/include: " Simone Ballarin
@ 2023-09-28 22:58 ` Stefano Stabellini
2023-09-29 7:46 ` Simone Ballarin
0 siblings, 1 reply; 9+ messages in thread
From: Stefano Stabellini @ 2023-09-28 22:58 UTC (permalink / raw)
To: Simone Ballarin
Cc: xen-devel, consulting, sstabellini, jbeulich, Andrew Cooper,
Roger Pau Monné, Wei Liu, Gianluca Luparini
On Thu, 28 Sep 2023, Simone Ballarin wrote:
> The xen sources contains violations of MISRA C:2012 Rule 7.2 whose
> headline states:
> "A 'u' or 'U' suffix shall be applied to all integer constants
> that are represented in an unsigned type".
>
> Add the 'U' suffix to integers literals with unsigned type.
> Use _AC() for macro costants that are used also in assembly files.
>
> For the sake of uniformity, the following changes are made:
> - add the 'U' suffix to macros in 'pci.h'
> - use _AC() for macros near 'X86_CR0_PG'
>
> Signed-off-by: Gianluca Luparini <gianluca.luparini@bugseng.com>
> Signed-off-by: Simone Ballarin <simone.ballarin@bugseng.com>
> ---
> Changes in v7:
> - switch order of Signed-off-by tags
> - change tag from x86/arm to x86/include
> Changes in v6:
> - new patch obtained by splitting ASM related changes from
> "xen/x86: address violations of MISRA C:2012 Rule 7.2 (v5)"
> - use UL suffix for X86_CR0_* macros
> ---
> xen/arch/x86/include/asm/apicdef.h | 2 +-
> xen/arch/x86/include/asm/config.h | 2 +-
> xen/arch/x86/include/asm/hpet.h | 2 +-
> xen/arch/x86/include/asm/msi.h | 2 +-
> xen/arch/x86/include/asm/msr-index.h | 182 +++++++++++++--------------
> xen/arch/x86/include/asm/pci.h | 8 +-
> xen/arch/x86/include/asm/x86-defns.h | 22 ++--
> 7 files changed, 110 insertions(+), 110 deletions(-)
>
> diff --git a/xen/arch/x86/include/asm/apicdef.h b/xen/arch/x86/include/asm/apicdef.h
> index a261436993..8d1b0087d4 100644
> --- a/xen/arch/x86/include/asm/apicdef.h
> +++ b/xen/arch/x86/include/asm/apicdef.h
> @@ -8,7 +8,7 @@
> * Ingo Molnar <mingo@redhat.com>, 1999, 2000
> */
>
> -#define APIC_DEFAULT_PHYS_BASE 0xfee00000
> +#define APIC_DEFAULT_PHYS_BASE 0xfee00000U
>
> #define APIC_ID 0x20
> #define APIC_ID_MASK (0xFFu<<24)
> diff --git a/xen/arch/x86/include/asm/config.h b/xen/arch/x86/include/asm/config.h
> index fbc4bb3416..bbced338be 100644
> --- a/xen/arch/x86/include/asm/config.h
> +++ b/xen/arch/x86/include/asm/config.h
> @@ -257,7 +257,7 @@ extern unsigned char boot_edid_info[128];
> #endif /* CONFIG_PV32 */
>
> #define MACH2PHYS_COMPAT_VIRT_START HYPERVISOR_COMPAT_VIRT_START
> -#define MACH2PHYS_COMPAT_VIRT_END 0xFFE00000
> +#define MACH2PHYS_COMPAT_VIRT_END 0xFFE00000U
> #define MACH2PHYS_COMPAT_NR_ENTRIES(d) \
> ((MACH2PHYS_COMPAT_VIRT_END-MACH2PHYS_COMPAT_VIRT_START(d))>>2)
>
> diff --git a/xen/arch/x86/include/asm/hpet.h b/xen/arch/x86/include/asm/hpet.h
> index 9919f74730..c5e8e9c8db 100644
> --- a/xen/arch/x86/include/asm/hpet.h
> +++ b/xen/arch/x86/include/asm/hpet.h
> @@ -41,7 +41,7 @@
> #define HPET_TN_ROUTE 0x3e00
> #define HPET_TN_FSB 0x4000
> #define HPET_TN_FSB_CAP 0x8000
> -#define HPET_TN_RESERVED 0xffff0081
> +#define HPET_TN_RESERVED 0xffff0081U
> #define HPET_TN_INT_ROUTE_CAP (0xffffffffULL << 32)
>
>
> diff --git a/xen/arch/x86/include/asm/msi.h b/xen/arch/x86/include/asm/msi.h
> index a53ade95c9..d89723d009 100644
> --- a/xen/arch/x86/include/asm/msi.h
> +++ b/xen/arch/x86/include/asm/msi.h
> @@ -37,7 +37,7 @@
> */
>
> #define MSI_ADDR_BASE_HI 0
> -#define MSI_ADDR_BASE_LO 0xfee00000
> +#define MSI_ADDR_BASE_LO 0xfee00000U
> #define MSI_ADDR_BASE_MASK (~0xfffff)
> #define MSI_ADDR_HEADER MSI_ADDR_BASE_LO
>
> diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h
> index 11ffed543a..718f8f860d 100644
> --- a/xen/arch/x86/include/asm/msr-index.h
> +++ b/xen/arch/x86/include/asm/msr-index.h
> @@ -22,7 +22,7 @@
> #define APIC_BASE_BSP (_AC(1, ULL) << 8)
> #define APIC_BASE_EXTD (_AC(1, ULL) << 10)
> #define APIC_BASE_ENABLE (_AC(1, ULL) << 11)
> -#define APIC_BASE_ADDR_MASK 0x000ffffffffff000ULL
> +#define APIC_BASE_ADDR_MASK _AC(0x000ffffffffff000, ULL)
This is not used by assembly code?
> #define MSR_TEST_CTRL 0x00000033
> #define TEST_CTRL_SPLITLOCK_DETECT (_AC(1, ULL) << 29)
> @@ -30,7 +30,7 @@
>
> #define MSR_INTEL_CORE_THREAD_COUNT 0x00000035
> #define MSR_CTC_THREAD_MASK 0x0000ffff
> -#define MSR_CTC_CORE_MASK 0xffff0000
> +#define MSR_CTC_CORE_MASK _AC(0xffff0000, U)
Also this one is not?
> #define MSR_SPEC_CTRL 0x00000048
> #define SPEC_CTRL_IBRS (_AC(1, ULL) << 0)
> @@ -186,7 +186,7 @@
> #define MSR_UARCH_MISC_CTRL 0x00001b01
> #define UARCH_CTRL_DOITM (_AC(1, ULL) << 0)
>
> -#define MSR_EFER 0xc0000080 /* Extended Feature Enable Register */
> +#define MSR_EFER _AC(0xc0000080, U) /* Extended Feature Enable Register */
> #define EFER_SCE (_AC(1, ULL) << 0) /* SYSCALL Enable */
> #define EFER_LME (_AC(1, ULL) << 8) /* Long Mode Enable */
> #define EFER_LMA (_AC(1, ULL) << 10) /* Long Mode Active */
> @@ -199,35 +199,35 @@
> (EFER_SCE | EFER_LME | EFER_LMA | EFER_NXE | EFER_SVME | EFER_FFXSE | \
> EFER_AIBRSE)
>
> -#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
> -#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
> -#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
> -#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
> -#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
> -#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
> -#define MSR_SHADOW_GS_BASE 0xc0000102 /* SwapGS GS shadow */
> -#define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */
> +#define MSR_STAR _AC(0xc0000081, U) /* legacy mode SYSCALL target */
> +#define MSR_LSTAR _AC(0xc0000082, U) /* long mode SYSCALL target */
> +#define MSR_CSTAR _AC(0xc0000083, U) /* compat mode SYSCALL target */
> +#define MSR_SYSCALL_MASK _AC(0xc0000084, U) /* EFLAGS mask for syscall */
> +#define MSR_FS_BASE _AC(0xc0000100, U) /* 64bit FS base */
> +#define MSR_GS_BASE _AC(0xc0000101, U) /* 64bit GS base */
> +#define MSR_SHADOW_GS_BASE _AC(0xc0000102, U) /* SwapGS GS shadow */
> +#define MSR_TSC_AUX _AC(0xc0000103, U) /* Auxiliary TSC */
None of these set seems to be used by assembly code
> -#define MSR_K8_SYSCFG 0xc0010010
> +#define MSR_K8_SYSCFG _AC(0xc0010010, U)
This one also is not?
> #define SYSCFG_MTRR_FIX_DRAM_EN (_AC(1, ULL) << 18)
> #define SYSCFG_MTRR_FIX_DRAM_MOD_EN (_AC(1, ULL) << 19)
> #define SYSCFG_MTRR_VAR_DRAM_EN (_AC(1, ULL) << 20)
> #define SYSCFG_MTRR_TOM2_EN (_AC(1, ULL) << 21)
> #define SYSCFG_TOM2_FORCE_WB (_AC(1, ULL) << 22)
>
> -#define MSR_K8_IORR_BASE0 0xc0010016
> -#define MSR_K8_IORR_MASK0 0xc0010017
> -#define MSR_K8_IORR_BASE1 0xc0010018
> -#define MSR_K8_IORR_MASK1 0xc0010019
> +#define MSR_K8_IORR_BASE0 _AC(0xc0010016, U)
> +#define MSR_K8_IORR_MASK0 _AC(0xc0010017, U)
> +#define MSR_K8_IORR_BASE1 _AC(0xc0010018, U)
> +#define MSR_K8_IORR_MASK1 _AC(0xc0010019, U)
These ones are not?
> -#define MSR_K8_TSEG_BASE 0xc0010112 /* AMD doc: SMMAddr */
> -#define MSR_K8_TSEG_MASK 0xc0010113 /* AMD doc: SMMMask */
> +#define MSR_K8_TSEG_BASE _AC(0xc0010112, U) /* AMD doc: SMMAddr */
> +#define MSR_K8_TSEG_MASK _AC(0xc0010113, U) /* AMD doc: SMMMask */
These ones are not?
>
> -#define MSR_K8_VM_CR 0xc0010114
> +#define MSR_K8_VM_CR _AC(0xc0010114, U)
Also this one
> #define VM_CR_INIT_REDIRECTION (_AC(1, ULL) << 1)
> #define VM_CR_SVM_DISABLE (_AC(1, ULL) << 4)
>
> -#define MSR_VIRT_SPEC_CTRL 0xc001011f /* Layout matches MSR_SPEC_CTRL */
> +#define MSR_VIRT_SPEC_CTRL _AC(0xc001011f, U) /* Layout matches MSR_SPEC_CTRL */
And this one.
What am I missing? Did you also add _AC to all the places where the
constants end up being used in asm inline? Because I don't think that
asm inline needs the _AC...
> #define MSR_AMD_CSTATE_CFG 0xc0010296
>
> @@ -313,7 +313,7 @@
> #define CMCI_EN (1UL<<30)
> #define CMCI_THRESHOLD_MASK 0x7FFF
>
> -#define MSR_AMD64_MC0_MASK 0xc0010044
> +#define MSR_AMD64_MC0_MASK 0xc0010044U
>
> #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
> #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x))
> @@ -345,82 +345,82 @@
>
> /* K7/K8 MSRs. Not complete. See the architecture manual for a more
> complete list. */
> -#define MSR_K7_EVNTSEL0 0xc0010000
> -#define MSR_K7_PERFCTR0 0xc0010004
> -#define MSR_K7_EVNTSEL1 0xc0010001
> -#define MSR_K7_PERFCTR1 0xc0010005
> -#define MSR_K7_EVNTSEL2 0xc0010002
> -#define MSR_K7_PERFCTR2 0xc0010006
> -#define MSR_K7_EVNTSEL3 0xc0010003
> -#define MSR_K7_PERFCTR3 0xc0010007
> -#define MSR_K8_TOP_MEM1 0xc001001a
> -#define MSR_K8_TOP_MEM2 0xc001001d
> -
> -#define MSR_K8_HWCR 0xc0010015
> +#define MSR_K7_EVNTSEL0 0xc0010000U
> +#define MSR_K7_PERFCTR0 0xc0010004U
> +#define MSR_K7_EVNTSEL1 0xc0010001U
> +#define MSR_K7_PERFCTR1 0xc0010005U
> +#define MSR_K7_EVNTSEL2 0xc0010002U
> +#define MSR_K7_PERFCTR2 0xc0010006U
> +#define MSR_K7_EVNTSEL3 0xc0010003U
> +#define MSR_K7_PERFCTR3 0xc0010007U
> +#define MSR_K8_TOP_MEM1 0xc001001aU
> +#define MSR_K8_TOP_MEM2 0xc001001dU
> +
> +#define MSR_K8_HWCR 0xc0010015U
> #define K8_HWCR_TSC_FREQ_SEL (1ULL << 24)
> #define K8_HWCR_CPUID_USER_DIS (1ULL << 35)
>
> -#define MSR_K7_FID_VID_CTL 0xc0010041
> -#define MSR_K7_FID_VID_STATUS 0xc0010042
> -#define MSR_K8_PSTATE_LIMIT 0xc0010061
> -#define MSR_K8_PSTATE_CTRL 0xc0010062
> -#define MSR_K8_PSTATE_STATUS 0xc0010063
> -#define MSR_K8_PSTATE0 0xc0010064
> -#define MSR_K8_PSTATE1 0xc0010065
> -#define MSR_K8_PSTATE2 0xc0010066
> -#define MSR_K8_PSTATE3 0xc0010067
> -#define MSR_K8_PSTATE4 0xc0010068
> -#define MSR_K8_PSTATE5 0xc0010069
> -#define MSR_K8_PSTATE6 0xc001006A
> -#define MSR_K8_PSTATE7 0xc001006B
> -#define MSR_K8_ENABLE_C1E 0xc0010055
> -#define MSR_K8_VM_HSAVE_PA 0xc0010117
> -
> -#define MSR_AMD_FAM15H_EVNTSEL0 0xc0010200
> -#define MSR_AMD_FAM15H_PERFCTR0 0xc0010201
> -#define MSR_AMD_FAM15H_EVNTSEL1 0xc0010202
> -#define MSR_AMD_FAM15H_PERFCTR1 0xc0010203
> -#define MSR_AMD_FAM15H_EVNTSEL2 0xc0010204
> -#define MSR_AMD_FAM15H_PERFCTR2 0xc0010205
> -#define MSR_AMD_FAM15H_EVNTSEL3 0xc0010206
> -#define MSR_AMD_FAM15H_PERFCTR3 0xc0010207
> -#define MSR_AMD_FAM15H_EVNTSEL4 0xc0010208
> -#define MSR_AMD_FAM15H_PERFCTR4 0xc0010209
> -#define MSR_AMD_FAM15H_EVNTSEL5 0xc001020a
> -#define MSR_AMD_FAM15H_PERFCTR5 0xc001020b
> -
> -#define MSR_AMD_L7S0_FEATURE_MASK 0xc0011002
> -#define MSR_AMD_THRM_FEATURE_MASK 0xc0011003
> -#define MSR_K8_FEATURE_MASK 0xc0011004
> -#define MSR_K8_EXT_FEATURE_MASK 0xc0011005
> +#define MSR_K7_FID_VID_CTL 0xc0010041U
> +#define MSR_K7_FID_VID_STATUS 0xc0010042U
> +#define MSR_K8_PSTATE_LIMIT 0xc0010061U
> +#define MSR_K8_PSTATE_CTRL 0xc0010062U
> +#define MSR_K8_PSTATE_STATUS 0xc0010063U
> +#define MSR_K8_PSTATE0 0xc0010064U
> +#define MSR_K8_PSTATE1 0xc0010065U
> +#define MSR_K8_PSTATE2 0xc0010066U
> +#define MSR_K8_PSTATE3 0xc0010067U
> +#define MSR_K8_PSTATE4 0xc0010068U
> +#define MSR_K8_PSTATE5 0xc0010069U
> +#define MSR_K8_PSTATE6 0xc001006AU
> +#define MSR_K8_PSTATE7 0xc001006BU
> +#define MSR_K8_ENABLE_C1E 0xc0010055U
> +#define MSR_K8_VM_HSAVE_PA 0xc0010117U
> +
> +#define MSR_AMD_FAM15H_EVNTSEL0 0xc0010200U
> +#define MSR_AMD_FAM15H_PERFCTR0 0xc0010201U
> +#define MSR_AMD_FAM15H_EVNTSEL1 0xc0010202U
> +#define MSR_AMD_FAM15H_PERFCTR1 0xc0010203U
> +#define MSR_AMD_FAM15H_EVNTSEL2 0xc0010204U
> +#define MSR_AMD_FAM15H_PERFCTR2 0xc0010205U
> +#define MSR_AMD_FAM15H_EVNTSEL3 0xc0010206U
> +#define MSR_AMD_FAM15H_PERFCTR3 0xc0010207U
> +#define MSR_AMD_FAM15H_EVNTSEL4 0xc0010208U
> +#define MSR_AMD_FAM15H_PERFCTR4 0xc0010209U
> +#define MSR_AMD_FAM15H_EVNTSEL5 0xc001020aU
> +#define MSR_AMD_FAM15H_PERFCTR5 0xc001020bU
> +
> +#define MSR_AMD_L7S0_FEATURE_MASK 0xc0011002U
> +#define MSR_AMD_THRM_FEATURE_MASK 0xc0011003U
> +#define MSR_K8_FEATURE_MASK 0xc0011004U
> +#define MSR_K8_EXT_FEATURE_MASK 0xc0011005U
>
> /* AMD64 MSRs */
> -#define MSR_AMD64_NB_CFG 0xc001001f
> +#define MSR_AMD64_NB_CFG 0xc001001fU
> #define AMD64_NB_CFG_CF8_EXT_ENABLE_BIT 46
> -#define MSR_AMD64_LS_CFG 0xc0011020
> -#define MSR_AMD64_IC_CFG 0xc0011021
> -#define MSR_AMD64_DC_CFG 0xc0011022
> -#define MSR_AMD64_DE_CFG 0xc0011029
> +#define MSR_AMD64_LS_CFG 0xc0011020U
> +#define MSR_AMD64_IC_CFG 0xc0011021U
> +#define MSR_AMD64_DC_CFG 0xc0011022U
> +#define MSR_AMD64_DE_CFG 0xc0011029U
> #define AMD64_DE_CFG_LFENCE_SERIALISE (_AC(1, ULL) << 1)
> -#define MSR_AMD64_EX_CFG 0xc001102c
> -#define MSR_AMD64_DE_CFG2 0xc00110e3
> +#define MSR_AMD64_EX_CFG 0xc001102cU
> +#define MSR_AMD64_DE_CFG2 0xc00110e3U
>
> -#define MSR_AMD64_DR0_ADDRESS_MASK 0xc0011027
> -#define MSR_AMD64_DR1_ADDRESS_MASK 0xc0011019
> -#define MSR_AMD64_DR2_ADDRESS_MASK 0xc001101a
> -#define MSR_AMD64_DR3_ADDRESS_MASK 0xc001101b
> +#define MSR_AMD64_DR0_ADDRESS_MASK 0xc0011027U
> +#define MSR_AMD64_DR1_ADDRESS_MASK 0xc0011019U
> +#define MSR_AMD64_DR2_ADDRESS_MASK 0xc001101aU
> +#define MSR_AMD64_DR3_ADDRESS_MASK 0xc001101bU
>
> /* AMD Family10h machine check MSRs */
> -#define MSR_F10_MC4_MISC1 0xc0000408
> -#define MSR_F10_MC4_MISC2 0xc0000409
> -#define MSR_F10_MC4_MISC3 0xc000040A
> +#define MSR_F10_MC4_MISC1 0xc0000408U
> +#define MSR_F10_MC4_MISC2 0xc0000409U
> +#define MSR_F10_MC4_MISC3 0xc000040AU
>
> /* AMD Family10h Bus Unit MSRs */
> -#define MSR_F10_BU_CFG 0xc0011023
> -#define MSR_F10_BU_CFG2 0xc001102a
> +#define MSR_F10_BU_CFG 0xc0011023U
> +#define MSR_F10_BU_CFG2 0xc001102aU
>
> /* Other AMD Fam10h MSRs */
> -#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
> +#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058U
> #define FAM10H_MMIO_CONF_ENABLE (1<<0)
> #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf
> #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
> @@ -429,22 +429,22 @@
>
> /* AMD Microcode MSRs */
> #define MSR_AMD_PATCHLEVEL 0x0000008b
> -#define MSR_AMD_PATCHLOADER 0xc0010020
> +#define MSR_AMD_PATCHLOADER 0xc0010020U
>
> /* AMD TSC RATE MSR */
> -#define MSR_AMD64_TSC_RATIO 0xc0000104
> +#define MSR_AMD64_TSC_RATIO 0xc0000104U
>
> /* AMD Lightweight Profiling MSRs */
> -#define MSR_AMD64_LWP_CFG 0xc0000105
> -#define MSR_AMD64_LWP_CBADDR 0xc0000106
> +#define MSR_AMD64_LWP_CFG 0xc0000105U
> +#define MSR_AMD64_LWP_CBADDR 0xc0000106U
>
> /* AMD OS Visible Workaround MSRs */
> -#define MSR_AMD_OSVW_ID_LENGTH 0xc0010140
> -#define MSR_AMD_OSVW_STATUS 0xc0010141
> +#define MSR_AMD_OSVW_ID_LENGTH 0xc0010140U
> +#define MSR_AMD_OSVW_STATUS 0xc0010141U
>
> /* AMD Protected Processor Inventory Number */
> -#define MSR_AMD_PPIN_CTL 0xc00102f0
> -#define MSR_AMD_PPIN 0xc00102f1
> +#define MSR_AMD_PPIN_CTL 0xc00102f0U
> +#define MSR_AMD_PPIN 0xc00102f1U
>
> /* VIA Cyrix defined MSRs*/
> #define MSR_VIA_FCR 0x00001107
> diff --git a/xen/arch/x86/include/asm/pci.h b/xen/arch/x86/include/asm/pci.h
> index f4a58c8acf..e1dd12eb19 100644
> --- a/xen/arch/x86/include/asm/pci.h
> +++ b/xen/arch/x86/include/asm/pci.h
> @@ -3,10 +3,10 @@
>
> #include <xen/mm.h>
>
> -#define CF8_BDF(cf8) ( ((cf8) & 0x00ffff00) >> 8)
> -#define CF8_ADDR_LO(cf8) ( (cf8) & 0x000000fc)
> -#define CF8_ADDR_HI(cf8) ( ((cf8) & 0x0f000000) >> 16)
> -#define CF8_ENABLED(cf8) (!!((cf8) & 0x80000000))
> +#define CF8_BDF(cf8) ( ((cf8) & 0x00ffff00U) >> 8)
> +#define CF8_ADDR_LO(cf8) ( (cf8) & 0x000000fcU)
> +#define CF8_ADDR_HI(cf8) ( ((cf8) & 0x0f000000U) >> 16)
> +#define CF8_ENABLED(cf8) (!!((cf8) & 0x80000000U))
>
> #define IS_SNB_GFX(id) (id == 0x01068086 || id == 0x01168086 \
> || id == 0x01268086 || id == 0x01028086 \
> diff --git a/xen/arch/x86/include/asm/x86-defns.h b/xen/arch/x86/include/asm/x86-defns.h
> index 5838631ef6..48d7a3b7af 100644
> --- a/xen/arch/x86/include/asm/x86-defns.h
> +++ b/xen/arch/x86/include/asm/x86-defns.h
> @@ -30,17 +30,17 @@
> /*
> * Intel CPU flags in CR0
> */
> -#define X86_CR0_PE 0x00000001 /* Enable Protected Mode (RW) */
> -#define X86_CR0_MP 0x00000002 /* Monitor Coprocessor (RW) */
> -#define X86_CR0_EM 0x00000004 /* Require FPU Emulation (RO) */
> -#define X86_CR0_TS 0x00000008 /* Task Switched (RW) */
> -#define X86_CR0_ET 0x00000010 /* Extension type (RO) */
> -#define X86_CR0_NE 0x00000020 /* Numeric Error Reporting (RW) */
> -#define X86_CR0_WP 0x00010000 /* Supervisor Write Protect (RW) */
> -#define X86_CR0_AM 0x00040000 /* Alignment Checking (RW) */
> -#define X86_CR0_NW 0x20000000 /* Not Write-Through (RW) */
> -#define X86_CR0_CD 0x40000000 /* Cache Disable (RW) */
> -#define X86_CR0_PG 0x80000000 /* Paging (RW) */
> +#define X86_CR0_PE _AC(0x00000001, UL) /* Enable Protected Mode (RW) */
> +#define X86_CR0_MP _AC(0x00000002, UL) /* Monitor Coprocessor (RW) */
> +#define X86_CR0_EM _AC(0x00000004, UL) /* Require FPU Emulation (RO) */
> +#define X86_CR0_TS _AC(0x00000008, UL) /* Task Switched (RW) */
> +#define X86_CR0_ET _AC(0x00000010, UL) /* Extension type (RO) */
> +#define X86_CR0_NE _AC(0x00000020, UL) /* Numeric Error Reporting (RW) */
> +#define X86_CR0_WP _AC(0x00010000, UL) /* Supervisor Write Protect (RW) */
> +#define X86_CR0_AM _AC(0x00040000, UL) /* Alignment Checking (RW) */
> +#define X86_CR0_NW _AC(0x20000000, UL) /* Not Write-Through (RW) */
> +#define X86_CR0_CD _AC(0x40000000, UL) /* Cache Disable (RW) */
> +#define X86_CR0_PG _AC(0x80000000, UL) /* Paging (RW) */
While "UL" here instead of "U"? They are all 32-bit values.
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [XEN PATCH v7 3/4] x86/include: address violations of MISRA C:2012 Rule 7.2
2023-09-28 22:58 ` Stefano Stabellini
@ 2023-09-29 7:46 ` Simone Ballarin
2023-09-29 18:34 ` Stefano Stabellini
0 siblings, 1 reply; 9+ messages in thread
From: Simone Ballarin @ 2023-09-29 7:46 UTC (permalink / raw)
To: Stefano Stabellini
Cc: xen-devel, consulting, jbeulich, Andrew Cooper,
Roger Pau Monné, Wei Liu, Gianluca Luparini
On 29/09/23 00:58, Stefano Stabellini wrote:
> On Thu, 28 Sep 2023, Simone Ballarin wrote:
>> The xen sources contains violations of MISRA C:2012 Rule 7.2 whose
>> headline states:
>> "A 'u' or 'U' suffix shall be applied to all integer constants
>> that are represented in an unsigned type".
>>
>> Add the 'U' suffix to integers literals with unsigned type.
>> Use _AC() for macro costants that are used also in assembly files.
>>
>> For the sake of uniformity, the following changes are made:
>> - add the 'U' suffix to macros in 'pci.h'
>> - use _AC() for macros near 'X86_CR0_PG'
>>
>> Signed-off-by: Gianluca Luparini <gianluca.luparini@bugseng.com>
>> Signed-off-by: Simone Ballarin <simone.ballarin@bugseng.com>
>> ---
>> Changes in v7:
>> - switch order of Signed-off-by tags
>> - change tag from x86/arm to x86/include
>> Changes in v6:
>> - new patch obtained by splitting ASM related changes from
>> "xen/x86: address violations of MISRA C:2012 Rule 7.2 (v5)"
>> - use UL suffix for X86_CR0_* macros
>> ---
>> xen/arch/x86/include/asm/apicdef.h | 2 +-
>> xen/arch/x86/include/asm/config.h | 2 +-
>> xen/arch/x86/include/asm/hpet.h | 2 +-
>> xen/arch/x86/include/asm/msi.h | 2 +-
>> xen/arch/x86/include/asm/msr-index.h | 182 +++++++++++++--------------
>> xen/arch/x86/include/asm/pci.h | 8 +-
>> xen/arch/x86/include/asm/x86-defns.h | 22 ++--
>> 7 files changed, 110 insertions(+), 110 deletions(-)
>>
>> diff --git a/xen/arch/x86/include/asm/apicdef.h b/xen/arch/x86/include/asm/apicdef.h
>> index a261436993..8d1b0087d4 100644
>> --- a/xen/arch/x86/include/asm/apicdef.h
>> +++ b/xen/arch/x86/include/asm/apicdef.h
>> @@ -8,7 +8,7 @@
>> * Ingo Molnar <mingo@redhat.com>, 1999, 2000
>> */
>>
>> -#define APIC_DEFAULT_PHYS_BASE 0xfee00000
>> +#define APIC_DEFAULT_PHYS_BASE 0xfee00000U
>>
>> #define APIC_ID 0x20
>> #define APIC_ID_MASK (0xFFu<<24)
>> diff --git a/xen/arch/x86/include/asm/config.h b/xen/arch/x86/include/asm/config.h
>> index fbc4bb3416..bbced338be 100644
>> --- a/xen/arch/x86/include/asm/config.h
>> +++ b/xen/arch/x86/include/asm/config.h
>> @@ -257,7 +257,7 @@ extern unsigned char boot_edid_info[128];
>> #endif /* CONFIG_PV32 */
>>
>> #define MACH2PHYS_COMPAT_VIRT_START HYPERVISOR_COMPAT_VIRT_START
>> -#define MACH2PHYS_COMPAT_VIRT_END 0xFFE00000
>> +#define MACH2PHYS_COMPAT_VIRT_END 0xFFE00000U
>> #define MACH2PHYS_COMPAT_NR_ENTRIES(d) \
>> ((MACH2PHYS_COMPAT_VIRT_END-MACH2PHYS_COMPAT_VIRT_START(d))>>2)
>>
>> diff --git a/xen/arch/x86/include/asm/hpet.h b/xen/arch/x86/include/asm/hpet.h
>> index 9919f74730..c5e8e9c8db 100644
>> --- a/xen/arch/x86/include/asm/hpet.h
>> +++ b/xen/arch/x86/include/asm/hpet.h
>> @@ -41,7 +41,7 @@
>> #define HPET_TN_ROUTE 0x3e00
>> #define HPET_TN_FSB 0x4000
>> #define HPET_TN_FSB_CAP 0x8000
>> -#define HPET_TN_RESERVED 0xffff0081
>> +#define HPET_TN_RESERVED 0xffff0081U
>> #define HPET_TN_INT_ROUTE_CAP (0xffffffffULL << 32)
>>
>>
>> diff --git a/xen/arch/x86/include/asm/msi.h b/xen/arch/x86/include/asm/msi.h
>> index a53ade95c9..d89723d009 100644
>> --- a/xen/arch/x86/include/asm/msi.h
>> +++ b/xen/arch/x86/include/asm/msi.h
>> @@ -37,7 +37,7 @@
>> */
>>
>> #define MSI_ADDR_BASE_HI 0
>> -#define MSI_ADDR_BASE_LO 0xfee00000
>> +#define MSI_ADDR_BASE_LO 0xfee00000U
>> #define MSI_ADDR_BASE_MASK (~0xfffff)
>> #define MSI_ADDR_HEADER MSI_ADDR_BASE_LO
>>
>> diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h
>> index 11ffed543a..718f8f860d 100644
>> --- a/xen/arch/x86/include/asm/msr-index.h
>> +++ b/xen/arch/x86/include/asm/msr-index.h
>> @@ -22,7 +22,7 @@
>> #define APIC_BASE_BSP (_AC(1, ULL) << 8)
>> #define APIC_BASE_EXTD (_AC(1, ULL) << 10)
>> #define APIC_BASE_ENABLE (_AC(1, ULL) << 11)
>> -#define APIC_BASE_ADDR_MASK 0x000ffffffffff000ULL
>> +#define APIC_BASE_ADDR_MASK _AC(0x000ffffffffff000, ULL)
>
> This is not used by assembly code?
>
>
>> #define MSR_TEST_CTRL 0x00000033
>> #define TEST_CTRL_SPLITLOCK_DETECT (_AC(1, ULL) << 29)
>> @@ -30,7 +30,7 @@
>>
>> #define MSR_INTEL_CORE_THREAD_COUNT 0x00000035
>> #define MSR_CTC_THREAD_MASK 0x0000ffff
>> -#define MSR_CTC_CORE_MASK 0xffff0000
>> +#define MSR_CTC_CORE_MASK _AC(0xffff0000, U)
>
> Also this one is not?
>
>
>> #define MSR_SPEC_CTRL 0x00000048
>> #define SPEC_CTRL_IBRS (_AC(1, ULL) << 0)
>> @@ -186,7 +186,7 @@
>> #define MSR_UARCH_MISC_CTRL 0x00001b01
>> #define UARCH_CTRL_DOITM (_AC(1, ULL) << 0)
>>
>> -#define MSR_EFER 0xc0000080 /* Extended Feature Enable Register */
>> +#define MSR_EFER _AC(0xc0000080, U) /* Extended Feature Enable Register */
>> #define EFER_SCE (_AC(1, ULL) << 0) /* SYSCALL Enable */
>> #define EFER_LME (_AC(1, ULL) << 8) /* Long Mode Enable */
>> #define EFER_LMA (_AC(1, ULL) << 10) /* Long Mode Active */
>> @@ -199,35 +199,35 @@
>> (EFER_SCE | EFER_LME | EFER_LMA | EFER_NXE | EFER_SVME | EFER_FFXSE | \
>> EFER_AIBRSE)
>>
>> -#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
>> -#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
>> -#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
>> -#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
>> -#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
>> -#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
>> -#define MSR_SHADOW_GS_BASE 0xc0000102 /* SwapGS GS shadow */
>> -#define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */
>> +#define MSR_STAR _AC(0xc0000081, U) /* legacy mode SYSCALL target */
>> +#define MSR_LSTAR _AC(0xc0000082, U) /* long mode SYSCALL target */
>> +#define MSR_CSTAR _AC(0xc0000083, U) /* compat mode SYSCALL target */
>> +#define MSR_SYSCALL_MASK _AC(0xc0000084, U) /* EFLAGS mask for syscall */
>> +#define MSR_FS_BASE _AC(0xc0000100, U) /* 64bit FS base */
>> +#define MSR_GS_BASE _AC(0xc0000101, U) /* 64bit GS base */
>> +#define MSR_SHADOW_GS_BASE _AC(0xc0000102, U) /* SwapGS GS shadow */
>> +#define MSR_TSC_AUX _AC(0xc0000103, U) /* Auxiliary TSC */
>
> None of these set seems to be used by assembly code
>
>
>> -#define MSR_K8_SYSCFG 0xc0010010
>> +#define MSR_K8_SYSCFG _AC(0xc0010010, U)
>
> This one also is not?
>
>
>> #define SYSCFG_MTRR_FIX_DRAM_EN (_AC(1, ULL) << 18)
>> #define SYSCFG_MTRR_FIX_DRAM_MOD_EN (_AC(1, ULL) << 19)
>> #define SYSCFG_MTRR_VAR_DRAM_EN (_AC(1, ULL) << 20)
>> #define SYSCFG_MTRR_TOM2_EN (_AC(1, ULL) << 21)
>> #define SYSCFG_TOM2_FORCE_WB (_AC(1, ULL) << 22)
>>
>> -#define MSR_K8_IORR_BASE0 0xc0010016
>> -#define MSR_K8_IORR_MASK0 0xc0010017
>> -#define MSR_K8_IORR_BASE1 0xc0010018
>> -#define MSR_K8_IORR_MASK1 0xc0010019
>> +#define MSR_K8_IORR_BASE0 _AC(0xc0010016, U)
>> +#define MSR_K8_IORR_MASK0 _AC(0xc0010017, U)
>> +#define MSR_K8_IORR_BASE1 _AC(0xc0010018, U)
>> +#define MSR_K8_IORR_MASK1 _AC(0xc0010019, U)
>
> These ones are not?
>
>
>> -#define MSR_K8_TSEG_BASE 0xc0010112 /* AMD doc: SMMAddr */
>> -#define MSR_K8_TSEG_MASK 0xc0010113 /* AMD doc: SMMMask */
>> +#define MSR_K8_TSEG_BASE _AC(0xc0010112, U) /* AMD doc: SMMAddr */
>> +#define MSR_K8_TSEG_MASK _AC(0xc0010113, U) /* AMD doc: SMMMask */
>
> These ones are not?
>
>>
>> -#define MSR_K8_VM_CR 0xc0010114
>> +#define MSR_K8_VM_CR _AC(0xc0010114, U)
>
> Also this one
>
>
>> #define VM_CR_INIT_REDIRECTION (_AC(1, ULL) << 1)
>> #define VM_CR_SVM_DISABLE (_AC(1, ULL) << 4)
>>
>> -#define MSR_VIRT_SPEC_CTRL 0xc001011f /* Layout matches MSR_SPEC_CTRL */
>> +#define MSR_VIRT_SPEC_CTRL _AC(0xc001011f, U) /* Layout matches MSR_SPEC_CTRL */
>
> And this one.
>
> What am I missing? Did you also add _AC to all the places where the
> constants end up being used in asm inline? Because I don't think that
> asm inline needs the _AC...
Initially I've used _AC only when strictly required, then I've received
the following comment
(https://lists.xenproject.org/archives/html/xen-devel/2023-08/msg02207.html):
I understand you use _AC() here because the constant is used in
assembly code. But I don't understand why you use it only here,
and not throughout at least the "modern" portion of the file. I
wonder what other x86 maintainers think about this.
>
>
>> #define MSR_AMD_CSTATE_CFG 0xc0010296
>>
>> @@ -313,7 +313,7 @@
>> #define CMCI_EN (1UL<<30)
>> #define CMCI_THRESHOLD_MASK 0x7FFF
>>
>> -#define MSR_AMD64_MC0_MASK 0xc0010044
>> +#define MSR_AMD64_MC0_MASK 0xc0010044U
>>
>> #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
>> #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x))
>> @@ -345,82 +345,82 @@
>>
>> /* K7/K8 MSRs. Not complete. See the architecture manual for a more
>> complete list. */
>> -#define MSR_K7_EVNTSEL0 0xc0010000
>> -#define MSR_K7_PERFCTR0 0xc0010004
>> -#define MSR_K7_EVNTSEL1 0xc0010001
>> -#define MSR_K7_PERFCTR1 0xc0010005
>> -#define MSR_K7_EVNTSEL2 0xc0010002
>> -#define MSR_K7_PERFCTR2 0xc0010006
>> -#define MSR_K7_EVNTSEL3 0xc0010003
>> -#define MSR_K7_PERFCTR3 0xc0010007
>> -#define MSR_K8_TOP_MEM1 0xc001001a
>> -#define MSR_K8_TOP_MEM2 0xc001001d
>> -
>> -#define MSR_K8_HWCR 0xc0010015
>> +#define MSR_K7_EVNTSEL0 0xc0010000U
>> +#define MSR_K7_PERFCTR0 0xc0010004U
>> +#define MSR_K7_EVNTSEL1 0xc0010001U
>> +#define MSR_K7_PERFCTR1 0xc0010005U
>> +#define MSR_K7_EVNTSEL2 0xc0010002U
>> +#define MSR_K7_PERFCTR2 0xc0010006U
>> +#define MSR_K7_EVNTSEL3 0xc0010003U
>> +#define MSR_K7_PERFCTR3 0xc0010007U
>> +#define MSR_K8_TOP_MEM1 0xc001001aU
>> +#define MSR_K8_TOP_MEM2 0xc001001dU
>> +
>> +#define MSR_K8_HWCR 0xc0010015U
>> #define K8_HWCR_TSC_FREQ_SEL (1ULL << 24)
>> #define K8_HWCR_CPUID_USER_DIS (1ULL << 35)
>>
>> -#define MSR_K7_FID_VID_CTL 0xc0010041
>> -#define MSR_K7_FID_VID_STATUS 0xc0010042
>> -#define MSR_K8_PSTATE_LIMIT 0xc0010061
>> -#define MSR_K8_PSTATE_CTRL 0xc0010062
>> -#define MSR_K8_PSTATE_STATUS 0xc0010063
>> -#define MSR_K8_PSTATE0 0xc0010064
>> -#define MSR_K8_PSTATE1 0xc0010065
>> -#define MSR_K8_PSTATE2 0xc0010066
>> -#define MSR_K8_PSTATE3 0xc0010067
>> -#define MSR_K8_PSTATE4 0xc0010068
>> -#define MSR_K8_PSTATE5 0xc0010069
>> -#define MSR_K8_PSTATE6 0xc001006A
>> -#define MSR_K8_PSTATE7 0xc001006B
>> -#define MSR_K8_ENABLE_C1E 0xc0010055
>> -#define MSR_K8_VM_HSAVE_PA 0xc0010117
>> -
>> -#define MSR_AMD_FAM15H_EVNTSEL0 0xc0010200
>> -#define MSR_AMD_FAM15H_PERFCTR0 0xc0010201
>> -#define MSR_AMD_FAM15H_EVNTSEL1 0xc0010202
>> -#define MSR_AMD_FAM15H_PERFCTR1 0xc0010203
>> -#define MSR_AMD_FAM15H_EVNTSEL2 0xc0010204
>> -#define MSR_AMD_FAM15H_PERFCTR2 0xc0010205
>> -#define MSR_AMD_FAM15H_EVNTSEL3 0xc0010206
>> -#define MSR_AMD_FAM15H_PERFCTR3 0xc0010207
>> -#define MSR_AMD_FAM15H_EVNTSEL4 0xc0010208
>> -#define MSR_AMD_FAM15H_PERFCTR4 0xc0010209
>> -#define MSR_AMD_FAM15H_EVNTSEL5 0xc001020a
>> -#define MSR_AMD_FAM15H_PERFCTR5 0xc001020b
>> -
>> -#define MSR_AMD_L7S0_FEATURE_MASK 0xc0011002
>> -#define MSR_AMD_THRM_FEATURE_MASK 0xc0011003
>> -#define MSR_K8_FEATURE_MASK 0xc0011004
>> -#define MSR_K8_EXT_FEATURE_MASK 0xc0011005
>> +#define MSR_K7_FID_VID_CTL 0xc0010041U
>> +#define MSR_K7_FID_VID_STATUS 0xc0010042U
>> +#define MSR_K8_PSTATE_LIMIT 0xc0010061U
>> +#define MSR_K8_PSTATE_CTRL 0xc0010062U
>> +#define MSR_K8_PSTATE_STATUS 0xc0010063U
>> +#define MSR_K8_PSTATE0 0xc0010064U
>> +#define MSR_K8_PSTATE1 0xc0010065U
>> +#define MSR_K8_PSTATE2 0xc0010066U
>> +#define MSR_K8_PSTATE3 0xc0010067U
>> +#define MSR_K8_PSTATE4 0xc0010068U
>> +#define MSR_K8_PSTATE5 0xc0010069U
>> +#define MSR_K8_PSTATE6 0xc001006AU
>> +#define MSR_K8_PSTATE7 0xc001006BU
>> +#define MSR_K8_ENABLE_C1E 0xc0010055U
>> +#define MSR_K8_VM_HSAVE_PA 0xc0010117U
>> +
>> +#define MSR_AMD_FAM15H_EVNTSEL0 0xc0010200U
>> +#define MSR_AMD_FAM15H_PERFCTR0 0xc0010201U
>> +#define MSR_AMD_FAM15H_EVNTSEL1 0xc0010202U
>> +#define MSR_AMD_FAM15H_PERFCTR1 0xc0010203U
>> +#define MSR_AMD_FAM15H_EVNTSEL2 0xc0010204U
>> +#define MSR_AMD_FAM15H_PERFCTR2 0xc0010205U
>> +#define MSR_AMD_FAM15H_EVNTSEL3 0xc0010206U
>> +#define MSR_AMD_FAM15H_PERFCTR3 0xc0010207U
>> +#define MSR_AMD_FAM15H_EVNTSEL4 0xc0010208U
>> +#define MSR_AMD_FAM15H_PERFCTR4 0xc0010209U
>> +#define MSR_AMD_FAM15H_EVNTSEL5 0xc001020aU
>> +#define MSR_AMD_FAM15H_PERFCTR5 0xc001020bU
>> +
>> +#define MSR_AMD_L7S0_FEATURE_MASK 0xc0011002U
>> +#define MSR_AMD_THRM_FEATURE_MASK 0xc0011003U
>> +#define MSR_K8_FEATURE_MASK 0xc0011004U
>> +#define MSR_K8_EXT_FEATURE_MASK 0xc0011005U
>>
>> /* AMD64 MSRs */
>> -#define MSR_AMD64_NB_CFG 0xc001001f
>> +#define MSR_AMD64_NB_CFG 0xc001001fU
>> #define AMD64_NB_CFG_CF8_EXT_ENABLE_BIT 46
>> -#define MSR_AMD64_LS_CFG 0xc0011020
>> -#define MSR_AMD64_IC_CFG 0xc0011021
>> -#define MSR_AMD64_DC_CFG 0xc0011022
>> -#define MSR_AMD64_DE_CFG 0xc0011029
>> +#define MSR_AMD64_LS_CFG 0xc0011020U
>> +#define MSR_AMD64_IC_CFG 0xc0011021U
>> +#define MSR_AMD64_DC_CFG 0xc0011022U
>> +#define MSR_AMD64_DE_CFG 0xc0011029U
>> #define AMD64_DE_CFG_LFENCE_SERIALISE (_AC(1, ULL) << 1)
>> -#define MSR_AMD64_EX_CFG 0xc001102c
>> -#define MSR_AMD64_DE_CFG2 0xc00110e3
>> +#define MSR_AMD64_EX_CFG 0xc001102cU
>> +#define MSR_AMD64_DE_CFG2 0xc00110e3U
>>
>> -#define MSR_AMD64_DR0_ADDRESS_MASK 0xc0011027
>> -#define MSR_AMD64_DR1_ADDRESS_MASK 0xc0011019
>> -#define MSR_AMD64_DR2_ADDRESS_MASK 0xc001101a
>> -#define MSR_AMD64_DR3_ADDRESS_MASK 0xc001101b
>> +#define MSR_AMD64_DR0_ADDRESS_MASK 0xc0011027U
>> +#define MSR_AMD64_DR1_ADDRESS_MASK 0xc0011019U
>> +#define MSR_AMD64_DR2_ADDRESS_MASK 0xc001101aU
>> +#define MSR_AMD64_DR3_ADDRESS_MASK 0xc001101bU
>>
>> /* AMD Family10h machine check MSRs */
>> -#define MSR_F10_MC4_MISC1 0xc0000408
>> -#define MSR_F10_MC4_MISC2 0xc0000409
>> -#define MSR_F10_MC4_MISC3 0xc000040A
>> +#define MSR_F10_MC4_MISC1 0xc0000408U
>> +#define MSR_F10_MC4_MISC2 0xc0000409U
>> +#define MSR_F10_MC4_MISC3 0xc000040AU
>>
>> /* AMD Family10h Bus Unit MSRs */
>> -#define MSR_F10_BU_CFG 0xc0011023
>> -#define MSR_F10_BU_CFG2 0xc001102a
>> +#define MSR_F10_BU_CFG 0xc0011023U
>> +#define MSR_F10_BU_CFG2 0xc001102aU
>>
>> /* Other AMD Fam10h MSRs */
>> -#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
>> +#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058U
>> #define FAM10H_MMIO_CONF_ENABLE (1<<0)
>> #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf
>> #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
>> @@ -429,22 +429,22 @@
>>
>> /* AMD Microcode MSRs */
>> #define MSR_AMD_PATCHLEVEL 0x0000008b
>> -#define MSR_AMD_PATCHLOADER 0xc0010020
>> +#define MSR_AMD_PATCHLOADER 0xc0010020U
>>
>> /* AMD TSC RATE MSR */
>> -#define MSR_AMD64_TSC_RATIO 0xc0000104
>> +#define MSR_AMD64_TSC_RATIO 0xc0000104U
>>
>> /* AMD Lightweight Profiling MSRs */
>> -#define MSR_AMD64_LWP_CFG 0xc0000105
>> -#define MSR_AMD64_LWP_CBADDR 0xc0000106
>> +#define MSR_AMD64_LWP_CFG 0xc0000105U
>> +#define MSR_AMD64_LWP_CBADDR 0xc0000106U
>>
>> /* AMD OS Visible Workaround MSRs */
>> -#define MSR_AMD_OSVW_ID_LENGTH 0xc0010140
>> -#define MSR_AMD_OSVW_STATUS 0xc0010141
>> +#define MSR_AMD_OSVW_ID_LENGTH 0xc0010140U
>> +#define MSR_AMD_OSVW_STATUS 0xc0010141U
>>
>> /* AMD Protected Processor Inventory Number */
>> -#define MSR_AMD_PPIN_CTL 0xc00102f0
>> -#define MSR_AMD_PPIN 0xc00102f1
>> +#define MSR_AMD_PPIN_CTL 0xc00102f0U
>> +#define MSR_AMD_PPIN 0xc00102f1U
>>
>> /* VIA Cyrix defined MSRs*/
>> #define MSR_VIA_FCR 0x00001107
>> diff --git a/xen/arch/x86/include/asm/pci.h b/xen/arch/x86/include/asm/pci.h
>> index f4a58c8acf..e1dd12eb19 100644
>> --- a/xen/arch/x86/include/asm/pci.h
>> +++ b/xen/arch/x86/include/asm/pci.h
>> @@ -3,10 +3,10 @@
>>
>> #include <xen/mm.h>
>>
>> -#define CF8_BDF(cf8) ( ((cf8) & 0x00ffff00) >> 8)
>> -#define CF8_ADDR_LO(cf8) ( (cf8) & 0x000000fc)
>> -#define CF8_ADDR_HI(cf8) ( ((cf8) & 0x0f000000) >> 16)
>> -#define CF8_ENABLED(cf8) (!!((cf8) & 0x80000000))
>> +#define CF8_BDF(cf8) ( ((cf8) & 0x00ffff00U) >> 8)
>> +#define CF8_ADDR_LO(cf8) ( (cf8) & 0x000000fcU)
>> +#define CF8_ADDR_HI(cf8) ( ((cf8) & 0x0f000000U) >> 16)
>> +#define CF8_ENABLED(cf8) (!!((cf8) & 0x80000000U))
>>
>> #define IS_SNB_GFX(id) (id == 0x01068086 || id == 0x01168086 \
>> || id == 0x01268086 || id == 0x01028086 \
>> diff --git a/xen/arch/x86/include/asm/x86-defns.h b/xen/arch/x86/include/asm/x86-defns.h
>> index 5838631ef6..48d7a3b7af 100644
>> --- a/xen/arch/x86/include/asm/x86-defns.h
>> +++ b/xen/arch/x86/include/asm/x86-defns.h
>> @@ -30,17 +30,17 @@
>> /*
>> * Intel CPU flags in CR0
>> */
>> -#define X86_CR0_PE 0x00000001 /* Enable Protected Mode (RW) */
>> -#define X86_CR0_MP 0x00000002 /* Monitor Coprocessor (RW) */
>> -#define X86_CR0_EM 0x00000004 /* Require FPU Emulation (RO) */
>> -#define X86_CR0_TS 0x00000008 /* Task Switched (RW) */
>> -#define X86_CR0_ET 0x00000010 /* Extension type (RO) */
>> -#define X86_CR0_NE 0x00000020 /* Numeric Error Reporting (RW) */
>> -#define X86_CR0_WP 0x00010000 /* Supervisor Write Protect (RW) */
>> -#define X86_CR0_AM 0x00040000 /* Alignment Checking (RW) */
>> -#define X86_CR0_NW 0x20000000 /* Not Write-Through (RW) */
>> -#define X86_CR0_CD 0x40000000 /* Cache Disable (RW) */
>> -#define X86_CR0_PG 0x80000000 /* Paging (RW) */
>> +#define X86_CR0_PE _AC(0x00000001, UL) /* Enable Protected Mode (RW) */
>> +#define X86_CR0_MP _AC(0x00000002, UL) /* Monitor Coprocessor (RW) */
>> +#define X86_CR0_EM _AC(0x00000004, UL) /* Require FPU Emulation (RO) */
>> +#define X86_CR0_TS _AC(0x00000008, UL) /* Task Switched (RW) */
>> +#define X86_CR0_ET _AC(0x00000010, UL) /* Extension type (RO) */
>> +#define X86_CR0_NE _AC(0x00000020, UL) /* Numeric Error Reporting (RW) */
>> +#define X86_CR0_WP _AC(0x00010000, UL) /* Supervisor Write Protect (RW) */
>> +#define X86_CR0_AM _AC(0x00040000, UL) /* Alignment Checking (RW) */
>> +#define X86_CR0_NW _AC(0x20000000, UL) /* Not Write-Through (RW) */
>> +#define X86_CR0_CD _AC(0x40000000, UL) /* Cache Disable (RW) */
>> +#define X86_CR0_PG _AC(0x80000000, UL) /* Paging (RW) */
>
> While "UL" here instead of "U"? They are all 32-bit values.
Initially U was used, then I've received the following indication
(https://lists.xenproject.org/archives/html/xen-devel/2023-08/msg02308.html):
CR0 being a 64-bit register, I consider this risky. Imo either
UL needs to be used as suffix, or the change needs limiting to
just PG (and even then perhaps better using UL).
--
Simone Ballarin, M.Sc.
Field Application Engineer, BUGSENG (https://bugseng.com)
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [XEN PATCH v7 3/4] x86/include: address violations of MISRA C:2012 Rule 7.2
2023-09-29 7:46 ` Simone Ballarin
@ 2023-09-29 18:34 ` Stefano Stabellini
0 siblings, 0 replies; 9+ messages in thread
From: Stefano Stabellini @ 2023-09-29 18:34 UTC (permalink / raw)
To: Simone Ballarin
Cc: Stefano Stabellini, xen-devel, consulting, jbeulich,
Andrew Cooper, Roger Pau Monné, Wei Liu, Gianluca Luparini
On Fri, 29 Sep 2023, Simone Ballarin wrote:
> On 29/09/23 00:58, Stefano Stabellini wrote:
> > On Thu, 28 Sep 2023, Simone Ballarin wrote:
> > > The xen sources contains violations of MISRA C:2012 Rule 7.2 whose
> > > headline states:
> > > "A 'u' or 'U' suffix shall be applied to all integer constants
> > > that are represented in an unsigned type".
> > >
> > > Add the 'U' suffix to integers literals with unsigned type.
> > > Use _AC() for macro costants that are used also in assembly files.
> > >
> > > For the sake of uniformity, the following changes are made:
> > > - add the 'U' suffix to macros in 'pci.h'
> > > - use _AC() for macros near 'X86_CR0_PG'
> > >
> > > Signed-off-by: Gianluca Luparini <gianluca.luparini@bugseng.com>
> > > Signed-off-by: Simone Ballarin <simone.ballarin@bugseng.com>
> > > ---
> > > Changes in v7:
> > > - switch order of Signed-off-by tags
> > > - change tag from x86/arm to x86/include
> > > Changes in v6:
> > > - new patch obtained by splitting ASM related changes from
> > > "xen/x86: address violations of MISRA C:2012 Rule 7.2 (v5)"
> > > - use UL suffix for X86_CR0_* macros
> > > ---
> > > xen/arch/x86/include/asm/apicdef.h | 2 +-
> > > xen/arch/x86/include/asm/config.h | 2 +-
> > > xen/arch/x86/include/asm/hpet.h | 2 +-
> > > xen/arch/x86/include/asm/msi.h | 2 +-
> > > xen/arch/x86/include/asm/msr-index.h | 182 +++++++++++++--------------
> > > xen/arch/x86/include/asm/pci.h | 8 +-
> > > xen/arch/x86/include/asm/x86-defns.h | 22 ++--
> > > 7 files changed, 110 insertions(+), 110 deletions(-)
> > >
> > > diff --git a/xen/arch/x86/include/asm/apicdef.h
> > > b/xen/arch/x86/include/asm/apicdef.h
> > > index a261436993..8d1b0087d4 100644
> > > --- a/xen/arch/x86/include/asm/apicdef.h
> > > +++ b/xen/arch/x86/include/asm/apicdef.h
> > > @@ -8,7 +8,7 @@
> > > * Ingo Molnar <mingo@redhat.com>, 1999, 2000
> > > */
> > > -#define APIC_DEFAULT_PHYS_BASE 0xfee00000
> > > +#define APIC_DEFAULT_PHYS_BASE 0xfee00000U
> > > #define APIC_ID 0x20
> > > #define APIC_ID_MASK (0xFFu<<24)
> > > diff --git a/xen/arch/x86/include/asm/config.h
> > > b/xen/arch/x86/include/asm/config.h
> > > index fbc4bb3416..bbced338be 100644
> > > --- a/xen/arch/x86/include/asm/config.h
> > > +++ b/xen/arch/x86/include/asm/config.h
> > > @@ -257,7 +257,7 @@ extern unsigned char boot_edid_info[128];
> > > #endif /* CONFIG_PV32 */
> > > #define MACH2PHYS_COMPAT_VIRT_START HYPERVISOR_COMPAT_VIRT_START
> > > -#define MACH2PHYS_COMPAT_VIRT_END 0xFFE00000
> > > +#define MACH2PHYS_COMPAT_VIRT_END 0xFFE00000U
> > > #define MACH2PHYS_COMPAT_NR_ENTRIES(d) \
> > > ((MACH2PHYS_COMPAT_VIRT_END-MACH2PHYS_COMPAT_VIRT_START(d))>>2)
> > > diff --git a/xen/arch/x86/include/asm/hpet.h
> > > b/xen/arch/x86/include/asm/hpet.h
> > > index 9919f74730..c5e8e9c8db 100644
> > > --- a/xen/arch/x86/include/asm/hpet.h
> > > +++ b/xen/arch/x86/include/asm/hpet.h
> > > @@ -41,7 +41,7 @@
> > > #define HPET_TN_ROUTE 0x3e00
> > > #define HPET_TN_FSB 0x4000
> > > #define HPET_TN_FSB_CAP 0x8000
> > > -#define HPET_TN_RESERVED 0xffff0081
> > > +#define HPET_TN_RESERVED 0xffff0081U
> > > #define HPET_TN_INT_ROUTE_CAP (0xffffffffULL << 32)
> > > diff --git a/xen/arch/x86/include/asm/msi.h
> > > b/xen/arch/x86/include/asm/msi.h
> > > index a53ade95c9..d89723d009 100644
> > > --- a/xen/arch/x86/include/asm/msi.h
> > > +++ b/xen/arch/x86/include/asm/msi.h
> > > @@ -37,7 +37,7 @@
> > > */
> > > #define MSI_ADDR_BASE_HI 0
> > > -#define MSI_ADDR_BASE_LO 0xfee00000
> > > +#define MSI_ADDR_BASE_LO 0xfee00000U
> > > #define MSI_ADDR_BASE_MASK (~0xfffff)
> > > #define MSI_ADDR_HEADER MSI_ADDR_BASE_LO
> > > diff --git a/xen/arch/x86/include/asm/msr-index.h
> > > b/xen/arch/x86/include/asm/msr-index.h
> > > index 11ffed543a..718f8f860d 100644
> > > --- a/xen/arch/x86/include/asm/msr-index.h
> > > +++ b/xen/arch/x86/include/asm/msr-index.h
> > > @@ -22,7 +22,7 @@
> > > #define APIC_BASE_BSP (_AC(1, ULL) << 8)
> > > #define APIC_BASE_EXTD (_AC(1, ULL) << 10)
> > > #define APIC_BASE_ENABLE (_AC(1, ULL) << 11)
> > > -#define APIC_BASE_ADDR_MASK 0x000ffffffffff000ULL
> > > +#define APIC_BASE_ADDR_MASK _AC(0x000ffffffffff000, ULL)
> >
> > This is not used by assembly code?
> >
> >
> > > #define MSR_TEST_CTRL 0x00000033
> > > #define TEST_CTRL_SPLITLOCK_DETECT (_AC(1, ULL) << 29)
> > > @@ -30,7 +30,7 @@
> > > #define MSR_INTEL_CORE_THREAD_COUNT 0x00000035
> > > #define MSR_CTC_THREAD_MASK 0x0000ffff
> > > -#define MSR_CTC_CORE_MASK 0xffff0000
> > > +#define MSR_CTC_CORE_MASK _AC(0xffff0000, U)
> >
> > Also this one is not?
> >
> >
> > > #define MSR_SPEC_CTRL 0x00000048
> > > #define SPEC_CTRL_IBRS (_AC(1, ULL) << 0)
> > > @@ -186,7 +186,7 @@
> > > #define MSR_UARCH_MISC_CTRL 0x00001b01
> > > #define UARCH_CTRL_DOITM (_AC(1, ULL) << 0)
> > > -#define MSR_EFER 0xc0000080 /* Extended
> > > Feature Enable Register */
> > > +#define MSR_EFER _AC(0xc0000080, U) /*
> > > Extended Feature Enable Register */
> > > #define EFER_SCE (_AC(1, ULL) << 0) /*
> > > SYSCALL Enable */
> > > #define EFER_LME (_AC(1, ULL) << 8) /* Long
> > > Mode Enable */
> > > #define EFER_LMA (_AC(1, ULL) << 10) /* Long
> > > Mode Active */
> > > @@ -199,35 +199,35 @@
> > > (EFER_SCE | EFER_LME | EFER_LMA | EFER_NXE | EFER_SVME | EFER_FFXSE
> > > | \
> > > EFER_AIBRSE)
> > > -#define MSR_STAR 0xc0000081 /* legacy mode
> > > SYSCALL target */
> > > -#define MSR_LSTAR 0xc0000082 /* long mode
> > > SYSCALL target */
> > > -#define MSR_CSTAR 0xc0000083 /* compat mode
> > > SYSCALL target */
> > > -#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for
> > > syscall */
> > > -#define MSR_FS_BASE 0xc0000100 /* 64bit FS base
> > > */
> > > -#define MSR_GS_BASE 0xc0000101 /* 64bit GS base
> > > */
> > > -#define MSR_SHADOW_GS_BASE 0xc0000102 /* SwapGS GS
> > > shadow */
> > > -#define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC
> > > */
> > > +#define MSR_STAR _AC(0xc0000081, U) /* legacy
> > > mode SYSCALL target */
> > > +#define MSR_LSTAR _AC(0xc0000082, U) /* long
> > > mode SYSCALL target */
> > > +#define MSR_CSTAR _AC(0xc0000083, U) /* compat
> > > mode SYSCALL target */
> > > +#define MSR_SYSCALL_MASK _AC(0xc0000084, U) /* EFLAGS
> > > mask for syscall */
> > > +#define MSR_FS_BASE _AC(0xc0000100, U) /* 64bit
> > > FS base */
> > > +#define MSR_GS_BASE _AC(0xc0000101, U) /* 64bit
> > > GS base */
> > > +#define MSR_SHADOW_GS_BASE _AC(0xc0000102, U) /* SwapGS
> > > GS shadow */
> > > +#define MSR_TSC_AUX _AC(0xc0000103, U) /*
> > > Auxiliary TSC */
> >
> > None of these set seems to be used by assembly code
> >
> >
> > > -#define MSR_K8_SYSCFG 0xc0010010
> > > +#define MSR_K8_SYSCFG _AC(0xc0010010, U)
> >
> > This one also is not?
> >
> >
> > > #define SYSCFG_MTRR_FIX_DRAM_EN (_AC(1, ULL) << 18)
> > > #define SYSCFG_MTRR_FIX_DRAM_MOD_EN (_AC(1, ULL) << 19)
> > > #define SYSCFG_MTRR_VAR_DRAM_EN (_AC(1, ULL) << 20)
> > > #define SYSCFG_MTRR_TOM2_EN (_AC(1, ULL) << 21)
> > > #define SYSCFG_TOM2_FORCE_WB (_AC(1, ULL) << 22)
> > > -#define MSR_K8_IORR_BASE0 0xc0010016
> > > -#define MSR_K8_IORR_MASK0 0xc0010017
> > > -#define MSR_K8_IORR_BASE1 0xc0010018
> > > -#define MSR_K8_IORR_MASK1 0xc0010019
> > > +#define MSR_K8_IORR_BASE0 _AC(0xc0010016, U)
> > > +#define MSR_K8_IORR_MASK0 _AC(0xc0010017, U)
> > > +#define MSR_K8_IORR_BASE1 _AC(0xc0010018, U)
> > > +#define MSR_K8_IORR_MASK1 _AC(0xc0010019, U)
> >
> > These ones are not?
> >
> >
> > > -#define MSR_K8_TSEG_BASE 0xc0010112 /* AMD doc:
> > > SMMAddr */
> > > -#define MSR_K8_TSEG_MASK 0xc0010113 /* AMD doc:
> > > SMMMask */
> > > +#define MSR_K8_TSEG_BASE _AC(0xc0010112, U) /* AMD
> > > doc: SMMAddr */
> > > +#define MSR_K8_TSEG_MASK _AC(0xc0010113, U) /* AMD
> > > doc: SMMMask */
> >
> > These ones are not?
> >
> > > -#define MSR_K8_VM_CR 0xc0010114
> > > +#define MSR_K8_VM_CR _AC(0xc0010114, U)
> >
> > Also this one
> >
> >
> > > #define VM_CR_INIT_REDIRECTION (_AC(1, ULL) << 1)
> > > #define VM_CR_SVM_DISABLE (_AC(1, ULL) << 4)
> > > -#define MSR_VIRT_SPEC_CTRL 0xc001011f /* Layout
> > > matches MSR_SPEC_CTRL */
> > > +#define MSR_VIRT_SPEC_CTRL _AC(0xc001011f, U) /* Layout
> > > matches MSR_SPEC_CTRL */
> >
> > And this one.
> >
> > What am I missing? Did you also add _AC to all the places where the
> > constants end up being used in asm inline? Because I don't think that
> > asm inline needs the _AC...
>
> Initially I've used _AC only when strictly required, then I've received
> the following comment
> (https://lists.xenproject.org/archives/html/xen-devel/2023-08/msg02207.html):
>
> I understand you use _AC() here because the constant is used in
> assembly code. But I don't understand why you use it only here,
> and not throughout at least the "modern" portion of the file. I
> wonder what other x86 maintainers think about this.
Ah OK...
> > While "UL" here instead of "U"? They are all 32-bit values.
>
> Initially U was used, then I've received the following indication
> (https://lists.xenproject.org/archives/html/xen-devel/2023-08/msg02308.html):
>
> CR0 being a 64-bit register, I consider this risky. Imo either
> UL needs to be used as suffix, or the change needs limiting to
> just PG (and even then perhaps better using UL).
In that case, I'll leave it to you and from my perspective:
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [XEN PATCH v7 4/4] xen/x86: address violations of MISRA C:2012 Rule 7.2
2023-09-28 15:23 [XEN PATCH v7 0/4] xen/x86: address violations of MISRA C:2012 Rule 7.2 Simone Ballarin
` (2 preceding siblings ...)
2023-09-28 15:23 ` [XEN PATCH v7 3/4] x86/include: " Simone Ballarin
@ 2023-09-28 15:23 ` Simone Ballarin
2023-09-28 23:00 ` Stefano Stabellini
3 siblings, 1 reply; 9+ messages in thread
From: Simone Ballarin @ 2023-09-28 15:23 UTC (permalink / raw)
To: xen-devel
Cc: consulting, sstabellini, jbeulich, Simone Ballarin, Andrew Cooper,
Roger Pau Monné, Wei Liu, Gianluca Luparini
The xen sources contains violations of MISRA C:2012 Rule 7.2 whose
headline states:
"A 'u' or 'U' suffix shall be applied to all integer constants
that are represented in an unsigned type".
Add the 'U' suffix to integers literals with unsigned type.
For the sake of uniformity, the following change is made:
- add the 'U' suffix to switch cases in 'cpuid.c'
Signed-off-by: Gianluca Luparini <gianluca.luparini@bugseng.com>
Signed-off-by: Simone Ballarin <simone.ballarin@bugseng.com>
---
Changes in v7:
- change cast to long in a cast to unsigned long in INVALID_PERCPU_AREA
to match the type of the first operand
- add missing Signed-off-by tags
Changes in v6:
- new patch obtained by splitting X86 related changes from
"xen/x86: address violations of MISRA C:2012 Rule 7.2 (v5)"
---
xen/arch/x86/apic.c | 2 +-
xen/arch/x86/cpu-policy.c | 18 +++++++++---------
xen/arch/x86/cpuid.c | 8 ++++----
xen/arch/x86/extable.c | 2 +-
xen/arch/x86/percpu.c | 2 +-
xen/arch/x86/psr.c | 2 +-
xen/arch/x86/spec_ctrl.c | 12 ++++++------
7 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/xen/arch/x86/apic.c b/xen/arch/x86/apic.c
index f1264ce7ed..6a43d81d2a 100644
--- a/xen/arch/x86/apic.c
+++ b/xen/arch/x86/apic.c
@@ -1191,7 +1191,7 @@ static void __init calibrate_APIC_clock(void)
* Setup the APIC counter to maximum. There is no way the lapic
* can underflow in the 100ms detection time frame.
*/
- __setup_APIC_LVTT(0xffffffff);
+ __setup_APIC_LVTT(0xffffffffU);
bus_freq = calibrate_apic_timer();
if ( !bus_freq )
diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c
index 81e574390f..423932bc13 100644
--- a/xen/arch/x86/cpu-policy.c
+++ b/xen/arch/x86/cpu-policy.c
@@ -321,7 +321,7 @@ static void recalculate_misc(struct cpu_policy *p)
p->extd.vendor_edx = p->basic.vendor_edx;
p->extd.raw_fms = p->basic.raw_fms;
- p->extd.raw[0x1].b &= 0xff00ffff;
+ p->extd.raw[0x1].b &= 0xff00ffffU;
p->extd.e1d |= p->basic._1d & CPUID_COMMON_1D_FEATURES;
p->extd.raw[0x8].a &= 0x0000ffff; /* GuestMaxPhysAddr hidden. */
@@ -378,10 +378,10 @@ static void __init calculate_host_policy(void)
* this information.
*/
if ( cpu_has_lfence_dispatch )
- max_extd_leaf = max(max_extd_leaf, 0x80000021);
+ max_extd_leaf = max(max_extd_leaf, 0x80000021U);
- p->extd.max_leaf = 0x80000000 | min_t(uint32_t, max_extd_leaf & 0xffff,
- ARRAY_SIZE(p->extd.raw) - 1);
+ p->extd.max_leaf = 0x80000000U | min_t(uint32_t, max_extd_leaf & 0xffff,
+ ARRAY_SIZE(p->extd.raw) - 1);
x86_cpu_featureset_to_policy(boot_cpu_data.x86_capability, p);
recalculate_xstate(p);
@@ -793,11 +793,11 @@ void recalculate_cpuid_policy(struct domain *d)
p->basic.max_leaf = min(p->basic.max_leaf, max->basic.max_leaf);
p->feat.max_subleaf = min(p->feat.max_subleaf, max->feat.max_subleaf);
- p->extd.max_leaf = 0x80000000 | min(p->extd.max_leaf & 0xffff,
- ((p->x86_vendor & (X86_VENDOR_AMD |
- X86_VENDOR_HYGON))
- ? CPUID_GUEST_NR_EXTD_AMD
- : CPUID_GUEST_NR_EXTD_INTEL) - 1);
+ p->extd.max_leaf = 0x80000000U | min(p->extd.max_leaf & 0xffff,
+ ((p->x86_vendor & (X86_VENDOR_AMD |
+ X86_VENDOR_HYGON))
+ ? CPUID_GUEST_NR_EXTD_AMD
+ : CPUID_GUEST_NR_EXTD_INTEL) - 1);
x86_cpu_policy_to_featureset(p, fs);
x86_cpu_policy_to_featureset(max, max_fs);
diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c
index 455a09b2dd..7290a979c6 100644
--- a/xen/arch/x86/cpuid.c
+++ b/xen/arch/x86/cpuid.c
@@ -93,7 +93,7 @@ void guest_cpuid(const struct vcpu *v, uint32_t leaf,
}
break;
- case 0x40000000 ... 0x400000ff:
+ case 0x40000000U ... 0x400000ffU:
if ( is_viridian_domain(d) )
return cpuid_viridian_leaves(v, leaf, subleaf, res);
@@ -103,10 +103,10 @@ void guest_cpuid(const struct vcpu *v, uint32_t leaf,
* Intel reserve up until 0x4fffffff for hypervisor use. AMD reserve
* only until 0x400000ff, but we already use double that.
*/
- case 0x40000100 ... 0x400001ff:
+ case 0x40000100U ... 0x400001ffU:
return cpuid_hypervisor_leaves(v, leaf, subleaf, res);
- case 0x80000000 ... 0x80000000 + CPUID_GUEST_NR_EXTD - 1:
+ case 0x80000000U ... 0x80000000U + CPUID_GUEST_NR_EXTD - 1:
ASSERT((p->extd.max_leaf & 0xffff) < ARRAY_SIZE(p->extd.raw));
if ( (leaf & 0xffff) > min_t(uint32_t, p->extd.max_leaf & 0xffff,
ARRAY_SIZE(p->extd.raw) - 1) )
@@ -352,7 +352,7 @@ void guest_cpuid(const struct vcpu *v, uint32_t leaf,
}
break;
- case 0x80000001:
+ case 0x80000001U:
/* SYSCALL is hidden outside of long mode on Intel. */
if ( p->x86_vendor == X86_VENDOR_INTEL &&
is_hvm_domain(d) && !hvm_long_mode_active(v) )
diff --git a/xen/arch/x86/extable.c b/xen/arch/x86/extable.c
index 74b14246e9..652010f413 100644
--- a/xen/arch/x86/extable.c
+++ b/xen/arch/x86/extable.c
@@ -141,7 +141,7 @@ static int __init cf_check stub_selftest(void)
.rax = 0x0123456789abcdef,
.res.fields.trapnr = X86_EXC_GP },
{ .opc = { endbr64, 0x02, 0x04, 0x04, 0xc3 }, /* add (%rsp,%rax),%al */
- .rax = 0xfedcba9876543210,
+ .rax = 0xfedcba9876543210UL,
.res.fields.trapnr = X86_EXC_SS },
{ .opc = { endbr64, 0xcc, 0xc3, 0xc3, 0xc3 }, /* int3 */
.res.fields.trapnr = X86_EXC_BP },
diff --git a/xen/arch/x86/percpu.c b/xen/arch/x86/percpu.c
index 288050cdba..3205eacea6 100644
--- a/xen/arch/x86/percpu.c
+++ b/xen/arch/x86/percpu.c
@@ -12,7 +12,7 @@ unsigned long __per_cpu_offset[NR_CPUS];
* possible #PF at (NULL + a little) which has security implications in the
* context of PV guests.
*/
-#define INVALID_PERCPU_AREA (0x8000000000000000L - (long)__per_cpu_start)
+#define INVALID_PERCPU_AREA (0x8000000000000000UL - (unsigned long)__per_cpu_start)
#define PERCPU_ORDER get_order_from_bytes(__per_cpu_data_end - __per_cpu_start)
void __init percpu_init_areas(void)
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 4c01813c4b..0b9631ac44 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -191,7 +191,7 @@ static struct feat_node *feat_l2_cat;
static struct feat_node *feat_mba;
/* Common functions */
-#define cat_default_val(len) (0xffffffff >> (32 - (len)))
+#define cat_default_val(len) (0xffffffffU >> (32 - (len)))
/*
* get_cdp_data - get DATA COS register value from input COS ID.
diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c
index 6fd7d44ce4..c53632089e 100644
--- a/xen/arch/x86/spec_ctrl.c
+++ b/xen/arch/x86/spec_ctrl.c
@@ -406,10 +406,10 @@ static void __init print_details(enum ind_thunk thunk)
cpuid_count(7, 0, &max, &tmp, &tmp, &_7d0);
if ( max >= 2 )
cpuid_count(7, 2, &tmp, &tmp, &tmp, &_7d2);
- if ( boot_cpu_data.extended_cpuid_level >= 0x80000008 )
- cpuid(0x80000008, &tmp, &e8b, &tmp, &tmp);
- if ( boot_cpu_data.extended_cpuid_level >= 0x80000021 )
- cpuid(0x80000021, &e21a, &tmp, &tmp, &tmp);
+ if ( boot_cpu_data.extended_cpuid_level >= 0x80000008U )
+ cpuid(0x80000008U, &tmp, &e8b, &tmp, &tmp);
+ if ( boot_cpu_data.extended_cpuid_level >= 0x80000021U )
+ cpuid(0x80000021U, &e21a, &tmp, &tmp, &tmp);
if ( cpu_has_arch_caps )
rdmsrl(MSR_ARCH_CAPABILITIES, caps);
@@ -1612,8 +1612,8 @@ void __init init_speculation_mitigations(void)
* TODO: Adjust cpu_has_svm_spec_ctrl to be usable earlier on boot.
*/
if ( opt_msr_sc_hvm &&
- (boot_cpu_data.extended_cpuid_level >= 0x8000000a) &&
- (cpuid_edx(0x8000000a) & (1u << SVM_FEATURE_SPEC_CTRL)) )
+ (boot_cpu_data.extended_cpuid_level >= 0x8000000aU) &&
+ (cpuid_edx(0x8000000aU) & (1u << SVM_FEATURE_SPEC_CTRL)) )
setup_force_cpu_cap(X86_FEATURE_SC_MSR_HVM);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [XEN PATCH v7 4/4] xen/x86: address violations of MISRA C:2012 Rule 7.2
2023-09-28 15:23 ` [XEN PATCH v7 4/4] xen/x86: " Simone Ballarin
@ 2023-09-28 23:00 ` Stefano Stabellini
0 siblings, 0 replies; 9+ messages in thread
From: Stefano Stabellini @ 2023-09-28 23:00 UTC (permalink / raw)
To: Simone Ballarin
Cc: xen-devel, consulting, sstabellini, jbeulich, Andrew Cooper,
Roger Pau Monné, Wei Liu, Gianluca Luparini
On Thu, 28 Sep 2023, Simone Ballarin wrote:
> The xen sources contains violations of MISRA C:2012 Rule 7.2 whose
> headline states:
> "A 'u' or 'U' suffix shall be applied to all integer constants
> that are represented in an unsigned type".
>
> Add the 'U' suffix to integers literals with unsigned type.
>
> For the sake of uniformity, the following change is made:
> - add the 'U' suffix to switch cases in 'cpuid.c'
>
> Signed-off-by: Gianluca Luparini <gianluca.luparini@bugseng.com>
> Signed-off-by: Simone Ballarin <simone.ballarin@bugseng.com>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
> ---
> Changes in v7:
> - change cast to long in a cast to unsigned long in INVALID_PERCPU_AREA
> to match the type of the first operand
> - add missing Signed-off-by tags
> Changes in v6:
> - new patch obtained by splitting X86 related changes from
> "xen/x86: address violations of MISRA C:2012 Rule 7.2 (v5)"
> ---
> xen/arch/x86/apic.c | 2 +-
> xen/arch/x86/cpu-policy.c | 18 +++++++++---------
> xen/arch/x86/cpuid.c | 8 ++++----
> xen/arch/x86/extable.c | 2 +-
> xen/arch/x86/percpu.c | 2 +-
> xen/arch/x86/psr.c | 2 +-
> xen/arch/x86/spec_ctrl.c | 12 ++++++------
> 7 files changed, 23 insertions(+), 23 deletions(-)
>
> diff --git a/xen/arch/x86/apic.c b/xen/arch/x86/apic.c
> index f1264ce7ed..6a43d81d2a 100644
> --- a/xen/arch/x86/apic.c
> +++ b/xen/arch/x86/apic.c
> @@ -1191,7 +1191,7 @@ static void __init calibrate_APIC_clock(void)
> * Setup the APIC counter to maximum. There is no way the lapic
> * can underflow in the 100ms detection time frame.
> */
> - __setup_APIC_LVTT(0xffffffff);
> + __setup_APIC_LVTT(0xffffffffU);
>
> bus_freq = calibrate_apic_timer();
> if ( !bus_freq )
> diff --git a/xen/arch/x86/cpu-policy.c b/xen/arch/x86/cpu-policy.c
> index 81e574390f..423932bc13 100644
> --- a/xen/arch/x86/cpu-policy.c
> +++ b/xen/arch/x86/cpu-policy.c
> @@ -321,7 +321,7 @@ static void recalculate_misc(struct cpu_policy *p)
> p->extd.vendor_edx = p->basic.vendor_edx;
>
> p->extd.raw_fms = p->basic.raw_fms;
> - p->extd.raw[0x1].b &= 0xff00ffff;
> + p->extd.raw[0x1].b &= 0xff00ffffU;
> p->extd.e1d |= p->basic._1d & CPUID_COMMON_1D_FEATURES;
>
> p->extd.raw[0x8].a &= 0x0000ffff; /* GuestMaxPhysAddr hidden. */
> @@ -378,10 +378,10 @@ static void __init calculate_host_policy(void)
> * this information.
> */
> if ( cpu_has_lfence_dispatch )
> - max_extd_leaf = max(max_extd_leaf, 0x80000021);
> + max_extd_leaf = max(max_extd_leaf, 0x80000021U);
>
> - p->extd.max_leaf = 0x80000000 | min_t(uint32_t, max_extd_leaf & 0xffff,
> - ARRAY_SIZE(p->extd.raw) - 1);
> + p->extd.max_leaf = 0x80000000U | min_t(uint32_t, max_extd_leaf & 0xffff,
> + ARRAY_SIZE(p->extd.raw) - 1);
>
> x86_cpu_featureset_to_policy(boot_cpu_data.x86_capability, p);
> recalculate_xstate(p);
> @@ -793,11 +793,11 @@ void recalculate_cpuid_policy(struct domain *d)
>
> p->basic.max_leaf = min(p->basic.max_leaf, max->basic.max_leaf);
> p->feat.max_subleaf = min(p->feat.max_subleaf, max->feat.max_subleaf);
> - p->extd.max_leaf = 0x80000000 | min(p->extd.max_leaf & 0xffff,
> - ((p->x86_vendor & (X86_VENDOR_AMD |
> - X86_VENDOR_HYGON))
> - ? CPUID_GUEST_NR_EXTD_AMD
> - : CPUID_GUEST_NR_EXTD_INTEL) - 1);
> + p->extd.max_leaf = 0x80000000U | min(p->extd.max_leaf & 0xffff,
> + ((p->x86_vendor & (X86_VENDOR_AMD |
> + X86_VENDOR_HYGON))
> + ? CPUID_GUEST_NR_EXTD_AMD
> + : CPUID_GUEST_NR_EXTD_INTEL) - 1);
>
> x86_cpu_policy_to_featureset(p, fs);
> x86_cpu_policy_to_featureset(max, max_fs);
> diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c
> index 455a09b2dd..7290a979c6 100644
> --- a/xen/arch/x86/cpuid.c
> +++ b/xen/arch/x86/cpuid.c
> @@ -93,7 +93,7 @@ void guest_cpuid(const struct vcpu *v, uint32_t leaf,
> }
> break;
>
> - case 0x40000000 ... 0x400000ff:
> + case 0x40000000U ... 0x400000ffU:
> if ( is_viridian_domain(d) )
> return cpuid_viridian_leaves(v, leaf, subleaf, res);
>
> @@ -103,10 +103,10 @@ void guest_cpuid(const struct vcpu *v, uint32_t leaf,
> * Intel reserve up until 0x4fffffff for hypervisor use. AMD reserve
> * only until 0x400000ff, but we already use double that.
> */
> - case 0x40000100 ... 0x400001ff:
> + case 0x40000100U ... 0x400001ffU:
> return cpuid_hypervisor_leaves(v, leaf, subleaf, res);
>
> - case 0x80000000 ... 0x80000000 + CPUID_GUEST_NR_EXTD - 1:
> + case 0x80000000U ... 0x80000000U + CPUID_GUEST_NR_EXTD - 1:
> ASSERT((p->extd.max_leaf & 0xffff) < ARRAY_SIZE(p->extd.raw));
> if ( (leaf & 0xffff) > min_t(uint32_t, p->extd.max_leaf & 0xffff,
> ARRAY_SIZE(p->extd.raw) - 1) )
> @@ -352,7 +352,7 @@ void guest_cpuid(const struct vcpu *v, uint32_t leaf,
> }
> break;
>
> - case 0x80000001:
> + case 0x80000001U:
> /* SYSCALL is hidden outside of long mode on Intel. */
> if ( p->x86_vendor == X86_VENDOR_INTEL &&
> is_hvm_domain(d) && !hvm_long_mode_active(v) )
> diff --git a/xen/arch/x86/extable.c b/xen/arch/x86/extable.c
> index 74b14246e9..652010f413 100644
> --- a/xen/arch/x86/extable.c
> +++ b/xen/arch/x86/extable.c
> @@ -141,7 +141,7 @@ static int __init cf_check stub_selftest(void)
> .rax = 0x0123456789abcdef,
> .res.fields.trapnr = X86_EXC_GP },
> { .opc = { endbr64, 0x02, 0x04, 0x04, 0xc3 }, /* add (%rsp,%rax),%al */
> - .rax = 0xfedcba9876543210,
> + .rax = 0xfedcba9876543210UL,
> .res.fields.trapnr = X86_EXC_SS },
> { .opc = { endbr64, 0xcc, 0xc3, 0xc3, 0xc3 }, /* int3 */
> .res.fields.trapnr = X86_EXC_BP },
> diff --git a/xen/arch/x86/percpu.c b/xen/arch/x86/percpu.c
> index 288050cdba..3205eacea6 100644
> --- a/xen/arch/x86/percpu.c
> +++ b/xen/arch/x86/percpu.c
> @@ -12,7 +12,7 @@ unsigned long __per_cpu_offset[NR_CPUS];
> * possible #PF at (NULL + a little) which has security implications in the
> * context of PV guests.
> */
> -#define INVALID_PERCPU_AREA (0x8000000000000000L - (long)__per_cpu_start)
> +#define INVALID_PERCPU_AREA (0x8000000000000000UL - (unsigned long)__per_cpu_start)
> #define PERCPU_ORDER get_order_from_bytes(__per_cpu_data_end - __per_cpu_start)
>
> void __init percpu_init_areas(void)
> diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
> index 4c01813c4b..0b9631ac44 100644
> --- a/xen/arch/x86/psr.c
> +++ b/xen/arch/x86/psr.c
> @@ -191,7 +191,7 @@ static struct feat_node *feat_l2_cat;
> static struct feat_node *feat_mba;
>
> /* Common functions */
> -#define cat_default_val(len) (0xffffffff >> (32 - (len)))
> +#define cat_default_val(len) (0xffffffffU >> (32 - (len)))
>
> /*
> * get_cdp_data - get DATA COS register value from input COS ID.
> diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c
> index 6fd7d44ce4..c53632089e 100644
> --- a/xen/arch/x86/spec_ctrl.c
> +++ b/xen/arch/x86/spec_ctrl.c
> @@ -406,10 +406,10 @@ static void __init print_details(enum ind_thunk thunk)
> cpuid_count(7, 0, &max, &tmp, &tmp, &_7d0);
> if ( max >= 2 )
> cpuid_count(7, 2, &tmp, &tmp, &tmp, &_7d2);
> - if ( boot_cpu_data.extended_cpuid_level >= 0x80000008 )
> - cpuid(0x80000008, &tmp, &e8b, &tmp, &tmp);
> - if ( boot_cpu_data.extended_cpuid_level >= 0x80000021 )
> - cpuid(0x80000021, &e21a, &tmp, &tmp, &tmp);
> + if ( boot_cpu_data.extended_cpuid_level >= 0x80000008U )
> + cpuid(0x80000008U, &tmp, &e8b, &tmp, &tmp);
> + if ( boot_cpu_data.extended_cpuid_level >= 0x80000021U )
> + cpuid(0x80000021U, &e21a, &tmp, &tmp, &tmp);
> if ( cpu_has_arch_caps )
> rdmsrl(MSR_ARCH_CAPABILITIES, caps);
>
> @@ -1612,8 +1612,8 @@ void __init init_speculation_mitigations(void)
> * TODO: Adjust cpu_has_svm_spec_ctrl to be usable earlier on boot.
> */
> if ( opt_msr_sc_hvm &&
> - (boot_cpu_data.extended_cpuid_level >= 0x8000000a) &&
> - (cpuid_edx(0x8000000a) & (1u << SVM_FEATURE_SPEC_CTRL)) )
> + (boot_cpu_data.extended_cpuid_level >= 0x8000000aU) &&
> + (cpuid_edx(0x8000000aU) & (1u << SVM_FEATURE_SPEC_CTRL)) )
> setup_force_cpu_cap(X86_FEATURE_SC_MSR_HVM);
> }
>
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 9+ messages in thread