* [PATCH v5 1/4] via-ide: Fix legacy mode emulation
2023-10-18 20:42 [PATCH v5 0/4] Add emulation of AmigaOne XE board BALATON Zoltan
@ 2023-10-18 20:42 ` BALATON Zoltan
2023-10-19 14:48 ` Mark Cave-Ayland
2023-10-18 20:42 ` [PATCH v5 2/4] hw/pci-host: Add emulation of Mai Logic Articia S BALATON Zoltan
` (2 subsequent siblings)
3 siblings, 1 reply; 6+ messages in thread
From: BALATON Zoltan @ 2023-10-18 20:42 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: Nicholas Piggin, Daniel Henrique Barboza, clg, philmd,
Bernhard Beschow, Mark Cave-Ayland, Rene Engel, vr_qemu
The initial value for BARs were set in reset method for emulating
legacy mode at start but this does not work because PCI code resets
BARs after calling device reset method. Remove this ineffective
default to avoid confusion.
Instead move setting the BARs to a callback on writing the PCI config
regsiter that sets legacy mode (which firmwares needing this mode seem
to do). This does not fully emulate what the data sheet says (which is
not very clear on this) but it implements enough to allow both modes
as used by firmwares and guests on machines we emulate.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/ide/via.c | 43 ++++++++++++++++++++++++++++++++++++++-----
1 file changed, 38 insertions(+), 5 deletions(-)
diff --git a/hw/ide/via.c b/hw/ide/via.c
index fff23803a6..5a1fe38fb8 100644
--- a/hw/ide/via.c
+++ b/hw/ide/via.c
@@ -28,6 +28,7 @@
#include "hw/pci/pci.h"
#include "migration/vmstate.h"
#include "qemu/module.h"
+#include "qemu/range.h"
#include "sysemu/dma.h"
#include "hw/isa/vt82c686.h"
#include "hw/ide/pci.h"
@@ -132,11 +133,6 @@ static void via_ide_reset(DeviceState *dev)
pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
PCI_STATUS_DEVSEL_MEDIUM);
- pci_set_long(pci_conf + PCI_BASE_ADDRESS_0, 0x000001f0);
- pci_set_long(pci_conf + PCI_BASE_ADDRESS_1, 0x000003f4);
- pci_set_long(pci_conf + PCI_BASE_ADDRESS_2, 0x00000170);
- pci_set_long(pci_conf + PCI_BASE_ADDRESS_3, 0x00000374);
- pci_set_long(pci_conf + PCI_BASE_ADDRESS_4, 0x0000cc01); /* BMIBA: 20-23h */
pci_set_long(pci_conf + PCI_INTERRUPT_LINE, 0x0000010e);
/* IDE chip enable, IDE configuration 1/2, IDE FIFO Configuration*/
@@ -159,6 +155,42 @@ static void via_ide_reset(DeviceState *dev)
pci_set_long(pci_conf + 0xc0, 0x00020001);
}
+static void via_ide_cfg_write(PCIDevice *pd, uint32_t addr,
+ uint32_t val, int len)
+{
+ pci_default_write_config(pd, addr, val, len);
+ /*
+ * Bits 0 and 2 of the PCI programming interface register are documented to
+ * select between legacy and native mode for the two IDE channels. when the
+ * guest selects legacy mode we reset the PCI BARs to legacy ports which is
+ * their default value. We don't care about setting each channel separately
+ * as no guest is known to do or need that. But only do this when BARs are
+ * unset when writing this register as logs from real hardware show that
+ * setting legacy mode after BARs were set will still use ports set by BARs
+ * not ISA ports (Linux on pegasos2 does this after firmware set native
+ * mode and programmed BARs). If 0x8a is written after reset without
+ * setting BARs then we want legacy ports (this is done by the AmigaOne
+ * firmware). We can't set these in via_ide_reset() because PCI code clears
+ * BARs after calling device reset method.
+ */
+ if (range_covers_byte(addr, len, PCI_CLASS_PROG) &&
+ pd->config[PCI_CLASS_PROG] == 0x8a &&
+ pci_get_long(pd->config + PCI_BASE_ADDRESS_0) ==
+ PCI_BASE_ADDRESS_SPACE_IO) {
+ pci_set_long(pd->config + PCI_BASE_ADDRESS_0, 0x1f0
+ | PCI_BASE_ADDRESS_SPACE_IO);
+ pci_set_long(pd->config + PCI_BASE_ADDRESS_1, 0x3f4
+ | PCI_BASE_ADDRESS_SPACE_IO);
+ pci_set_long(pd->config + PCI_BASE_ADDRESS_2, 0x170
+ | PCI_BASE_ADDRESS_SPACE_IO);
+ pci_set_long(pd->config + PCI_BASE_ADDRESS_3, 0x374
+ | PCI_BASE_ADDRESS_SPACE_IO);
+ /* BMIBA: 20-23h */
+ pci_set_long(pd->config + PCI_BASE_ADDRESS_4, 0xcc00
+ | PCI_BASE_ADDRESS_SPACE_IO);
+ }
+}
+
static void via_ide_realize(PCIDevice *dev, Error **errp)
{
PCIIDEState *d = PCI_IDE(dev);
@@ -221,6 +253,7 @@ static void via_ide_class_init(ObjectClass *klass, void *data)
/* Reason: only works as function of VIA southbridge */
dc->user_creatable = false;
+ k->config_write = via_ide_cfg_write;
k->realize = via_ide_realize;
k->exit = via_ide_exitfn;
k->vendor_id = PCI_VENDOR_ID_VIA;
--
2.30.9
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v5 1/4] via-ide: Fix legacy mode emulation
2023-10-18 20:42 ` [PATCH v5 1/4] via-ide: Fix legacy mode emulation BALATON Zoltan
@ 2023-10-19 14:48 ` Mark Cave-Ayland
0 siblings, 0 replies; 6+ messages in thread
From: Mark Cave-Ayland @ 2023-10-19 14:48 UTC (permalink / raw)
To: BALATON Zoltan, qemu-devel, qemu-ppc
Cc: Nicholas Piggin, Daniel Henrique Barboza, clg, philmd,
Bernhard Beschow, Rene Engel, vr_qemu
On 18/10/2023 21:42, BALATON Zoltan wrote:
> The initial value for BARs were set in reset method for emulating
> legacy mode at start but this does not work because PCI code resets
> BARs after calling device reset method. Remove this ineffective
> default to avoid confusion.
>
> Instead move setting the BARs to a callback on writing the PCI config
> regsiter that sets legacy mode (which firmwares needing this mode seem
> to do). This does not fully emulate what the data sheet says (which is
> not very clear on this) but it implements enough to allow both modes
> as used by firmwares and guests on machines we emulate.
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> hw/ide/via.c | 43 ++++++++++++++++++++++++++++++++++++++-----
> 1 file changed, 38 insertions(+), 5 deletions(-)
>
> diff --git a/hw/ide/via.c b/hw/ide/via.c
> index fff23803a6..5a1fe38fb8 100644
> --- a/hw/ide/via.c
> +++ b/hw/ide/via.c
> @@ -28,6 +28,7 @@
> #include "hw/pci/pci.h"
> #include "migration/vmstate.h"
> #include "qemu/module.h"
> +#include "qemu/range.h"
> #include "sysemu/dma.h"
> #include "hw/isa/vt82c686.h"
> #include "hw/ide/pci.h"
> @@ -132,11 +133,6 @@ static void via_ide_reset(DeviceState *dev)
> pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
> PCI_STATUS_DEVSEL_MEDIUM);
>
> - pci_set_long(pci_conf + PCI_BASE_ADDRESS_0, 0x000001f0);
> - pci_set_long(pci_conf + PCI_BASE_ADDRESS_1, 0x000003f4);
> - pci_set_long(pci_conf + PCI_BASE_ADDRESS_2, 0x00000170);
> - pci_set_long(pci_conf + PCI_BASE_ADDRESS_3, 0x00000374);
> - pci_set_long(pci_conf + PCI_BASE_ADDRESS_4, 0x0000cc01); /* BMIBA: 20-23h */
> pci_set_long(pci_conf + PCI_INTERRUPT_LINE, 0x0000010e);
>
> /* IDE chip enable, IDE configuration 1/2, IDE FIFO Configuration*/
> @@ -159,6 +155,42 @@ static void via_ide_reset(DeviceState *dev)
> pci_set_long(pci_conf + 0xc0, 0x00020001);
> }
>
> +static void via_ide_cfg_write(PCIDevice *pd, uint32_t addr,
> + uint32_t val, int len)
> +{
> + pci_default_write_config(pd, addr, val, len);
> + /*
> + * Bits 0 and 2 of the PCI programming interface register are documented to
> + * select between legacy and native mode for the two IDE channels. when the
> + * guest selects legacy mode we reset the PCI BARs to legacy ports which is
> + * their default value. We don't care about setting each channel separately
> + * as no guest is known to do or need that. But only do this when BARs are
> + * unset when writing this register as logs from real hardware show that
> + * setting legacy mode after BARs were set will still use ports set by BARs
> + * not ISA ports (Linux on pegasos2 does this after firmware set native
> + * mode and programmed BARs). If 0x8a is written after reset without
> + * setting BARs then we want legacy ports (this is done by the AmigaOne
> + * firmware). We can't set these in via_ide_reset() because PCI code clears
> + * BARs after calling device reset method.
> + */
> + if (range_covers_byte(addr, len, PCI_CLASS_PROG) &&
> + pd->config[PCI_CLASS_PROG] == 0x8a &&
> + pci_get_long(pd->config + PCI_BASE_ADDRESS_0) ==
> + PCI_BASE_ADDRESS_SPACE_IO) {
> + pci_set_long(pd->config + PCI_BASE_ADDRESS_0, 0x1f0
> + | PCI_BASE_ADDRESS_SPACE_IO);
> + pci_set_long(pd->config + PCI_BASE_ADDRESS_1, 0x3f4
> + | PCI_BASE_ADDRESS_SPACE_IO);
> + pci_set_long(pd->config + PCI_BASE_ADDRESS_2, 0x170
> + | PCI_BASE_ADDRESS_SPACE_IO);
> + pci_set_long(pd->config + PCI_BASE_ADDRESS_3, 0x374
> + | PCI_BASE_ADDRESS_SPACE_IO);
> + /* BMIBA: 20-23h */
> + pci_set_long(pd->config + PCI_BASE_ADDRESS_4, 0xcc00
> + | PCI_BASE_ADDRESS_SPACE_IO);
> + }
> +}
> +
> static void via_ide_realize(PCIDevice *dev, Error **errp)
> {
> PCIIDEState *d = PCI_IDE(dev);
> @@ -221,6 +253,7 @@ static void via_ide_class_init(ObjectClass *klass, void *data)
> /* Reason: only works as function of VIA southbridge */
> dc->user_creatable = false;
>
> + k->config_write = via_ide_cfg_write;
> k->realize = via_ide_realize;
> k->exit = via_ide_exitfn;
> k->vendor_id = PCI_VENDOR_ID_VIA;
As promised I've posted an updated version of the proposed patch which better matches
the hardware (and is also less invasive to hw/ide/via.c) at
https://lists.gnu.org/archive/html/qemu-devel/2023-10/msg06416.html.
ATB,
Mark.
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v5 2/4] hw/pci-host: Add emulation of Mai Logic Articia S
2023-10-18 20:42 [PATCH v5 0/4] Add emulation of AmigaOne XE board BALATON Zoltan
2023-10-18 20:42 ` [PATCH v5 1/4] via-ide: Fix legacy mode emulation BALATON Zoltan
@ 2023-10-18 20:42 ` BALATON Zoltan
2023-10-18 20:42 ` [PATCH v5 3/4] hw/ppc: Add emulation of AmigaOne XE board BALATON Zoltan
2023-10-18 20:42 ` [PATCH v5 4/4] tests/avocado: Add test for amigaone board BALATON Zoltan
3 siblings, 0 replies; 6+ messages in thread
From: BALATON Zoltan @ 2023-10-18 20:42 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: Nicholas Piggin, Daniel Henrique Barboza, clg, philmd,
Bernhard Beschow, Mark Cave-Ayland, Rene Engel, vr_qemu
The Articia S is a generic chipset supporting several different CPUs
that were among others used on some PPC boards. This is a minimal
emulation of the parts needed for emulating the AmigaOne board.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
hw/pci-host/Kconfig | 5 +
hw/pci-host/articia.c | 293 ++++++++++++++++++++++++++++++++++
hw/pci-host/meson.build | 2 +
include/hw/pci-host/articia.h | 17 ++
4 files changed, 317 insertions(+)
create mode 100644 hw/pci-host/articia.c
create mode 100644 include/hw/pci-host/articia.h
diff --git a/hw/pci-host/Kconfig b/hw/pci-host/Kconfig
index a07070eddf..33014c80a4 100644
--- a/hw/pci-host/Kconfig
+++ b/hw/pci-host/Kconfig
@@ -73,6 +73,11 @@ config SH_PCI
bool
select PCI
+config ARTICIA
+ bool
+ select PCI
+ select I8259
+
config MV64361
bool
select PCI
diff --git a/hw/pci-host/articia.c b/hw/pci-host/articia.c
new file mode 100644
index 0000000000..f3fcc49f81
--- /dev/null
+++ b/hw/pci-host/articia.c
@@ -0,0 +1,293 @@
+/*
+ * Mai Logic Articia S emulation
+ *
+ * Copyright (c) 2023 BALATON Zoltan
+ *
+ * This work is licensed under the GNU GPL license version 2 or later.
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "hw/pci/pci_device.h"
+#include "hw/pci/pci_host.h"
+#include "hw/irq.h"
+#include "hw/i2c/bitbang_i2c.h"
+#include "hw/intc/i8259.h"
+#include "hw/pci-host/articia.h"
+
+/*
+ * This is a minimal emulation of this chip as used in AmigaOne board.
+ * Most features are missing but those are not needed by firmware and guests.
+ */
+
+OBJECT_DECLARE_SIMPLE_TYPE(ArticiaState, ARTICIA)
+
+OBJECT_DECLARE_SIMPLE_TYPE(ArticiaHostState, ARTICIA_PCI_HOST)
+struct ArticiaHostState {
+ PCIDevice parent_obj;
+
+ ArticiaState *as;
+};
+
+/* TYPE_ARTICIA */
+
+struct ArticiaState {
+ PCIHostState parent_obj;
+
+ qemu_irq irq[PCI_NUM_PINS];
+ MemoryRegion io;
+ MemoryRegion mem;
+ MemoryRegion reg;
+
+ bitbang_i2c_interface smbus;
+ uint32_t gpio; /* bits 0-7 in, 8-15 out, 16-23 direction (0 in, 1 out) */
+ hwaddr gpio_base;
+ MemoryRegion gpio_reg;
+};
+
+static uint64_t articia_gpio_read(void *opaque, hwaddr addr, unsigned int size)
+{
+ ArticiaState *s = opaque;
+
+ return (s->gpio >> (addr * 8)) & 0xff;
+}
+
+static void articia_gpio_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned int size)
+{
+ ArticiaState *s = opaque;
+ uint32_t sh = addr * 8;
+
+ if (addr == 0) {
+ /* in bits read only? */
+ return;
+ }
+
+ if ((s->gpio & (0xff << sh)) != (val & 0xff) << sh) {
+ s->gpio &= ~(0xff << sh | 0xff);
+ s->gpio |= (val & 0xff) << sh;
+ s->gpio |= bitbang_i2c_set(&s->smbus, BITBANG_I2C_SDA,
+ s->gpio & BIT(16) ?
+ !!(s->gpio & BIT(8)) : 1);
+ if ((s->gpio & BIT(17))) {
+ s->gpio &= ~BIT(0);
+ s->gpio |= bitbang_i2c_set(&s->smbus, BITBANG_I2C_SCL,
+ !!(s->gpio & BIT(9)));
+ }
+ }
+}
+
+static const MemoryRegionOps articia_gpio_ops = {
+ .read = articia_gpio_read,
+ .write = articia_gpio_write,
+ .valid.min_access_size = 1,
+ .valid.max_access_size = 1,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static uint64_t articia_reg_read(void *opaque, hwaddr addr, unsigned int size)
+{
+ ArticiaState *s = opaque;
+ uint64_t ret = UINT_MAX;
+
+ switch (addr) {
+ case 0xc00cf8:
+ ret = pci_host_conf_le_ops.read(PCI_HOST_BRIDGE(s), 0, size);
+ break;
+ case 0xe00cfc ... 0xe00cff:
+ ret = pci_host_data_le_ops.read(PCI_HOST_BRIDGE(s), addr - 0xe00cfc, size);
+ break;
+ case 0xf00000:
+ ret = pic_read_irq(isa_pic);
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "%s: Unimplemented register read 0x%"
+ HWADDR_PRIx " %d\n", __func__, addr, size);
+ break;
+ }
+ return ret;
+}
+
+static void articia_reg_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned int size)
+{
+ ArticiaState *s = opaque;
+
+ switch (addr) {
+ case 0xc00cf8:
+ pci_host_conf_le_ops.write(PCI_HOST_BRIDGE(s), 0, val, size);
+ break;
+ case 0xe00cfc ... 0xe00cff:
+ pci_host_data_le_ops.write(PCI_HOST_BRIDGE(s), addr, val, size);
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "%s: Unimplemented register write 0x%"
+ HWADDR_PRIx " %d <- %"PRIx64"\n", __func__, addr, size, val);
+ break;
+ }
+}
+
+static const MemoryRegionOps articia_reg_ops = {
+ .read = articia_reg_read,
+ .write = articia_reg_write,
+ .valid.min_access_size = 1,
+ .valid.max_access_size = 4,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void articia_pcihost_set_irq(void *opaque, int n, int level)
+{
+ ArticiaState *s = opaque;
+ qemu_set_irq(s->irq[n], level);
+}
+
+/*
+ * AmigaOne SE PCI slot to IRQ routing
+ *
+ * repository: https://source.denx.de/u-boot/custodians/u-boot-avr32.git
+ * refspec: v2010.06
+ * file: board/MAI/AmigaOneG3SE/articiaS_pci.c
+ */
+static int amigaone_pcihost_bus0_map_irq(PCIDevice *pdev, int pin)
+{
+ int devfn_slot = PCI_SLOT(pdev->devfn);
+
+ switch (devfn_slot) {
+ case 6: /* On board ethernet */
+ return 3;
+ case 7: /* South bridge */
+ return pin;
+ default: /* PCI Slot 1 Devfn slot 8, Slot 2 Devfn 9, Slot 3 Devfn 10 */
+ return pci_swizzle(devfn_slot, pin);
+ }
+
+}
+
+static void articia_realize(DeviceState *dev, Error **errp)
+{
+ ArticiaState *s = ARTICIA(dev);
+ PCIHostState *h = PCI_HOST_BRIDGE(dev);
+ PCIDevice *pdev;
+
+ bitbang_i2c_init(&s->smbus, i2c_init_bus(dev, "smbus"));
+ memory_region_init_io(&s->gpio_reg, OBJECT(s), &articia_gpio_ops, s,
+ TYPE_ARTICIA, 4);
+
+ memory_region_init(&s->mem, OBJECT(dev), "pci-mem", UINT64_MAX);
+ memory_region_init(&s->io, OBJECT(dev), "pci-io", 0xc00000);
+ memory_region_init_io(&s->reg, OBJECT(s), &articia_reg_ops, s,
+ TYPE_ARTICIA, 0x1000000);
+ memory_region_add_subregion_overlap(&s->reg, 0, &s->io, 1);
+
+ /* devfn_min is 8 that matches first PCI slot in AmigaOne */
+ h->bus = pci_register_root_bus(dev, NULL, articia_pcihost_set_irq,
+ amigaone_pcihost_bus0_map_irq, dev, &s->mem,
+ &s->io, PCI_DEVFN(8, 0), 4, TYPE_PCI_BUS);
+ pdev = pci_create_simple_multifunction(h->bus, PCI_DEVFN(0, 0),
+ TYPE_ARTICIA_PCI_HOST);
+ ARTICIA_PCI_HOST(pdev)->as = s;
+ pci_create_simple(h->bus, PCI_DEVFN(0, 1), TYPE_ARTICIA_PCI_BRIDGE);
+
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->reg);
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mem);
+ qdev_init_gpio_out(dev, s->irq, ARRAY_SIZE(s->irq));
+}
+
+static void articia_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = articia_realize;
+ set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
+}
+
+/* TYPE_ARTICIA_PCI_HOST */
+
+static void articia_pci_host_cfg_write(PCIDevice *d, uint32_t addr,
+ uint32_t val, int len)
+{
+ ArticiaState *s = ARTICIA_PCI_HOST(d)->as;
+
+ pci_default_write_config(d, addr, val, len);
+ switch (addr) {
+ case 0x40:
+ s->gpio_base = val;
+ break;
+ case 0x44:
+ if (val != 0x11) {
+ /* FIXME what do the bits actually mean? */
+ break;
+ }
+ if (memory_region_is_mapped(&s->gpio_reg)) {
+ memory_region_del_subregion(&s->io, &s->gpio_reg);
+ }
+ memory_region_add_subregion(&s->io, s->gpio_base + 0x38, &s->gpio_reg);
+ break;
+ }
+}
+
+static void articia_pci_host_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+ k->config_write = articia_pci_host_cfg_write;
+ k->vendor_id = 0x10cc;
+ k->device_id = 0x0660;
+ k->class_id = PCI_CLASS_BRIDGE_HOST;
+ /*
+ * PCI-facing part of the host bridge,
+ * not usable without the host-facing part
+ */
+ dc->user_creatable = false;
+}
+
+/* TYPE_ARTICIA_PCI_BRIDGE */
+
+static void articia_pci_bridge_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+ k->vendor_id = 0x10cc;
+ k->device_id = 0x0661;
+ k->class_id = PCI_CLASS_BRIDGE_HOST;
+ /*
+ * PCI-facing part of the host bridge,
+ * not usable without the host-facing part
+ */
+ dc->user_creatable = false;
+}
+
+static const TypeInfo articia_types[] = {
+ {
+ .name = TYPE_ARTICIA,
+ .parent = TYPE_PCI_HOST_BRIDGE,
+ .instance_size = sizeof(ArticiaState),
+ .class_init = articia_class_init,
+ },
+ {
+ .name = TYPE_ARTICIA_PCI_HOST,
+ .parent = TYPE_PCI_DEVICE,
+ .instance_size = sizeof(ArticiaHostState),
+ .class_init = articia_pci_host_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { INTERFACE_CONVENTIONAL_PCI_DEVICE },
+ { },
+ },
+ },
+ {
+ .name = TYPE_ARTICIA_PCI_BRIDGE,
+ .parent = TYPE_PCI_DEVICE,
+ .instance_size = sizeof(PCIDevice),
+ .class_init = articia_pci_bridge_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { INTERFACE_CONVENTIONAL_PCI_DEVICE },
+ { },
+ },
+ },
+};
+
+DEFINE_TYPES(articia_types)
diff --git a/hw/pci-host/meson.build b/hw/pci-host/meson.build
index 64eada76fe..40de48eb7f 100644
--- a/hw/pci-host/meson.build
+++ b/hw/pci-host/meson.build
@@ -20,6 +20,8 @@ pci_ss.add(when: 'CONFIG_GRACKLE_PCI', if_true: files('grackle.c'))
pci_ss.add(when: 'CONFIG_UNIN_PCI', if_true: files('uninorth.c'))
# PowerPC E500 boards
pci_ss.add(when: 'CONFIG_PPCE500_PCI', if_true: files('ppce500.c'))
+# AmigaOne
+pci_ss.add(when: 'CONFIG_ARTICIA', if_true: files('articia.c'))
# Pegasos2
pci_ss.add(when: 'CONFIG_MV64361', if_true: files('mv64361.c'))
diff --git a/include/hw/pci-host/articia.h b/include/hw/pci-host/articia.h
new file mode 100644
index 0000000000..529c240274
--- /dev/null
+++ b/include/hw/pci-host/articia.h
@@ -0,0 +1,17 @@
+/*
+ * Mai Logic Articia S emulation
+ *
+ * Copyright (c) 2023 BALATON Zoltan
+ *
+ * This work is licensed under the GNU GPL license version 2 or later.
+ *
+ */
+
+#ifndef ARTICIA_H
+#define ARTICIA_H
+
+#define TYPE_ARTICIA "articia"
+#define TYPE_ARTICIA_PCI_HOST "articia-pci-host"
+#define TYPE_ARTICIA_PCI_BRIDGE "articia-pci-bridge"
+
+#endif
--
2.30.9
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v5 3/4] hw/ppc: Add emulation of AmigaOne XE board
2023-10-18 20:42 [PATCH v5 0/4] Add emulation of AmigaOne XE board BALATON Zoltan
2023-10-18 20:42 ` [PATCH v5 1/4] via-ide: Fix legacy mode emulation BALATON Zoltan
2023-10-18 20:42 ` [PATCH v5 2/4] hw/pci-host: Add emulation of Mai Logic Articia S BALATON Zoltan
@ 2023-10-18 20:42 ` BALATON Zoltan
2023-10-18 20:42 ` [PATCH v5 4/4] tests/avocado: Add test for amigaone board BALATON Zoltan
3 siblings, 0 replies; 6+ messages in thread
From: BALATON Zoltan @ 2023-10-18 20:42 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: Nicholas Piggin, Daniel Henrique Barboza, clg, philmd,
Bernhard Beschow, Mark Cave-Ayland, Rene Engel, vr_qemu
The AmigaOne is a rebranded MAI Teron board that uses U-Boot firmware
with patches to support AmigaOS and is very similar to pegasos2 so can
be easily emulated sharing most code with pegasos2. The reason to
emulate it is that AmigaOS comes in different versions for AmigaOne
and PegasosII which only have drivers for one machine and firmware so
these only run on the specific machine. Adding this board allows
another AmigaOS version to be used reusing already existing peagasos2
emulation. (The AmigaOne was the first of these boards so likely most
widespread which then inspired Pegasos that was later replaced with
PegasosII due to problems with Articia S, so these have a lot of
similarity. Pegasos mainly ran MorphOS while the PegasosII version of
AmigaOS was added later and therefore less common than the AmigaOne
version.)
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
MAINTAINERS | 8 ++
configs/devices/ppc-softmmu/default.mak | 1 +
hw/ppc/Kconfig | 7 +
hw/ppc/amigaone.c | 164 ++++++++++++++++++++++++
hw/ppc/meson.build | 2 +
5 files changed, 182 insertions(+)
create mode 100644 hw/ppc/amigaone.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 9bd4fe378d..efc3f369bb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1508,6 +1508,14 @@ F: hw/pci-host/mv64361.c
F: hw/pci-host/mv643xx.h
F: include/hw/pci-host/mv64361.h
+amigaone
+M: BALATON Zoltan <balaton@eik.bme.hu>
+L: qemu-ppc@nongnu.org
+S: Maintained
+F: hw/ppc/amigaone.c
+F: hw/pci-host/articia.c
+F: include/hw/pci-host/articia.h
+
Virtual Open Firmware (VOF)
M: Alexey Kardashevskiy <aik@ozlabs.ru>
R: David Gibson <david@gibson.dropbear.id.au>
diff --git a/configs/devices/ppc-softmmu/default.mak b/configs/devices/ppc-softmmu/default.mak
index a887f5438b..b85fd2bcd7 100644
--- a/configs/devices/ppc-softmmu/default.mak
+++ b/configs/devices/ppc-softmmu/default.mak
@@ -14,6 +14,7 @@ CONFIG_SAM460EX=y
CONFIG_MAC_OLDWORLD=y
CONFIG_MAC_NEWWORLD=y
+CONFIG_AMIGAONE=y
CONFIG_PEGASOS2=y
# For PReP
diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
index 5dfbf47ef5..56f0475a8e 100644
--- a/hw/ppc/Kconfig
+++ b/hw/ppc/Kconfig
@@ -69,6 +69,13 @@ config SAM460EX
select USB_OHCI
select FDT_PPC
+config AMIGAONE
+ bool
+ imply ATI_VGA
+ select ARTICIA
+ select VT82C686
+ select SMBUS_EEPROM
+
config PEGASOS2
bool
imply ATI_VGA
diff --git a/hw/ppc/amigaone.c b/hw/ppc/amigaone.c
new file mode 100644
index 0000000000..3589924c8a
--- /dev/null
+++ b/hw/ppc/amigaone.c
@@ -0,0 +1,164 @@
+/*
+ * QEMU Eyetech AmigaOne/Mai Logic Teron emulation
+ *
+ * Copyright (c) 2023 BALATON Zoltan
+ *
+ * This work is licensed under the GNU GPL license version 2 or later.
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "qemu/datadir.h"
+#include "qemu/log.h"
+#include "qemu/error-report.h"
+#include "qapi/error.h"
+#include "hw/ppc/ppc.h"
+#include "hw/boards.h"
+#include "hw/loader.h"
+#include "hw/pci-host/articia.h"
+#include "hw/isa/vt82c686.h"
+#include "hw/ide/pci.h"
+#include "hw/i2c/smbus_eeprom.h"
+#include "hw/ppc/ppc.h"
+#include "sysemu/reset.h"
+#include "kvm_ppc.h"
+
+#define BUS_FREQ_HZ 100000000
+
+/*
+ * Firmware binary available at
+ * https://www.hyperion-entertainment.com/index.php/downloads?view=files&parent=28
+ * then "tail -c 524288 updater.image >u-boot-amigaone.bin"
+ *
+ * BIOS emulator in firmware cannot run QEMU vgabios and hangs on it, use
+ * -device VGA,romfile=VGABIOS-lgpl-latest.bin
+ * from http://www.nongnu.org/vgabios/ instead.
+ */
+#define PROM_FILENAME "u-boot-amigaone.bin"
+#define PROM_ADDR 0xfff00000
+#define PROM_SIZE (512 * KiB)
+
+static void amigaone_cpu_reset(void *opaque)
+{
+ PowerPCCPU *cpu = opaque;
+
+ cpu_reset(CPU(cpu));
+ cpu_ppc_tb_reset(&cpu->env);
+}
+
+static void fix_spd_data(uint8_t *spd)
+{
+ uint32_t bank_size = 4 * MiB * spd[31];
+ uint32_t rows = bank_size / spd[13] / spd[17];
+ spd[3] = ctz32(rows) - spd[4];
+}
+
+static void amigaone_init(MachineState *machine)
+{
+ PowerPCCPU *cpu;
+ CPUPPCState *env;
+ MemoryRegion *rom, *pci_mem, *mr;
+ const char *fwname = machine->firmware ?: PROM_FILENAME;
+ char *filename;
+ ssize_t sz;
+ PCIBus *pci_bus;
+ Object *via;
+ DeviceState *dev;
+ I2CBus *i2c_bus;
+ uint8_t *spd_data;
+ int i;
+
+ /* init CPU */
+ cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
+ env = &cpu->env;
+ if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
+ error_report("Incompatible CPU, only 6xx bus supported");
+ exit(1);
+ }
+ cpu_ppc_tb_init(env, BUS_FREQ_HZ / 4);
+ qemu_register_reset(amigaone_cpu_reset, cpu);
+
+ /* RAM */
+ if (machine->ram_size > 2 * GiB) {
+ error_report("RAM size more than 2 GiB is not supported");
+ exit(1);
+ }
+ memory_region_add_subregion(get_system_memory(), 0, machine->ram);
+ if (machine->ram_size < 1 * GiB + 32 * KiB) {
+ /* Firmware uses this area for startup */
+ mr = g_new(MemoryRegion, 1);
+ memory_region_init_ram(mr, NULL, "init-cache", 32 * KiB, &error_fatal);
+ memory_region_add_subregion(get_system_memory(), 0x40000000, mr);
+ }
+
+ /* allocate and load firmware */
+ filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, fwname);
+ if (!filename) {
+ error_report("Could not find firmware '%s'", fwname);
+ exit(1);
+ }
+ rom = g_new(MemoryRegion, 1);
+ memory_region_init_rom(rom, NULL, "rom", PROM_SIZE, &error_fatal);
+ memory_region_add_subregion(get_system_memory(), PROM_ADDR, rom);
+ sz = load_image_targphys(filename, PROM_ADDR, PROM_SIZE);
+ if (sz <= 0 || sz > PROM_SIZE) {
+ error_report("Could not load firmware '%s'", filename);
+ exit(1);
+ }
+ g_free(filename);
+
+ /* Articia S */
+ dev = sysbus_create_simple(TYPE_ARTICIA, 0xfe000000, NULL);
+
+ i2c_bus = I2C_BUS(qdev_get_child_bus(dev, "smbus"));
+ if (machine->ram_size > 512 * MiB) {
+ spd_data = spd_data_generate(SDR, machine->ram_size / 2);
+ } else {
+ spd_data = spd_data_generate(SDR, machine->ram_size);
+ }
+ fix_spd_data(spd_data);
+ smbus_eeprom_init_one(i2c_bus, 0x51, spd_data);
+ if (machine->ram_size > 512 * MiB) {
+ smbus_eeprom_init_one(i2c_bus, 0x52, spd_data);
+ }
+
+ pci_mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
+ mr = g_new(MemoryRegion, 1);
+ memory_region_init_alias(mr, OBJECT(dev), "pci-mem-low", pci_mem,
+ 0, 0x1000000);
+ memory_region_add_subregion(get_system_memory(), 0xfd000000, mr);
+ mr = g_new(MemoryRegion, 1);
+ memory_region_init_alias(mr, OBJECT(dev), "pci-mem-high", pci_mem,
+ 0x80000000, 0x7d000000);
+ memory_region_add_subregion(get_system_memory(), 0x80000000, mr);
+ pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0"));
+
+ /* VIA VT82c686B South Bridge (multifunction PCI device) */
+ via = OBJECT(pci_create_simple_multifunction(pci_bus, PCI_DEVFN(7, 0),
+ TYPE_VT82C686B_ISA));
+ object_property_add_alias(OBJECT(machine), "rtc-time",
+ object_resolve_path_component(via, "rtc"),
+ "date");
+ qdev_connect_gpio_out(DEVICE(via), 0,
+ qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT_INT));
+ for (i = 0; i < PCI_NUM_PINS; i++) {
+ qdev_connect_gpio_out(dev, i, qdev_get_gpio_in_named(DEVICE(via),
+ "pirq", i));
+ }
+ pci_ide_create_devs(PCI_DEVICE(object_resolve_path_component(via, "ide")));
+ pci_vga_init(pci_bus);
+}
+
+static void amigaone_machine_init(MachineClass *mc)
+{
+ mc->desc = "Eyetech AmigaOne/Mai Logic Teron";
+ mc->init = amigaone_init;
+ mc->block_default_type = IF_IDE;
+ mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7457_v1.2");
+ mc->default_display = "std";
+ mc->default_ram_id = "ram";
+ mc->default_ram_size = 128 * MiB;
+}
+
+DEFINE_MACHINE("amigaone", amigaone_machine_init)
diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build
index 7c2c52434a..7338f9432a 100644
--- a/hw/ppc/meson.build
+++ b/hw/ppc/meson.build
@@ -81,6 +81,8 @@ ppc_ss.add(when: 'CONFIG_E500', if_true: files(
))
# PowerPC 440 Xilinx ML507 reference board.
ppc_ss.add(when: 'CONFIG_VIRTEX', if_true: files('virtex_ml507.c'))
+# AmigaOne
+ppc_ss.add(when: 'CONFIG_AMIGAONE', if_true: files('amigaone.c'))
# Pegasos2
ppc_ss.add(when: 'CONFIG_PEGASOS2', if_true: files('pegasos2.c'))
--
2.30.9
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v5 4/4] tests/avocado: Add test for amigaone board
2023-10-18 20:42 [PATCH v5 0/4] Add emulation of AmigaOne XE board BALATON Zoltan
` (2 preceding siblings ...)
2023-10-18 20:42 ` [PATCH v5 3/4] hw/ppc: Add emulation of AmigaOne XE board BALATON Zoltan
@ 2023-10-18 20:42 ` BALATON Zoltan
3 siblings, 0 replies; 6+ messages in thread
From: BALATON Zoltan @ 2023-10-18 20:42 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: Nicholas Piggin, Daniel Henrique Barboza, clg, philmd,
Bernhard Beschow, Mark Cave-Ayland, Rene Engel, vr_qemu
Add an avocado test for the amigaone board that tests it with the
firmware.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
---
tests/avocado/ppc_amiga.py | 38 ++++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
create mode 100644 tests/avocado/ppc_amiga.py
diff --git a/tests/avocado/ppc_amiga.py b/tests/avocado/ppc_amiga.py
new file mode 100644
index 0000000000..b6f866f91d
--- /dev/null
+++ b/tests/avocado/ppc_amiga.py
@@ -0,0 +1,38 @@
+# Test AmigaNG boards
+#
+# Copyright (c) 2023 BALATON Zoltan
+#
+# This work is licensed under the terms of the GNU GPL, version 2 or
+# later. See the COPYING file in the top-level directory.
+
+from avocado.utils import archive
+from avocado.utils import process
+from avocado_qemu import QemuSystemTest
+from avocado_qemu import wait_for_console_pattern
+
+class AmigaOneMachine(QemuSystemTest):
+
+ timeout = 90
+
+ def test_ppc_amigaone(self):
+ """
+ :avocado: tags=arch:ppc
+ :avocado: tags=machine:amigaone
+ :avocado: tags=device:articia
+ :avocado: tags=accel:tcg
+ """
+ self.require_accelerator("tcg")
+ tar_name = 'A1Firmware_Floppy_05-Mar-2005.zip'
+ tar_url = ('https://www.hyperion-entertainment.com/index.php/'
+ 'downloads?view=download&format=raw&file=25')
+ tar_hash = 'c52e59bc73e31d8bcc3cc2106778f7ac84f6c755'
+ zip_file = self.fetch_asset(tar_name, locations=tar_url,
+ asset_hash=tar_hash)
+ archive.extract(zip_file, self.workdir)
+ cmd = f"tail -c 524288 {self.workdir}/floppy_edition/updater.image >{self.workdir}/u-boot-amigaone.bin"
+ process.run(cmd, shell=True)
+
+ self.vm.set_console()
+ self.vm.add_args('-bios', self.workdir + '/u-boot-amigaone.bin')
+ self.vm.launch()
+ wait_for_console_pattern(self, 'FLASH:')
--
2.30.9
^ permalink raw reply related [flat|nested] 6+ messages in thread