* [XEN PATCH v2 01/25] arm: vgic: its: Decouple HW and virtual ITS
2023-11-10 12:56 [XEN PATCH v2 00/25] arm: Add GICv3 support to the New VGIC Mykyta Poturai
@ 2023-11-10 12:56 ` Mykyta Poturai
2023-11-10 12:56 ` [XEN PATCH v2 02/25] arm: new VGIC: Add GICv3 world switch backend Mykyta Poturai
` (23 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Mykyta Poturai @ 2023-11-10 12:56 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org
Cc: Mykyta Poturai, Stefano Stabellini, Julien Grall,
Bertrand Marquis, Volodymyr Babchuk, Michal Orzel
HW its directly uses struct pending_irq which makes it hard to swich to
a different VITS implementation if it doesn't use the same structure.
Rename struct its_device to struct vgic_its_device and move it to vgic.h,
so it can be defined by the VITS implementation. Add helper functions to
allow HW ITS to allocate/free and manage the instances this struct. This
seems like a sane approach, since the instances are already stored in the
struct vgic. Also move vgic_vcpu_inject_lpi to the vgic files for the same
reasons.
Signed-off-by: Mykyta Poturai <mykyta_poturai@epam.com>
---
xen/arch/arm/gic-v3-its.c | 208 ++++----------------------
xen/arch/arm/gic-v3-lpi.c | 20 ---
xen/arch/arm/include/asm/gic_v3_its.h | 2 +
xen/arch/arm/include/asm/vgic.h | 29 ++++
xen/arch/arm/vgic-v3-its.c | 206 ++++++++++++++++++++++++-
5 files changed, 258 insertions(+), 207 deletions(-)
diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c
index 8afcd9783b..cc3d82cde1 100644
--- a/xen/arch/arm/gic-v3-its.c
+++ b/xen/arch/arm/gic-v3-its.c
@@ -13,7 +13,6 @@
#include <xen/iocap.h>
#include <xen/libfdt/libfdt.h>
#include <xen/mm.h>
-#include <xen/rbtree.h>
#include <xen/sched.h>
#include <xen/sizes.h>
#include <asm/gic.h>
@@ -30,25 +29,6 @@
*/
LIST_HEAD(host_its_list);
-/*
- * Describes a device which is using the ITS and is used by a guest.
- * Since device IDs are per ITS (in contrast to vLPIs, which are per
- * guest), we have to differentiate between different virtual ITSes.
- * We use the doorbell address here, since this is a nice architectural
- * property of MSIs in general and we can easily get to the base address
- * of the ITS and look that up.
- */
-struct its_device {
- struct rb_node rbnode;
- struct host_its *hw_its;
- void *itt_addr;
- paddr_t guest_doorbell; /* Identifies the virtual ITS */
- uint32_t host_devid;
- uint32_t guest_devid;
- uint32_t eventids; /* Number of event IDs (MSIs) */
- uint32_t *host_lpi_blocks; /* Which LPIs are used on the host */
- struct pending_irq *pend_irqs; /* One struct per event */
-};
bool gicv3_its_host_has_its(void)
{
@@ -509,7 +489,7 @@ static int gicv3_its_init_single_its(struct host_its *hw_its)
* TODO: Investigate the interaction when a guest removes a device while
* some LPIs are still in flight.
*/
-static int remove_mapped_guest_device(struct its_device *dev)
+static int remove_mapped_guest_device(struct vgic_its_device *dev)
{
int ret = 0;
unsigned int i;
@@ -530,10 +510,7 @@ static int remove_mapped_guest_device(struct its_device *dev)
printk(XENLOG_WARNING "Can't unmap host ITS device 0x%x\n",
dev->host_devid);
- xfree(dev->itt_addr);
- xfree(dev->pend_irqs);
- xfree(dev->host_lpi_blocks);
- xfree(dev);
+ vgic_its_free_device(dev);
return 0;
}
@@ -551,24 +528,6 @@ static struct host_its *gicv3_its_find_by_doorbell(paddr_t doorbell_address)
return NULL;
}
-static int compare_its_guest_devices(struct its_device *dev,
- paddr_t vdoorbell, uint32_t vdevid)
-{
- if ( dev->guest_doorbell < vdoorbell )
- return -1;
-
- if ( dev->guest_doorbell > vdoorbell )
- return 1;
-
- if ( dev->guest_devid < vdevid )
- return -1;
-
- if ( dev->guest_devid > vdevid )
- return 1;
-
- return 0;
-}
-
/*
* On the host ITS @its, map @nr_events consecutive LPIs.
* The mapping connects a device @devid and event @eventid pair to LPI @lpi,
@@ -616,8 +575,7 @@ int gicv3_its_map_guest_device(struct domain *d,
{
void *itt_addr = NULL;
struct host_its *hw_its;
- struct its_device *dev = NULL;
- struct rb_node **new = &d->arch.vgic.its_devices.rb_node, *parent = NULL;
+ struct vgic_its_device *temp, *dev = NULL;
int i, ret = -ENOENT; /* "i" must be signed to check for >= 0 below. */
hw_its = gicv3_its_find_by_doorbell(host_doorbell);
@@ -643,36 +601,22 @@ int gicv3_its_map_guest_device(struct domain *d,
/* check for already existing mappings */
spin_lock(&d->arch.vgic.its_devices_lock);
- while ( *new )
+ temp = vgic_its_get_device(d, guest_doorbell, guest_devid);
+ if ( temp )
{
- struct its_device *temp;
- int cmp;
+ if ( !valid )
+ vgic_its_delete_device(d, temp);
- temp = rb_entry(*new, struct its_device, rbnode);
+ spin_unlock(&d->arch.vgic.its_devices_lock);
- parent = *new;
- cmp = compare_its_guest_devices(temp, guest_doorbell, guest_devid);
- if ( !cmp )
+ if ( valid )
{
- if ( !valid )
- rb_erase(&temp->rbnode, &d->arch.vgic.its_devices);
-
- spin_unlock(&d->arch.vgic.its_devices_lock);
-
- if ( valid )
- {
- printk(XENLOG_G_WARNING "d%d tried to remap guest ITS device 0x%x to host device 0x%x\n",
- d->domain_id, guest_devid, host_devid);
- return -EBUSY;
- }
-
- return remove_mapped_guest_device(temp);
+ printk(XENLOG_G_WARNING "d%d tried to remap guest ITS device 0x%x to host device 0x%x\n",
+ d->domain_id, guest_devid, host_devid);
+ return -EBUSY;
}
- if ( cmp > 0 )
- new = &((*new)->rb_left);
- else
- new = &((*new)->rb_right);
+ return remove_mapped_guest_device(temp);
}
if ( !valid )
@@ -688,7 +632,7 @@ int gicv3_its_map_guest_device(struct domain *d,
clean_and_invalidate_dcache_va_range(itt_addr,
nr_events * hw_its->itte_size);
- dev = xzalloc(struct its_device);
+ dev = vgic_its_alloc_device(nr_events);
if ( !dev )
goto out_unlock;
@@ -704,13 +648,6 @@ int gicv3_its_map_guest_device(struct domain *d,
* See the mailing list discussion for some background:
* https://lists.xen.org/archives/html/xen-devel/2017-03/msg03645.html
*/
- dev->pend_irqs = xzalloc_array(struct pending_irq, nr_events);
- if ( !dev->pend_irqs )
- goto out_unlock;
-
- dev->host_lpi_blocks = xzalloc_array(uint32_t, nr_events);
- if ( !dev->host_lpi_blocks )
- goto out_unlock;
ret = its_send_cmd_mapd(hw_its, host_devid, fls(nr_events - 1),
virt_to_maddr(itt_addr), true);
@@ -724,8 +661,7 @@ int gicv3_its_map_guest_device(struct domain *d,
dev->host_devid = host_devid;
dev->eventids = nr_events;
- rb_link_node(&dev->rbnode, parent, new);
- rb_insert_color(&dev->rbnode, &d->arch.vgic.its_devices);
+ vgic_its_add_device(d, dev);
spin_unlock(&d->arch.vgic.its_devices_lock);
@@ -771,117 +707,27 @@ out_unlock:
out:
if ( dev )
- {
- xfree(dev->pend_irqs);
- xfree(dev->host_lpi_blocks);
- }
+ vgic_its_free_device(dev);
+
xfree(itt_addr);
- xfree(dev);
return ret;
}
-/* Must be called with the its_device_lock held. */
-static struct its_device *get_its_device(struct domain *d, paddr_t vdoorbell,
- uint32_t vdevid)
-{
- struct rb_node *node = d->arch.vgic.its_devices.rb_node;
- struct its_device *dev;
-
- ASSERT(spin_is_locked(&d->arch.vgic.its_devices_lock));
-
- while (node)
- {
- int cmp;
-
- dev = rb_entry(node, struct its_device, rbnode);
- cmp = compare_its_guest_devices(dev, vdoorbell, vdevid);
-
- if ( !cmp )
- return dev;
-
- if ( cmp > 0 )
- node = node->rb_left;
- else
- node = node->rb_right;
- }
-
- return NULL;
-}
-
-static struct pending_irq *get_event_pending_irq(struct domain *d,
- paddr_t vdoorbell_address,
- uint32_t vdevid,
- uint32_t eventid,
- uint32_t *host_lpi)
-{
- struct its_device *dev;
- struct pending_irq *pirq = NULL;
-
- spin_lock(&d->arch.vgic.its_devices_lock);
- dev = get_its_device(d, vdoorbell_address, vdevid);
- if ( dev && eventid < dev->eventids )
- {
- pirq = &dev->pend_irqs[eventid];
- if ( host_lpi )
- *host_lpi = dev->host_lpi_blocks[eventid / LPI_BLOCK] +
- (eventid % LPI_BLOCK);
- }
- spin_unlock(&d->arch.vgic.its_devices_lock);
-
- return pirq;
-}
-
-struct pending_irq *gicv3_its_get_event_pending_irq(struct domain *d,
- paddr_t vdoorbell_address,
- uint32_t vdevid,
- uint32_t eventid)
-{
- return get_event_pending_irq(d, vdoorbell_address, vdevid, eventid, NULL);
-}
-
-int gicv3_remove_guest_event(struct domain *d, paddr_t vdoorbell_address,
- uint32_t vdevid, uint32_t eventid)
+uint32_t gicv3_its_get_host_lpi(struct domain *d, paddr_t vdoorbell_address,
+ uint32_t vdevid, uint32_t eventid)
{
+ struct vgic_its_device *dev;
uint32_t host_lpi = INVALID_LPI;
- if ( !get_event_pending_irq(d, vdoorbell_address, vdevid, eventid,
- &host_lpi) )
- return -EINVAL;
-
- if ( host_lpi == INVALID_LPI )
- return -EINVAL;
-
- gicv3_lpi_update_host_entry(host_lpi, d->domain_id, INVALID_LPI);
-
- return 0;
-}
-
-/*
- * Connects the event ID for an already assigned device to the given VCPU/vLPI
- * pair. The corresponding physical LPI is already mapped on the host side
- * (when assigning the physical device to the guest), so we just connect the
- * target VCPU/vLPI pair to that interrupt to inject it properly if it fires.
- * Returns a pointer to the already allocated struct pending_irq that is
- * meant to be used by that event.
- */
-struct pending_irq *gicv3_assign_guest_event(struct domain *d,
- paddr_t vdoorbell_address,
- uint32_t vdevid, uint32_t eventid,
- uint32_t virt_lpi)
-{
- struct pending_irq *pirq;
- uint32_t host_lpi = INVALID_LPI;
-
- pirq = get_event_pending_irq(d, vdoorbell_address, vdevid, eventid,
- &host_lpi);
-
- if ( !pirq )
- return NULL;
-
- gicv3_lpi_update_host_entry(host_lpi, d->domain_id, virt_lpi);
+ spin_lock(&d->arch.vgic.its_devices_lock);
+ dev = vgic_its_get_device(d, vdoorbell_address, vdevid);
+ if ( dev )
+ host_lpi = dev->host_lpi_blocks[eventid / LPI_BLOCK] +
+ (eventid % LPI_BLOCK);
- return pirq;
+ spin_unlock(&d->arch.vgic.its_devices_lock);
+ return host_lpi;
}
int gicv3_its_deny_access(struct domain *d)
diff --git a/xen/arch/arm/gic-v3-lpi.c b/xen/arch/arm/gic-v3-lpi.c
index eb0a5535e4..5f73b2b9f2 100644
--- a/xen/arch/arm/gic-v3-lpi.c
+++ b/xen/arch/arm/gic-v3-lpi.c
@@ -128,26 +128,6 @@ uint64_t gicv3_get_redist_address(unsigned int cpu, bool use_pta)
return per_cpu(lpi_redist, cpu).redist_id << 16;
}
-void vgic_vcpu_inject_lpi(struct domain *d, unsigned int virq)
-{
- /*
- * TODO: this assumes that the struct pending_irq stays valid all of
- * the time. We cannot properly protect this with the current locking
- * scheme, but the future per-IRQ lock will solve this problem.
- */
- struct pending_irq *p = irq_to_pending(d->vcpu[0], virq);
- unsigned int vcpu_id;
-
- if ( !p )
- return;
-
- vcpu_id = ACCESS_ONCE(p->lpi_vcpu_id);
- if ( vcpu_id >= d->max_vcpus )
- return;
-
- vgic_inject_irq(d, d->vcpu[vcpu_id], virq, true);
-}
-
/*
* Handle incoming LPIs, which are a bit special, because they are potentially
* numerous and also only get injected into guests. Treat them specially here,
diff --git a/xen/arch/arm/include/asm/gic_v3_its.h b/xen/arch/arm/include/asm/gic_v3_its.h
index c24d4752d0..f61a37a8fa 100644
--- a/xen/arch/arm/include/asm/gic_v3_its.h
+++ b/xen/arch/arm/include/asm/gic_v3_its.h
@@ -196,6 +196,8 @@ struct pending_irq *gicv3_assign_guest_event(struct domain *d,
uint32_t virt_lpi);
void gicv3_lpi_update_host_entry(uint32_t host_lpi, int domain_id,
uint32_t virt_lpi);
+uint32_t gicv3_its_get_host_lpi(struct domain *d, paddr_t vdoorbell_address,
+ uint32_t vdevid, uint32_t eventid);
#else
diff --git a/xen/arch/arm/include/asm/vgic.h b/xen/arch/arm/include/asm/vgic.h
index 922779ce14..56a3b6f828 100644
--- a/xen/arch/arm/include/asm/vgic.h
+++ b/xen/arch/arm/include/asm/vgic.h
@@ -317,6 +317,35 @@ extern bool vgic_migrate_irq(struct vcpu *old, struct vcpu *new, unsigned int ir
extern void vgic_check_inflight_irqs_pending(struct domain *d, struct vcpu *v,
unsigned int rank, uint32_t r);
+#ifdef CONFIG_HAS_ITS
+/*
+ * Describes a device which is using the ITS and is used by a guest.
+ * Since device IDs are per ITS (in contrast to vLPIs, which are per
+ * guest), we have to differentiate between different virtual ITSes.
+ * We use the doorbell address here, since this is a nice architectural
+ * property of MSIs in general and we can easily get to the base address
+ * of the ITS and look that up.
+ */
+struct vgic_its_device {
+ struct rb_node rbnode;
+ struct host_its *hw_its;
+ void *itt_addr;
+ paddr_t guest_doorbell; /* Identifies the virtual ITS */
+ uint32_t host_devid;
+ uint32_t guest_devid;
+ uint32_t eventids; /* Number of event IDs (MSIs) */
+ uint32_t *host_lpi_blocks; /* Which LPIs are used on the host */
+ struct pending_irq *pend_irqs; /* One struct per event */
+};
+
+struct vgic_its_device *vgic_its_alloc_device(int nr_events);
+void vgic_its_free_device(struct vgic_its_device *its_dev);
+int vgic_its_add_device(struct domain *d, struct vgic_its_device *its_dev);
+void vgic_its_delete_device(struct domain *d, struct vgic_its_device *its_dev);
+struct vgic_its_device* vgic_its_get_device(struct domain *d, paddr_t vdoorbell,
+ uint32_t vdevid);
+#endif /* CONFIG_HAS_ITS */
+
#endif /* !CONFIG_NEW_VGIC */
/*** Common VGIC functions used by Xen arch code ****/
diff --git a/xen/arch/arm/vgic-v3-its.c b/xen/arch/arm/vgic-v3-its.c
index 05429030b5..0d839f3fa4 100644
--- a/xen/arch/arm/vgic-v3-its.c
+++ b/xen/arch/arm/vgic-v3-its.c
@@ -266,6 +266,200 @@ static bool write_itte(struct virt_its *its, uint32_t devid,
return true;
}
+static struct pending_irq *get_event_pending_irq(struct domain *d,
+ paddr_t vdoorbell_address,
+ uint32_t vdevid,
+ uint32_t eventid)
+{
+ struct vgic_its_device *dev;
+ struct pending_irq *pirq = NULL;
+
+ spin_lock(&d->arch.vgic.its_devices_lock);
+ dev = vgic_its_get_device(d, vdoorbell_address, vdevid);
+ if ( dev && eventid < dev->eventids )
+ pirq = &dev->pend_irqs[eventid];
+
+ spin_unlock(&d->arch.vgic.its_devices_lock);
+
+ return pirq;
+}
+
+static int remove_guest_event(struct domain *d, paddr_t vdoorbell_address,
+ uint32_t vdevid, uint32_t eventid)
+{
+ uint32_t host_lpi = INVALID_LPI;
+
+ host_lpi = gicv3_its_get_host_lpi(d, vdoorbell_address, vdevid, eventid);
+ if ( host_lpi == INVALID_LPI )
+ return -EINVAL;
+
+ gicv3_lpi_update_host_entry(host_lpi, d->domain_id, INVALID_LPI);
+
+ return 0;
+}
+
+/*
+ * Connects the event ID for an already assigned device to the given VCPU/vLPI
+ * pair. The corresponding physical LPI is already mapped on the host side
+ * (when assigning the physical device to the guest), so we just connect the
+ * target VCPU/vLPI pair to that interrupt to inject it properly if it fires.
+ * Returns a pointer to the already allocated struct pending_irq that is
+ * meant to be used by that event.
+ */
+static struct pending_irq *assign_guest_event(struct domain *d,
+ paddr_t vdoorbell_address,
+ uint32_t vdevid, uint32_t eventid,
+ uint32_t virt_lpi)
+{
+ struct pending_irq *pirq;
+ uint32_t host_lpi = INVALID_LPI;
+
+ host_lpi = gicv3_its_get_host_lpi(d, vdoorbell_address, vdevid, eventid);
+ if ( host_lpi == INVALID_LPI )
+ return NULL;
+ pirq = get_event_pending_irq(d, vdoorbell_address, vdevid, eventid);
+ if ( !pirq )
+ return NULL;
+
+ gicv3_lpi_update_host_entry(host_lpi, d->domain_id, virt_lpi);
+
+ return pirq;
+}
+
+static int compare_its_guest_devices(struct vgic_its_device *dev,
+ paddr_t vdoorbell, uint32_t vdevid)
+{
+ if ( dev->guest_doorbell < vdoorbell )
+ return -1;
+
+ if ( dev->guest_doorbell > vdoorbell )
+ return 1;
+
+ if ( dev->guest_devid < vdevid )
+ return -1;
+
+ if ( dev->guest_devid > vdevid )
+ return 1;
+
+ return 0;
+}
+
+/* Must be called with the its_device_lock held. */
+struct vgic_its_device *vgic_its_get_device(struct domain *d, paddr_t vdoorbell,
+ uint32_t vdevid)
+{
+ struct rb_node *node = d->arch.vgic.its_devices.rb_node;
+ struct vgic_its_device *dev;
+
+ ASSERT(spin_is_locked(&d->arch.vgic.its_devices_lock));
+
+ while (node)
+ {
+ int cmp;
+
+ dev = rb_entry(node, struct vgic_its_device, rbnode);
+ cmp = compare_its_guest_devices(dev, vdoorbell, vdevid);
+
+ if ( !cmp )
+ return dev;
+
+ if ( cmp > 0 )
+ node = node->rb_left;
+ else
+ node = node->rb_right;
+ }
+
+ return NULL;
+}
+
+struct vgic_its_device *vgic_its_alloc_device(int nr_events)
+{
+ struct vgic_its_device *dev;
+
+ dev = xzalloc(struct vgic_its_device);
+ if ( !dev )
+ goto fail;
+
+ dev->pend_irqs = xzalloc_array(struct pending_irq, nr_events);
+ if ( !dev->pend_irqs )
+ goto fail_pend;
+
+ dev->host_lpi_blocks = xzalloc_array(uint32_t, nr_events);
+ if ( !dev->host_lpi_blocks )
+ goto fail_host_lpi;
+
+ return dev;
+fail_host_lpi:
+ xfree(dev->pend_irqs);
+fail_pend:
+ xfree(dev);
+fail:
+ return NULL;
+}
+
+void vgic_its_free_device(struct vgic_its_device *its_dev)
+{
+ xfree(its_dev->pend_irqs);
+ xfree(its_dev->host_lpi_blocks);
+ xfree(its_dev);
+}
+
+int vgic_its_add_device(struct domain *d, struct vgic_its_device *its_dev)
+{
+ struct rb_node **new = &d->arch.vgic.its_devices.rb_node, *parent = NULL;
+ while ( *new )
+ {
+ struct vgic_its_device *temp;
+ int cmp;
+
+ temp = rb_entry(*new, struct vgic_its_device, rbnode);
+
+ parent = *new;
+ cmp = compare_its_guest_devices(temp, its_dev->guest_doorbell,
+ its_dev->guest_devid);
+ if ( !cmp )
+ {
+ printk(XENLOG_ERR "Trying to add an already existing ITS device vdoorbell %lx vdevid %d\n",
+ its_dev->guest_doorbell, its_dev->guest_devid);
+ return -EINVAL;
+ }
+
+ if ( cmp > 0 )
+ new = &((*new)->rb_left);
+ else
+ new = &((*new)->rb_right);
+ }
+
+ rb_link_node(&its_dev->rbnode, parent, new);
+ rb_insert_color(&its_dev->rbnode, &d->arch.vgic.its_devices);
+ return 0;
+}
+
+void vgic_its_delete_device(struct domain *d, struct vgic_its_device *its_dev)
+{
+ rb_erase(&its_dev->rbnode, &d->arch.vgic.its_devices);
+}
+
+void vgic_vcpu_inject_lpi(struct domain *d, unsigned int virq)
+{
+ /*
+ * TODO: this assumes that the struct pending_irq stays valid all of
+ * the time. We cannot properly protect this with the current locking
+ * scheme, but the future per-IRQ lock will solve this problem.
+ */
+ struct pending_irq *p = irq_to_pending(d->vcpu[0], virq);
+ unsigned int vcpu_id;
+
+ if ( !p )
+ return;
+
+ vcpu_id = ACCESS_ONCE(p->lpi_vcpu_id);
+ if ( vcpu_id >= d->max_vcpus )
+ return;
+
+ vgic_inject_irq(d, d->vcpu[vcpu_id], virq, true);
+}
+
/**************************************
* Functions that handle ITS commands *
**************************************/
@@ -349,7 +543,7 @@ static int its_handle_clear(struct virt_its *its, uint64_t *cmdptr)
if ( !read_itte(its, devid, eventid, &vcpu, &vlpi) )
goto out_unlock;
- p = gicv3_its_get_event_pending_irq(its->d, its->doorbell_address,
+ p = get_event_pending_irq(its->d, its->doorbell_address,
devid, eventid);
/* Protect against an invalid LPI number. */
if ( unlikely(!p) )
@@ -471,7 +665,7 @@ static int its_handle_inv(struct virt_its *its, uint64_t *cmdptr)
if ( vlpi == INVALID_LPI )
goto out_unlock_its;
- p = gicv3_its_get_event_pending_irq(d, its->doorbell_address,
+ p = get_event_pending_irq(d, its->doorbell_address,
devid, eventid);
if ( unlikely(!p) )
goto out_unlock_its;
@@ -615,7 +809,7 @@ static int its_discard_event(struct virt_its *its,
spin_unlock_irqrestore(&vcpu->arch.vgic.lock, flags);
/* Remove the corresponding host LPI entry */
- return gicv3_remove_guest_event(its->d, its->doorbell_address,
+ return remove_guest_event(its->d, its->doorbell_address,
vdevid, vevid);
}
@@ -744,7 +938,7 @@ static int its_handle_mapti(struct virt_its *its, uint64_t *cmdptr)
* determined by the same device ID and event ID on the host side.
* This returns us the corresponding, still unused pending_irq.
*/
- pirq = gicv3_assign_guest_event(its->d, its->doorbell_address,
+ pirq = assign_guest_event(its->d, its->doorbell_address,
devid, eventid, intid);
if ( !pirq )
goto out_remove_mapping;
@@ -785,7 +979,7 @@ static int its_handle_mapti(struct virt_its *its, uint64_t *cmdptr)
* cleanup and return an error here in any case.
*/
out_remove_host_entry:
- gicv3_remove_guest_event(its->d, its->doorbell_address, devid, eventid);
+ remove_guest_event(its->d, its->doorbell_address, devid, eventid);
out_remove_mapping:
spin_lock(&its->its_lock);
@@ -819,7 +1013,7 @@ static int its_handle_movi(struct virt_its *its, uint64_t *cmdptr)
if ( !nvcpu )
goto out_unlock;
- p = gicv3_its_get_event_pending_irq(its->d, its->doorbell_address,
+ p = get_event_pending_irq(its->d, its->doorbell_address,
devid, eventid);
if ( unlikely(!p) )
goto out_unlock;
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [XEN PATCH v2 02/25] arm: new VGIC: Add GICv3 world switch backend
2023-11-10 12:56 [XEN PATCH v2 00/25] arm: Add GICv3 support to the New VGIC Mykyta Poturai
2023-11-10 12:56 ` [XEN PATCH v2 01/25] arm: vgic: its: Decouple HW and virtual ITS Mykyta Poturai
@ 2023-11-10 12:56 ` Mykyta Poturai
2023-11-10 12:56 ` [XEN PATCH v2 03/25] arm: new VGIC: Add GICv3 MMIO handling framework Mykyta Poturai
` (22 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Mykyta Poturai @ 2023-11-10 12:56 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org
Cc: Mykyta Poturai, Stefano Stabellini, Julien Grall,
Bertrand Marquis, Volodymyr Babchuk, Michal Orzel
As the GICv3 virtual interface registers differ from their GICv2
siblings, we need different handlers for processing maintenance
interrupts and reading/writing to the LRs.
Implement the respective handler functions and connect them to
existing code to be called if the host is using a GICv3.
This is based on Linux commit 59529f69f5048e0 by Marc Zyngier
Signed-off-by: Mykyta Poturai <mykyta_poturai@epam.com>
---
xen/arch/arm/vgic/vgic-v3.c | 206 ++++++++++++++++++++++++++++++++++++
xen/arch/arm/vgic/vgic.c | 18 +++-
xen/arch/arm/vgic/vgic.h | 13 ++-
3 files changed, 234 insertions(+), 3 deletions(-)
create mode 100644 xen/arch/arm/vgic/vgic-v3.c
diff --git a/xen/arch/arm/vgic/vgic-v3.c b/xen/arch/arm/vgic/vgic-v3.c
new file mode 100644
index 0000000000..b018ee6040
--- /dev/null
+++ b/xen/arch/arm/vgic/vgic-v3.c
@@ -0,0 +1,206 @@
+/*
+ * Imported from Linux ("new" KVM VGIC) and heavily adapted to Xen.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <asm/new_vgic.h>
+#include <asm/gic.h>
+#include <xen/sched.h>
+
+#include "vgic.h"
+
+/*
+ * transfer the content of the LRs back into the corresponding ap_list:
+ * - active bit is transferred as is
+ * - pending bit is
+ * - transferred as is in case of edge sensitive IRQs
+ * - set to the line-level (resample time) for level sensitive IRQs
+ */
+void vgic_v3_fold_lr_state(struct vcpu *vcpu)
+{
+ struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic;
+ unsigned int used_lrs = vcpu->arch.vgic.used_lrs;
+ unsigned long flags;
+ unsigned int lr;
+
+ if ( !used_lrs ) /* No LRs used, so nothing to sync back here. */
+ return;
+
+ gic_hw_ops->update_hcr_status(GICH_HCR_UIE, false);
+
+ for ( lr = 0; lr < used_lrs; lr++ )
+ {
+ struct gic_lr lr_val;
+ uint32_t intid;
+ struct vgic_irq *irq;
+ struct irq_desc *desc = NULL;
+
+ gic_hw_ops->read_lr(lr, &lr_val);
+
+ /*
+ * TODO: Possible optimization to avoid reading LRs:
+ * Read the ELRSR to find out which of our LRs have been cleared
+ * by the guest. We just need to know the IRQ number for those, which
+ * we could save in an array when populating the LRs.
+ * This trades one MMIO access (ELRSR) for possibly more than one (LRs),
+ * but requires some more code to save the IRQ number and to handle
+ * those finished IRQs according to the algorithm below.
+ * We need some numbers to justify this: chances are that we don't
+ * have many LRs in use most of the time, so we might not save much.
+ */
+ gic_hw_ops->clear_lr(lr);
+
+ intid = lr_val.virq;
+ irq = vgic_get_irq(vcpu->domain, vcpu, intid);
+
+ local_irq_save(flags);
+
+ /*
+ * We check this here without taking the lock, because the locking
+ * order forces us to do so. irq->hw is a "write-once" member, so
+ * whenever we read true, the associated hardware IRQ will not go
+ * away anymore.
+ * TODO: rework this if possible, either by using the desc pointer
+ * directly in struct vgic_irq or by changing the locking order.
+ * Especially if we ever drop the assumption above.
+ */
+ if ( irq->hw )
+ {
+ desc = irq_to_desc(irq->hwintid);
+ spin_lock(&desc->lock);
+ }
+
+ spin_lock(&irq->irq_lock);
+
+ /*
+ * If a hardware mapped IRQ has been handled for good, we need to
+ * clear the _IRQ_INPROGRESS bit to allow handling of new IRQs.
+ *
+ * TODO: This is probably racy, but is so already in the existing
+ * VGIC. A fix does not seem to be trivial.
+ */
+ if ( irq->hw && !lr_val.active && !lr_val.pending )
+ clear_bit(_IRQ_INPROGRESS, &desc->status);
+
+ /* Always preserve the active bit */
+ irq->active = lr_val.active;
+
+ /* Edge is the only case where we preserve the pending bit */
+ if ( irq->config == VGIC_CONFIG_EDGE && lr_val.pending )
+ {
+ irq->pending_latch = true;
+
+ if ( vgic_irq_is_sgi(intid) )
+ irq->source |= (1U << lr_val.virt.source);
+ }
+
+ /* Clear soft pending state when level irqs have been acked. */
+ if ( irq->config == VGIC_CONFIG_LEVEL && !lr_val.pending )
+ irq->pending_latch = false;
+
+ /*
+ * Level-triggered mapped IRQs are special because we only
+ * observe rising edges as input to the VGIC.
+ *
+ * If the guest never acked the interrupt we have to sample
+ * the physical line and set the line level, because the
+ * device state could have changed or we simply need to
+ * process the still pending interrupt later.
+ *
+ * If this causes us to lower the level, we have to also clear
+ * the physical active state, since we will otherwise never be
+ * told when the interrupt becomes asserted again.
+ */
+ if ( vgic_irq_is_mapped_level(irq) && lr_val.pending )
+ {
+ ASSERT(irq->hwintid >= VGIC_NR_PRIVATE_IRQS);
+
+ irq->line_level = gic_read_pending_state(desc);
+
+ if ( !irq->line_level )
+ gic_set_active_state(desc, false);
+ }
+
+ spin_unlock(&irq->irq_lock);
+ if ( desc )
+ spin_unlock(&desc->lock);
+ local_irq_restore(flags);
+
+ vgic_put_irq(vcpu->domain, irq);
+ }
+
+ gic_hw_ops->update_hcr_status(GICH_HCR_EN, false);
+ vgic_cpu->used_lrs = 0;
+}
+
+/* Requires the irq to be locked already */
+void vgic_v3_populate_lr(struct vcpu *vcpu, struct vgic_irq *irq, int lr)
+{
+ struct gic_lr lr_val = { 0 };
+
+ lr_val.virq = irq->intid;
+
+ if ( irq_is_pending(irq) )
+ {
+ lr_val.pending = true;
+
+ if ( irq->config == VGIC_CONFIG_EDGE )
+ irq->pending_latch = false;
+
+ if ( vgic_irq_is_sgi(irq->intid) &&
+ vcpu->domain->arch.vgic.version == VGIC_V2 )
+ {
+ uint32_t src = ffs(irq->source);
+
+ BUG_ON(!src);
+ lr_val.virt.source = (src - 1);
+ irq->source &= ~(1 << (src - 1));
+ if ( irq->source )
+ irq->pending_latch = true;
+ }
+ }
+
+ lr_val.active = irq->active;
+
+ if ( irq->hw )
+ {
+ lr_val.hw_status = true;
+ lr_val.hw.pirq = irq->hwintid;
+ /*
+ * Never set pending+active on a HW interrupt, as the
+ * pending state is kept at the physical distributor
+ * level.
+ */
+ if ( irq->active && irq_is_pending(irq) )
+ lr_val.pending = false;
+ }
+ else
+ {
+ if ( irq->config == VGIC_CONFIG_LEVEL )
+ lr_val.virt.eoi = true;
+ }
+
+ /*
+ * Level-triggered mapped IRQs are special because we only observe
+ * rising edges as input to the VGIC. We therefore lower the line
+ * level here, so that we can take new virtual IRQs. See
+ * vgic_v2_fold_lr_state for more info.
+ */
+ if ( vgic_irq_is_mapped_level(irq) && lr_val.pending )
+ irq->line_level = false;
+
+ /* The GICv2 LR only holds five bits of priority. */
+ lr_val.priority = irq->priority >> 3;
+
+ gic_hw_ops->write_lr(lr, &lr_val);
+}
diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c
index b9463a5f27..97ca827fc4 100644
--- a/xen/arch/arm/vgic/vgic.c
+++ b/xen/arch/arm/vgic/vgic.c
@@ -520,7 +520,14 @@ retry:
static void vgic_fold_lr_state(struct vcpu *vcpu)
{
- vgic_v2_fold_lr_state(vcpu);
+ if ( vcpu->domain->arch.vgic.version == GIC_V2 )
+ {
+ vgic_v2_fold_lr_state(vcpu);
+ }
+ else
+ {
+ vgic_v3_fold_lr_state(vcpu);
+ }
}
/* Requires the irq_lock to be held. */
@@ -529,7 +536,14 @@ static void vgic_populate_lr(struct vcpu *vcpu,
{
ASSERT(spin_is_locked(&irq->irq_lock));
- vgic_v2_populate_lr(vcpu, irq, lr);
+ if ( vcpu->domain->arch.vgic.version == GIC_V2 )
+ {
+ vgic_v2_populate_lr(vcpu, irq, lr);
+ }
+ else
+ {
+ vgic_v3_populate_lr(vcpu, irq, lr);
+ }
}
static void vgic_set_underflow(struct vcpu *vcpu)
diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h
index 534b24bcd3..2819569f30 100644
--- a/xen/arch/arm/vgic/vgic.h
+++ b/xen/arch/arm/vgic/vgic.h
@@ -70,8 +70,19 @@ void vgic_v2_enable(struct vcpu *vcpu);
int vgic_v2_map_resources(struct domain *d);
int vgic_register_dist_iodev(struct domain *d, gfn_t dist_base_fn,
enum vgic_type);
+#ifdef CONFIG_GICV3
+void vgic_v3_fold_lr_state(struct vcpu *vcpu);
+void vgic_v3_populate_lr(struct vcpu *vcpu, struct vgic_irq *irq, int lr);
+#else
+static inline void vgic_v3_fold_lr_state(struct vcpu *vcpu)
+{
+}
+static inline void vgic_v3_populate_lr(struct vcpu *vcpu, struct vgic_irq *irq, int lr)
+{
+}
+#endif /* CONFIG_GICV3 */
-#endif
+#endif /* __XEN_ARM_VGIC_VGIC_H__ */
/*
* Local variables:
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [XEN PATCH v2 03/25] arm: new VGIC: Add GICv3 MMIO handling framework
2023-11-10 12:56 [XEN PATCH v2 00/25] arm: Add GICv3 support to the New VGIC Mykyta Poturai
2023-11-10 12:56 ` [XEN PATCH v2 01/25] arm: vgic: its: Decouple HW and virtual ITS Mykyta Poturai
2023-11-10 12:56 ` [XEN PATCH v2 02/25] arm: new VGIC: Add GICv3 world switch backend Mykyta Poturai
@ 2023-11-10 12:56 ` Mykyta Poturai
2023-11-10 12:56 ` [XEN PATCH v2 05/25] arm: new VGIC: Add GICv3 redistributor IIDR and TYPER handler Mykyta Poturai
` (21 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Mykyta Poturai @ 2023-11-10 12:56 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org
Cc: Mykyta Poturai, Stefano Stabellini, Julien Grall,
Bertrand Marquis, Volodymyr Babchuk, Michal Orzel
Create a new file called vgic-mmio-v3.c and describe the GICv3
distributor and redistributor registers there.
Also we provide a function to deal with the registration of the
separate redistributor frames per VCPU and allocation of redistributor
regions.
Based on Linux commits:
ed9b8cefa91695 by Andre Przywara
1aab6f468c10a1 by Christoffer Dall
ccc27bf5be7b78 by Eric Auger
Signed-off-by: Mykyta Poturai <mykyta_poturai@epam.com>
---
xen/arch/arm/include/asm/gic_v3_defs.h | 2 +
xen/arch/arm/include/asm/new_vgic.h | 18 +-
xen/arch/arm/vgic/vgic-init.c | 10 +-
xen/arch/arm/vgic/vgic-mmio-v3.c | 435 +++++++++++++++++++++++++
xen/arch/arm/vgic/vgic-mmio.c | 3 +
xen/arch/arm/vgic/vgic.h | 15 +
6 files changed, 475 insertions(+), 8 deletions(-)
create mode 100644 xen/arch/arm/vgic/vgic-mmio-v3.c
diff --git a/xen/arch/arm/include/asm/gic_v3_defs.h b/xen/arch/arm/include/asm/gic_v3_defs.h
index 227533868f..b7059635d7 100644
--- a/xen/arch/arm/include/asm/gic_v3_defs.h
+++ b/xen/arch/arm/include/asm/gic_v3_defs.h
@@ -35,6 +35,7 @@
#define GICD_IROUTER (0x6000)
#define GICD_IROUTER32 (0x6100)
#define GICD_IROUTER1019 (0x7FD8)
+#define GICD_IDREGS (0xFFD0)
#define GICD_PIDR2 (0xFFE8)
/* Common between GICD_PIDR2 and GICR_PIDR2 */
@@ -89,6 +90,7 @@
#define GICR_INVLPIR (0x00A0)
#define GICR_INVALLR (0x00B0)
#define GICR_SYNCR (0x00C0)
+#define GICR_IDREGS GICD_IDREGS
#define GICR_PIDR2 GICD_PIDR2
/* GICR for SGI's & PPI's */
diff --git a/xen/arch/arm/include/asm/new_vgic.h b/xen/arch/arm/include/asm/new_vgic.h
index 1e76213893..11d8f71851 100644
--- a/xen/arch/arm/include/asm/new_vgic.h
+++ b/xen/arch/arm/include/asm/new_vgic.h
@@ -31,6 +31,8 @@
#define VGIC_MAX_SPI 1019
#define VGIC_MAX_RESERVED 1023
#define VGIC_MIN_LPI 8192
+#define VGIC_V3_DIST_SIZE SZ_64K
+#define VGIC_V3_REDIST_SIZE (2 * SZ_64K)
#define irq_is_ppi(irq) ((irq) >= VGIC_NR_SGIS && (irq) < VGIC_NR_PRIVATE_IRQS)
#define irq_is_spi(irq) ((irq) >= VGIC_NR_PRIVATE_IRQS && \
@@ -94,6 +96,14 @@ enum iodev_type {
IODEV_REDIST,
};
+struct vgic_redist_region {
+ uint32_t index;
+ paddr_t base;
+ uint32_t count; /* number of redistributors or 0 if single region */
+ uint32_t free_index; /* index of the next free redistributor */
+ struct list_head list;
+};
+
struct vgic_io_device {
gfn_t base_fn;
struct vcpu *redist_vcpu;
@@ -121,11 +131,7 @@ struct vgic_dist {
/* either a GICv2 CPU interface */
paddr_t cbase;
/* or a number of GICv3 redistributor regions */
- struct
- {
- paddr_t vgic_redist_base;
- paddr_t vgic_redist_free_offset;
- };
+ struct list_head rd_regions;
};
paddr_t csize; /* CPU interface size */
paddr_t vbase; /* virtual CPU interface base address */
@@ -174,6 +180,8 @@ struct vgic_cpu {
* parts of the redistributor.
*/
struct vgic_io_device rd_iodev;
+ struct vgic_redist_region *rdreg;
+ uint32_t rdreg_index;
struct vgic_io_device sgi_iodev;
/* Contains the attributes and gpa of the LPI pending tables. */
diff --git a/xen/arch/arm/vgic/vgic-init.c b/xen/arch/arm/vgic/vgic-init.c
index f8d7d3a226..c3b34be192 100644
--- a/xen/arch/arm/vgic/vgic-init.c
+++ b/xen/arch/arm/vgic/vgic-init.c
@@ -107,14 +107,18 @@ int domain_vgic_register(struct domain *d, unsigned int *mmio_count)
{
case GIC_V2:
*mmio_count = 1;
+ d->arch.vgic.cbase = VGIC_ADDR_UNDEF;
break;
+ case GIC_V3:
+ *mmio_count = 2;
+ INIT_LIST_HEAD(&d->arch.vgic.rd_regions);
+ break;
+
default:
BUG();
}
d->arch.vgic.dbase = VGIC_ADDR_UNDEF;
- d->arch.vgic.cbase = VGIC_ADDR_UNDEF;
- d->arch.vgic.vgic_redist_base = VGIC_ADDR_UNDEF;
return 0;
}
@@ -207,7 +211,7 @@ int vcpu_vgic_init(struct vcpu *v)
if ( gic_hw_version() == GIC_V2 )
vgic_v2_enable(v);
else
- ret = -ENXIO;
+ vgic_register_redist_iodev(v);
return ret;
}
diff --git a/xen/arch/arm/vgic/vgic-mmio-v3.c b/xen/arch/arm/vgic/vgic-mmio-v3.c
new file mode 100644
index 0000000000..b79a63ce3e
--- /dev/null
+++ b/xen/arch/arm/vgic/vgic-mmio-v3.c
@@ -0,0 +1,435 @@
+/*
+ * VGICv3 MMIO handling functions
+ * Imported from Linux ("new" KVM VGIC) and heavily adapted to Xen.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <xen/bitops.h>
+#include <xen/sched.h>
+#include <xen/sizes.h>
+#include <asm/new_vgic.h>
+#include <asm/gic_v3_defs.h>
+#include <asm/vreg.h>
+
+#include "vgic.h"
+#include "vgic-mmio.h"
+
+static const struct vgic_register_region vgic_v3_dist_registers[] = {
+ REGISTER_DESC_WITH_LENGTH(GICD_CTLR,
+ vgic_mmio_read_raz, vgic_mmio_write_wi,
+ 16, VGIC_ACCESS_32bit),
+ REGISTER_DESC_WITH_LENGTH(GICD_STATUSR,
+ vgic_mmio_read_rao, vgic_mmio_write_wi, 4,
+ VGIC_ACCESS_32bit),
+ REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_IGROUPR,
+ vgic_mmio_read_rao, vgic_mmio_write_wi, 1,
+ VGIC_ACCESS_32bit),
+ REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ISENABLER,
+ vgic_mmio_read_enable, vgic_mmio_write_senable, 1,
+ VGIC_ACCESS_32bit),
+ REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ICENABLER,
+ vgic_mmio_read_enable, vgic_mmio_write_cenable, 1,
+ VGIC_ACCESS_32bit),
+ REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ISPENDR,
+ vgic_mmio_read_pending, vgic_mmio_write_spending, 1,
+ VGIC_ACCESS_32bit),
+ REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ICPENDR,
+ vgic_mmio_read_pending, vgic_mmio_write_cpending, 1,
+ VGIC_ACCESS_32bit),
+ REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ISACTIVER,
+ vgic_mmio_read_active, vgic_mmio_write_sactive, 1,
+ VGIC_ACCESS_32bit),
+ REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ICACTIVER,
+ vgic_mmio_read_active, vgic_mmio_write_cactive,
+ 1, VGIC_ACCESS_32bit),
+ REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_IPRIORITYR,
+ vgic_mmio_read_priority, vgic_mmio_write_priority,
+ 8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
+ REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ITARGETSR,
+ vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
+ VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
+ REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ICFGR,
+ vgic_mmio_read_config, vgic_mmio_write_config, 2,
+ VGIC_ACCESS_32bit),
+ REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_IGRPMODR,
+ vgic_mmio_read_raz, vgic_mmio_write_wi, 1,
+ VGIC_ACCESS_32bit),
+ REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_IROUTER,
+ vgic_mmio_read_raz, vgic_mmio_write_wi, 64,
+ VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
+ REGISTER_DESC_WITH_LENGTH(GICD_IDREGS,
+ vgic_mmio_read_raz, vgic_mmio_write_wi, 48,
+ VGIC_ACCESS_32bit),
+};
+
+static const struct vgic_register_region vgic_v3_rd_registers[] = {
+ /* RD_base registers */
+ REGISTER_DESC_WITH_LENGTH(GICR_CTLR,
+ vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
+ VGIC_ACCESS_32bit),
+ REGISTER_DESC_WITH_LENGTH(GICR_STATUSR,
+ vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
+ VGIC_ACCESS_32bit),
+ REGISTER_DESC_WITH_LENGTH(GICR_IIDR,
+ vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
+ VGIC_ACCESS_32bit),
+ REGISTER_DESC_WITH_LENGTH(GICR_TYPER,
+ vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
+ VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
+ REGISTER_DESC_WITH_LENGTH(GICR_WAKER,
+ vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
+ VGIC_ACCESS_32bit),
+ REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER,
+ vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
+ VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
+ REGISTER_DESC_WITH_LENGTH(GICR_PENDBASER,
+ vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
+ VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
+ REGISTER_DESC_WITH_LENGTH(GICR_INVLPIR,
+ vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
+ VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
+ REGISTER_DESC_WITH_LENGTH(GICR_INVALLR,
+ vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
+ VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
+ REGISTER_DESC_WITH_LENGTH(GICR_SYNCR,
+ vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
+ VGIC_ACCESS_32bit),
+ REGISTER_DESC_WITH_LENGTH(GICR_IDREGS,
+ vgic_mmio_read_raz, vgic_mmio_write_wi, 48,
+ VGIC_ACCESS_32bit),
+ /* SGI_base registers */
+ REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IGROUPR0,
+ vgic_mmio_read_rao, vgic_mmio_write_wi, 4,
+ VGIC_ACCESS_32bit),
+ REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_ISENABLER0,
+ vgic_mmio_read_enable, vgic_mmio_write_senable, 4,
+ VGIC_ACCESS_32bit),
+ REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_ICENABLER0,
+ vgic_mmio_read_enable, vgic_mmio_write_cenable, 4,
+ VGIC_ACCESS_32bit),
+ REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_ISPENDR0,
+ vgic_mmio_read_pending, vgic_mmio_write_spending, 4,
+ VGIC_ACCESS_32bit),
+ REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_ICPENDR0,
+ vgic_mmio_read_pending, vgic_mmio_write_cpending,4,
+ VGIC_ACCESS_32bit),
+ REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_ISACTIVER0,
+ vgic_mmio_read_active, vgic_mmio_write_sactive, 4,
+ VGIC_ACCESS_32bit),
+ REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_ICACTIVER0,
+ vgic_mmio_read_active, vgic_mmio_write_cactive, 4,
+ VGIC_ACCESS_32bit),
+ REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IPRIORITYR0,
+ vgic_mmio_read_priority, vgic_mmio_write_priority, 32,
+ VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
+ REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_ICFGR0,
+ vgic_mmio_read_config, vgic_mmio_write_config, 8,
+ VGIC_ACCESS_32bit),
+ REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IGRPMODR0,
+ vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
+ VGIC_ACCESS_32bit),
+ REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_NSACR,
+ vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
+ VGIC_ACCESS_32bit),
+};
+
+unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev)
+{
+ dev->regions = vgic_v3_dist_registers;
+ dev->nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);
+
+ return SZ_64K;
+}
+
+static bool vgic_v3_redist_region_full(struct vgic_redist_region *region)
+{
+ if ( !region->count )
+ return false;
+
+ return (region->free_index >= region->count);
+}
+
+/**
+ * vgic_v3_rdist_free_slot - Look up registered rdist regions and identify one
+ * which has free space to put a new rdist region.
+ *
+ * @rd_regions: redistributor region list head
+ *
+ * A redistributor regions maps n redistributors, n = region size / (2 x 64kB).
+ * Stride between redistributors is 0 and regions are filled in the index order.
+ *
+ * Return: the redist region handle, if any, that has space to map a new rdist
+ * region.
+ */
+static struct vgic_redist_region *vgic_v3_rdist_free_slot(struct list_head *rd_regions)
+{
+ struct vgic_redist_region *rdreg;
+
+ list_for_each_entry(rdreg, rd_regions, list)
+ {
+ if ( !vgic_v3_redist_region_full(rdreg) )
+ return rdreg;
+ }
+ return NULL;
+}
+
+
+/**
+ * vgic_register_redist_iodev - register a single redist iodev
+ * @vcpu: The VCPU to which the redistributor belongs
+ *
+ * Register a KVM iodev for this VCPU's redistributor using the address
+ * provided.
+ *
+ * Return 0 on success, -ERRNO otherwise.
+ */
+int vgic_register_redist_iodev(struct vcpu *vcpu)
+{
+ struct domain *d = vcpu->domain;
+ struct vgic_dist *vgic = &d->arch.vgic;
+ struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic;
+ struct vgic_io_device *rd_dev = &vcpu->arch.vgic.rd_iodev;
+ struct vgic_redist_region *rdreg;
+ paddr_t rd_base;
+
+ /*
+ * We may be creating VCPUs before having set the base address for the
+ * redistributor region, in which case we will come back to this
+ * function for all VCPUs when the base address is set. Just return
+ * without doing any work for now.
+ */
+ rdreg = vgic_v3_rdist_free_slot(&vgic->rd_regions);
+ if ( !rdreg )
+ return 0;
+
+ vgic_cpu->rdreg = rdreg;
+ vgic_cpu->rdreg_index = rdreg->free_index;
+
+ rd_base = rdreg->base + rdreg->free_index * VGIC_V3_REDIST_SIZE;
+
+ rd_dev->base_fn = gaddr_to_gfn(rd_base);
+ rd_dev->iodev_type = IODEV_REDIST;
+ rd_dev->regions = vgic_v3_rd_registers;
+ rd_dev->nr_regions = ARRAY_SIZE(vgic_v3_rd_registers);
+ rd_dev->redist_vcpu = vcpu;
+
+ register_mmio_handler(d, &vgic_io_ops, rd_base, VGIC_V3_REDIST_SIZE,
+ rd_dev);
+
+ rdreg->free_index++;
+ return 0;
+}
+
+static int vgic_register_all_redist_iodevs(struct domain *d)
+{
+ struct vcpu *vcpu;
+ int ret = 0;
+
+ for_each_vcpu(d, vcpu)
+ {
+ ret = vgic_register_redist_iodev(vcpu);
+ if ( ret )
+ break;
+ }
+
+ if ( ret )
+ {
+ printk(XENLOG_ERR "Failed to register redistributor iodev\n");
+ }
+
+ return ret;
+}
+
+static inline size_t vgic_v3_rd_region_size(struct domain *d,
+ struct vgic_redist_region *rdreg)
+{
+ if ( !rdreg->count )
+ return d->max_vcpus * VGIC_V3_REDIST_SIZE;
+ else
+ return rdreg->count * VGIC_V3_REDIST_SIZE;
+}
+
+/**
+ * vgic_v3_rdist_overlap - check if a region overlaps with any
+ * existing redistributor region
+ *
+ * @kvm: kvm handle
+ * @base: base of the region
+ * @size: size of region
+ *
+ * Return: true if there is an overlap
+ */
+bool vgic_v3_rdist_overlap(struct domain *domain, paddr_t base, size_t size)
+{
+ struct vgic_dist *d = &domain->arch.vgic;
+ struct vgic_redist_region *rdreg;
+
+ list_for_each_entry(rdreg, &d->rd_regions, list)
+ {
+ if ( (base + size > rdreg->base) &&
+ (base < rdreg->base + vgic_v3_rd_region_size(domain, rdreg)) )
+ return true;
+ }
+ return false;
+}
+
+static inline bool vgic_dist_overlap(struct domain *domain, paddr_t base,
+ size_t size)
+{
+ struct vgic_dist *d = &domain->arch.vgic;
+
+ return (base + size > d->dbase) && (base < d->dbase + VGIC_V3_DIST_SIZE);
+}
+
+struct vgic_redist_region *vgic_v3_rdist_region_from_index(struct domain *d,
+ u32 index)
+{
+ struct list_head *rd_regions = &d->arch.vgic.rd_regions;
+ struct vgic_redist_region *rdreg;
+
+ list_for_each_entry(rdreg, rd_regions, list)
+ {
+ if ( rdreg->index == index )
+ return rdreg;
+ }
+ return NULL;
+}
+
+int vgic_check_iorange(paddr_t ioaddr, paddr_t addr, paddr_t alignment,
+ paddr_t size)
+{
+ if ( !IS_VGIC_ADDR_UNDEF(ioaddr) )
+ return -EEXIST;
+
+ if ( !IS_ALIGNED(addr, alignment) || !IS_ALIGNED(size, alignment) )
+ return -EINVAL;
+
+ if ( addr + size < addr )
+ return -EINVAL;
+
+ return 0;
+}
+
+/**
+ * vgic_v3_alloc_redist_region - Allocate a new redistributor region
+ *
+ * Performs various checks before inserting the rdist region in the list.
+ * Those tests depend on whether the size of the rdist region is known
+ * (ie. count != 0). The list is sorted by rdist region index.
+ *
+ * @kvm: kvm handle
+ * @index: redist region index
+ * @base: base of the new rdist region
+ * @count: number of redistributors the region is made of (0 in the old style
+ * single region, whose size is induced from the number of vcpus)
+ *
+ * Return 0 on success, < 0 otherwise
+ */
+static int vgic_v3_alloc_redist_region(struct domain *domain, uint32_t index,
+ paddr_t base, uint32_t count)
+{
+ struct vgic_dist *d = &domain->arch.vgic;
+ struct vgic_redist_region *rdreg;
+ struct list_head *rd_regions = &d->rd_regions;
+ int nr_vcpus = domain->max_vcpus;
+ size_t size = count ? count * VGIC_V3_REDIST_SIZE
+ : nr_vcpus * VGIC_V3_REDIST_SIZE;
+ int ret;
+
+ /* cross the end of memory ? */
+ if ( base + size < base )
+ return -EINVAL;
+
+ if ( list_empty(rd_regions) )
+ {
+ if ( index != 0 )
+ return -EINVAL;
+ }
+ else
+ {
+ rdreg = list_last_entry(rd_regions, struct vgic_redist_region, list);
+
+ /* Don't mix single region and discrete redist regions */
+ if ( !count && rdreg->count )
+ return -EINVAL;
+
+ if ( !count )
+ return -EEXIST;
+
+ if ( index != rdreg->index + 1 )
+ return -EINVAL;
+ }
+
+ /*
+ * For legacy single-region redistributor regions (!count),
+ * check that the redistributor region does not overlap with the
+ * distributor's address space.
+ */
+ if ( !count && !IS_VGIC_ADDR_UNDEF(d->dbase) &&
+ vgic_dist_overlap(domain, base, size) )
+ return -EINVAL;
+
+ /* collision with any other rdist region? */
+ if ( vgic_v3_rdist_overlap(domain, base, size) )
+ return -EINVAL;
+
+ rdreg = xzalloc(struct vgic_redist_region);
+ if ( !rdreg )
+ return -ENOMEM;
+
+ rdreg->base = VGIC_ADDR_UNDEF;
+
+ ret = vgic_check_iorange(rdreg->base, base, SZ_64K, size);
+ if ( ret )
+ goto free;
+
+ rdreg->base = base;
+ rdreg->count = count;
+ rdreg->free_index = 0;
+ rdreg->index = index;
+
+ list_add_tail(&rdreg->list, rd_regions);
+ return 0;
+free:
+ xfree(rdreg);
+ return ret;
+}
+
+void vgic_v3_free_redist_region(struct vgic_redist_region *rdreg)
+{
+ list_del(&rdreg->list);
+ xfree(rdreg);
+}
+
+int vgic_v3_set_redist_base(struct domain *d, u32 index, u64 addr, u32 count)
+{
+ int ret;
+
+ ret = vgic_v3_alloc_redist_region(d, index, addr, count);
+ if ( ret )
+ return ret;
+
+ /*
+ * Register iodevs for each existing VCPU. Adding more VCPUs
+ * afterwards will register the iodevs when needed.
+ */
+ ret = vgic_register_all_redist_iodevs(d);
+ if ( ret )
+ {
+ struct vgic_redist_region *rdreg;
+
+ rdreg = vgic_v3_rdist_region_from_index(d, index);
+ vgic_v3_free_redist_region(rdreg);
+ return ret;
+ }
+
+ return 0;
+}
diff --git a/xen/arch/arm/vgic/vgic-mmio.c b/xen/arch/arm/vgic/vgic-mmio.c
index 5d935a7301..1c3f861887 100644
--- a/xen/arch/arm/vgic/vgic-mmio.c
+++ b/xen/arch/arm/vgic/vgic-mmio.c
@@ -619,6 +619,9 @@ int vgic_register_dist_iodev(struct domain *d, gfn_t dist_base_fn,
case VGIC_V2:
len = vgic_v2_init_dist_iodev(io_device);
break;
+ case VGIC_V3:
+ len = vgic_v3_init_dist_iodev(io_device);
+ break;
default:
BUG();
}
diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h
index 2819569f30..a8e3ef5970 100644
--- a/xen/arch/arm/vgic/vgic.h
+++ b/xen/arch/arm/vgic/vgic.h
@@ -73,6 +73,9 @@ int vgic_register_dist_iodev(struct domain *d, gfn_t dist_base_fn,
#ifdef CONFIG_GICV3
void vgic_v3_fold_lr_state(struct vcpu *vcpu);
void vgic_v3_populate_lr(struct vcpu *vcpu, struct vgic_irq *irq, int lr);
+unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev);
+int vgic_v3_set_redist_base(struct domain *d, u32 index, u64 addr, u32 count);
+int vgic_register_redist_iodev(struct vcpu *vcpu);
#else
static inline void vgic_v3_fold_lr_state(struct vcpu *vcpu)
{
@@ -80,6 +83,18 @@ static inline void vgic_v3_fold_lr_state(struct vcpu *vcpu)
static inline void vgic_v3_populate_lr(struct vcpu *vcpu, struct vgic_irq *irq, int lr)
{
}
+static inline unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev)
+{
+ return 0;
+}
+static inline int vgic_v3_set_redist_base(struct domain *d, u32 index, u64 addr, u32 count)
+{
+ return 0;
+}
+static inline int vgic_register_redist_iodev(struct vcpu *vcpu)
+{
+ return 0;
+}
#endif /* CONFIG_GICV3 */
#endif /* __XEN_ARM_VGIC_VGIC_H__ */
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [XEN PATCH v2 05/25] arm: new VGIC: Add GICv3 redistributor IIDR and TYPER handler
2023-11-10 12:56 [XEN PATCH v2 00/25] arm: Add GICv3 support to the New VGIC Mykyta Poturai
` (2 preceding siblings ...)
2023-11-10 12:56 ` [XEN PATCH v2 03/25] arm: new VGIC: Add GICv3 MMIO handling framework Mykyta Poturai
@ 2023-11-10 12:56 ` Mykyta Poturai
2023-11-10 12:56 ` [XEN PATCH v2 04/25] arm: new VGIC: Add GICv3 CTLR, IIDR, TYPER handlers Mykyta Poturai
` (20 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Mykyta Poturai @ 2023-11-10 12:56 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org
Cc: Mykyta Poturai, Stefano Stabellini, Julien Grall,
Bertrand Marquis, Volodymyr Babchuk, Michal Orzel
The redistributor TYPER tells the OS about the associated MPIDR,
also the LAST bit is crucial to determine the number of redistributors.
Based on Linux commit 741972d8a69ce74 by Andre Przywara
Signed-off-by: Mykyta Poturai <mykyta_poturai@epam.com>
---
xen/arch/arm/vgic/vgic-mmio-v3.c | 65 +++++++++++++++++++++++++++++++-
1 file changed, 63 insertions(+), 2 deletions(-)
diff --git a/xen/arch/arm/vgic/vgic-mmio-v3.c b/xen/arch/arm/vgic/vgic-mmio-v3.c
index beb3d6ad2a..707a38c727 100644
--- a/xen/arch/arm/vgic/vgic-mmio-v3.c
+++ b/xen/arch/arm/vgic/vgic-mmio-v3.c
@@ -22,6 +22,13 @@
#include "vgic.h"
#include "vgic-mmio.h"
+/* extract @num bytes at @offset bytes offset in data */
+unsigned long extract_bytes(uint64_t data, unsigned int offset,
+ unsigned int num)
+{
+ return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0);
+}
+
/*
* The Revision field in the IIDR have the following meanings:
*
@@ -91,6 +98,60 @@ static void vgic_mmio_write_v3_misc(struct vcpu *vcpu, paddr_t addr,
}
}
+static bool vgic_mmio_vcpu_rdist_is_last(struct vcpu *vcpu)
+{
+ struct vgic_dist *vgic = &vcpu->domain->arch.vgic;
+ struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic;
+ struct vgic_redist_region *iter, *rdreg = vgic_cpu->rdreg;
+
+ if ( !rdreg )
+ return false;
+
+ if ( vgic_cpu->rdreg_index < rdreg->free_index - 1 )
+ {
+ return false;
+ }
+ else if ( rdreg->count && vgic_cpu->rdreg_index == (rdreg->count - 1) )
+ {
+ struct list_head *rd_regions = &vgic->rd_regions;
+ paddr_t end = rdreg->base + rdreg->count * VGIC_V3_REDIST_SIZE;
+
+ /*
+ * the rdist is the last one of the redist region,
+ * check whether there is no other contiguous rdist region
+ */
+ list_for_each_entry(iter, rd_regions, list)
+ {
+ if ( iter->base == end && iter->free_index > 0 )
+ return false;
+ }
+ }
+ return true;
+}
+
+static unsigned long vgic_mmio_read_v3r_typer(struct vcpu *vcpu, paddr_t addr,
+ unsigned int len)
+{
+ unsigned long mpidr = vcpuid_to_vaffinity(vcpu->vcpu_id);
+ int target_vcpu_id = vcpu->vcpu_id;
+ u64 value;
+
+ value = (u64)(mpidr & GENMASK(23, 0)) << 32;
+ value |= ((target_vcpu_id & 0xffff) << 8);
+
+ if ( vgic_mmio_vcpu_rdist_is_last(vcpu) )
+ value |= GICR_TYPER_LAST;
+
+ return extract_bytes(value, addr & 7, len);
+}
+
+static unsigned long vgic_mmio_read_v3r_iidr(struct vcpu *vcpu, paddr_t addr,
+ unsigned int len)
+{
+ return (PRODUCT_ID_KVM << 24) | (VARIANT_ID_XEN << 16) |
+ (IMPLEMENTER_ARM << 0);
+}
+
static const struct vgic_register_region vgic_v3_dist_registers[] = {
REGISTER_DESC_WITH_LENGTH(GICD_CTLR,
vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc,
@@ -148,10 +209,10 @@ static const struct vgic_register_region vgic_v3_rd_registers[] = {
vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
VGIC_ACCESS_32bit),
REGISTER_DESC_WITH_LENGTH(GICR_IIDR,
- vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
+ vgic_mmio_read_v3r_iidr, vgic_mmio_write_wi, 4,
VGIC_ACCESS_32bit),
REGISTER_DESC_WITH_LENGTH(GICR_TYPER,
- vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
+ vgic_mmio_read_v3r_typer, vgic_mmio_write_wi, 8,
VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
REGISTER_DESC_WITH_LENGTH(GICR_WAKER,
vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [XEN PATCH v2 04/25] arm: new VGIC: Add GICv3 CTLR, IIDR, TYPER handlers
2023-11-10 12:56 [XEN PATCH v2 00/25] arm: Add GICv3 support to the New VGIC Mykyta Poturai
` (3 preceding siblings ...)
2023-11-10 12:56 ` [XEN PATCH v2 05/25] arm: new VGIC: Add GICv3 redistributor IIDR and TYPER handler Mykyta Poturai
@ 2023-11-10 12:56 ` Mykyta Poturai
2023-11-10 12:56 ` [XEN PATCH v2 08/25] arm: new VGIC: Add GICv3 SGI system register trap handler Mykyta Poturai
` (19 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Mykyta Poturai @ 2023-11-10 12:56 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org
Cc: Mykyta Poturai, Stefano Stabellini, Julien Grall,
Bertrand Marquis, Volodymyr Babchuk, Michal Orzel
As in the GICv2 emulation we handle those three registers in one
function.
Based on Linux commit fd59ed3be17e41 by Andre Przywara
Signed-off-by: Mykyta Poturai <mykyta_poturai@epam.com>
---
xen/arch/arm/include/asm/gic_v3_defs.h | 2 +
xen/arch/arm/vgic/vgic-mmio-v3.c | 71 +++++++++++++++++++++++++-
xen/arch/arm/vgic/vgic.h | 1 +
3 files changed, 73 insertions(+), 1 deletion(-)
diff --git a/xen/arch/arm/include/asm/gic_v3_defs.h b/xen/arch/arm/include/asm/gic_v3_defs.h
index b7059635d7..e0d536e887 100644
--- a/xen/arch/arm/include/asm/gic_v3_defs.h
+++ b/xen/arch/arm/include/asm/gic_v3_defs.h
@@ -25,6 +25,7 @@
* Common GICD registers are defined in gic.h
*/
+#define GICD_TYPER2 (0x00C)
#define GICD_STATUSR (0x010)
#define GICD_SETSPI_NSR (0x040)
#define GICD_CLRSPI_NSR (0x048)
@@ -57,6 +58,7 @@
#define GICD_TYPE_LPIS (1U << 17)
#define GICD_CTLR_RWP (1UL << 31)
+#define GICD_CTLR_DS (1U << 6)
#define GICD_CTLR_ARE_NS (1U << 4)
#define GICD_CTLR_ENABLE_G1A (1U << 1)
#define GICD_CTLR_ENABLE_G1 (1U << 0)
diff --git a/xen/arch/arm/vgic/vgic-mmio-v3.c b/xen/arch/arm/vgic/vgic-mmio-v3.c
index b79a63ce3e..beb3d6ad2a 100644
--- a/xen/arch/arm/vgic/vgic-mmio-v3.c
+++ b/xen/arch/arm/vgic/vgic-mmio-v3.c
@@ -22,9 +22,78 @@
#include "vgic.h"
#include "vgic-mmio.h"
+/*
+ * The Revision field in the IIDR have the following meanings:
+ *
+ * Revision 2: Interrupt groups are guest-configurable and signaled using
+ * their configured groups.
+ */
+
+static unsigned long vgic_mmio_read_v3_misc(struct vcpu *vcpu, paddr_t addr,
+ unsigned int len)
+{
+ struct vgic_dist *vgic = &vcpu->domain->arch.vgic;
+ uint32_t value = 0;
+
+ switch ( addr & 0x0c )
+ {
+ case GICD_CTLR:
+ if ( vgic->enabled )
+ value |= GICD_CTLR_ENABLE_G1A;
+ value |= GICD_CTLR_ARE_NS | GICD_CTLR_DS;
+ break;
+ case GICD_TYPER:
+ value = vgic->nr_spis + VGIC_NR_PRIVATE_IRQS;
+ value = (value >> 5) - 1;
+ value |= (INTERRUPT_ID_BITS_SPIS - 1) << 19;
+ break;
+ case GICD_TYPER2:
+ break;
+ case GICD_IIDR:
+ value = (PRODUCT_ID_KVM << 24) | (VARIANT_ID_XEN << 16) |
+ (IMPLEMENTER_ARM << 0);
+ break;
+ default:
+ return 0;
+ }
+
+ return value;
+}
+
+static void vgic_mmio_write_v3_misc(struct vcpu *vcpu, paddr_t addr,
+ unsigned int len, unsigned long val)
+{
+ struct vgic_dist *dist = &vcpu->domain->arch.vgic;
+
+ switch ( addr & 0x0c )
+ {
+ case GICD_CTLR:
+ {
+ bool was_enabled;
+
+ domain_lock(vcpu->domain);
+
+ was_enabled = dist->enabled;
+
+ dist->enabled = val & GICD_CTLR_ENABLE_G1A;
+
+ if ( dist->enabled )
+ vgic_kick_vcpus(vcpu->domain);
+
+ domain_unlock(vcpu->domain);
+ break;
+ }
+ case GICD_TYPER:
+ case GICD_TYPER2:
+ case GICD_IIDR:
+ /* This is at best for documentation purposes... */
+ return;
+ }
+}
+
static const struct vgic_register_region vgic_v3_dist_registers[] = {
REGISTER_DESC_WITH_LENGTH(GICD_CTLR,
- vgic_mmio_read_raz, vgic_mmio_write_wi,
+ vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc,
16, VGIC_ACCESS_32bit),
REGISTER_DESC_WITH_LENGTH(GICD_STATUSR,
vgic_mmio_read_rao, vgic_mmio_write_wi, 4,
diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h
index a8e3ef5970..b3bba7b5f3 100644
--- a/xen/arch/arm/vgic/vgic.h
+++ b/xen/arch/arm/vgic/vgic.h
@@ -28,6 +28,7 @@
#define VGIC_ADDR_UNDEF INVALID_PADDR
#define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF)
+#define INTERRUPT_ID_BITS_SPIS 10
#define VGIC_PRI_BITS 5
#define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS)
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [XEN PATCH v2 08/25] arm: new VGIC: Add GICv3 SGI system register trap handler
2023-11-10 12:56 [XEN PATCH v2 00/25] arm: Add GICv3 support to the New VGIC Mykyta Poturai
` (4 preceding siblings ...)
2023-11-10 12:56 ` [XEN PATCH v2 04/25] arm: new VGIC: Add GICv3 CTLR, IIDR, TYPER handlers Mykyta Poturai
@ 2023-11-10 12:56 ` Mykyta Poturai
2023-11-10 12:56 ` [XEN PATCH v2 07/25] arm: new VGIC: Add GICv3 IROUTER register handlers Mykyta Poturai
` (18 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Mykyta Poturai @ 2023-11-10 12:56 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org
Cc: Mykyta Poturai, Stefano Stabellini, Julien Grall,
Bertrand Marquis, Volodymyr Babchuk, Michal Orzel
In contrast to GICv2 SGIs in a GICv3 implementation are not triggered
by a MMIO write, but with a system register write. Xen knows about
that register already, we just need to implement the handler and wire
it up to the core Xen/ARM code.
Base on Linux commit 621ecd8d2123bc13 by Andre Przywara
Signed-off-by: Mykyta Poturai <mykyta_poturai@epam.com>
---
xen/arch/arm/include/asm/gic_v3_defs.h | 2 +-
xen/arch/arm/vgic/vgic-mmio-v3.c | 147 +++++++++++++++++++++++++
xen/arch/arm/vgic/vgic.c | 10 +-
xen/arch/arm/vgic/vgic.h | 5 +
4 files changed, 160 insertions(+), 4 deletions(-)
diff --git a/xen/arch/arm/include/asm/gic_v3_defs.h b/xen/arch/arm/include/asm/gic_v3_defs.h
index e0d536e887..1e81687818 100644
--- a/xen/arch/arm/include/asm/gic_v3_defs.h
+++ b/xen/arch/arm/include/asm/gic_v3_defs.h
@@ -204,7 +204,7 @@
#define ICH_SGI_IRQ_SHIFT 24
#define ICH_SGI_IRQ_MASK 0xf
#define ICH_SGI_TARGETLIST_MASK 0xffff
-#define ICH_SGI_AFFx_MASK 0xff
+#define ICH_SGI_AFFx_MASK 0xffULL
#define ICH_SGI_AFFINITY_LEVEL(x) (16 * (x))
struct rdist_region {
diff --git a/xen/arch/arm/vgic/vgic-mmio-v3.c b/xen/arch/arm/vgic/vgic-mmio-v3.c
index 3d892a68cb..19ebf723ee 100644
--- a/xen/arch/arm/vgic/vgic-mmio-v3.c
+++ b/xen/arch/arm/vgic/vgic-mmio-v3.c
@@ -42,6 +42,153 @@ unsigned long extract_bytes(uint64_t data, unsigned int offset,
return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0);
}
+static int match_mpidr(u64 sgi_aff, u16 sgi_cpu_mask, struct vcpu *vcpu)
+{
+ unsigned long affinity;
+ int level0;
+
+ /*
+ * Split the current VCPU's MPIDR into affinity level 0 and the
+ * rest as this is what we have to compare against.
+ */
+ affinity = vcpuid_to_vaffinity(vcpu->vcpu_id);
+ level0 = MPIDR_AFFINITY_LEVEL(affinity, 0);
+ affinity &= ~MPIDR_LEVEL_MASK;
+
+ /* bail out if the upper three levels don't match */
+ if ( sgi_aff != affinity )
+ return -1;
+
+ /* Is this VCPU's bit set in the mask ? */
+ if ( !(sgi_cpu_mask & BIT(level0, ULL)) )
+ return -1;
+
+ return level0;
+}
+
+#define SGI_AFFINITY_LEVEL(reg, level) \
+ ((((reg) & (ICH_SGI_AFFx_MASK << ICH_SGI_AFFINITY_LEVEL(level))) >> \
+ ICH_SGI_AFFINITY_LEVEL(level)) \
+ << MPIDR_LEVEL_SHIFT(level))
+
+static bool vgic_v3_emulate_sgi1r(struct cpu_user_regs *regs, uint64_t *r,
+ bool read)
+{
+ struct domain *d = current->domain;
+ struct vcpu *vcpu = current;
+ struct vcpu *c_vcpu;
+ u16 target_cpus;
+ u64 mpidr;
+ int sgi;
+ int vcpu_id = vcpu->vcpu_id;
+ bool broadcast;
+ unsigned long flags;
+
+ if ( read )
+ {
+ gdprintk(XENLOG_WARNING, "Reading SGI1R_EL1 - WO register\n");
+ return false;
+ }
+
+ sgi = (*r >> ICH_SGI_IRQ_SHIFT) & ICH_SGI_IRQ_MASK;
+ broadcast = *r & BIT(ICH_SGI_IRQMODE_SHIFT, ULL);
+ target_cpus = (*r & ICH_SGI_TARGETLIST_MASK);
+
+ mpidr = SGI_AFFINITY_LEVEL(*r, 3);
+ mpidr |= SGI_AFFINITY_LEVEL(*r, 2);
+ mpidr |= SGI_AFFINITY_LEVEL(*r, 1);
+
+ /*
+ * We iterate over all VCPUs to find the MPIDRs matching the request.
+ * If we have handled one CPU, we clear its bit to detect early
+ * if we are already finished. This avoids iterating through all
+ * VCPUs when most of the times we just signal a single VCPU.
+ */
+ for_each_vcpu(d, c_vcpu)
+ {
+ struct vgic_irq *irq;
+
+ /* Exit early if we have dealt with all requested CPUs */
+ if ( !broadcast && target_cpus == 0 )
+ break;
+
+ /* Don't signal the calling VCPU */
+ if ( broadcast && c_vcpu->vcpu_id == vcpu_id )
+ continue;
+
+ if ( !broadcast )
+ {
+ int level0;
+
+ level0 = match_mpidr(mpidr, target_cpus, c_vcpu);
+ if ( level0 == -1 )
+ continue;
+
+ /* remove this matching VCPU from the mask */
+ target_cpus &= ~BIT(level0, UL);
+ }
+
+ irq = vgic_get_irq(vcpu->domain, c_vcpu, sgi);
+
+ spin_lock_irqsave(&irq->irq_lock, flags);
+
+ if ( !irq->hw )
+ {
+ irq->pending_latch = true;
+ vgic_queue_irq_unlock(vcpu->domain, irq, flags);
+ }
+ else
+ {
+ printk(XENLOG_ERR "HW SGIs are not implemented\n");
+ BUG();
+ spin_unlock_irqrestore(&irq->irq_lock, flags);
+ }
+
+ vgic_put_irq(vcpu->domain, irq);
+ }
+
+ return true;
+}
+
+static bool vgic_v3_emulate_sysreg(struct cpu_user_regs *regs, union hsr hsr)
+{
+ struct hsr_sysreg sysreg = hsr.sysreg;
+
+ ASSERT(hsr.ec == HSR_EC_SYSREG);
+
+ if ( sysreg.read )
+ perfc_incr(vgic_sysreg_reads);
+ else
+ perfc_incr(vgic_sysreg_writes);
+
+ switch ( hsr.bits & HSR_SYSREG_REGS_MASK )
+ {
+ case HSR_SYSREG_ICC_SGI1R_EL1:
+ return vreg_emulate_sysreg(regs, hsr, vgic_v3_emulate_sgi1r);
+
+ default:
+ return false;
+ }
+}
+
+bool vgic_v3_emulate_reg(struct cpu_user_regs *regs, union hsr hsr)
+{
+ switch ( hsr.ec )
+ {
+#ifdef CONFIG_ARM_64
+ case HSR_EC_SYSREG:
+ return vgic_v3_emulate_sysreg(regs, hsr);
+#endif
+ case HSR_EC_CP15_64:
+ printk(XENLOG_ERR
+ "vgic_v3_emulate_reg: HSR_EC_CP15_64 not implemented");
+ BUG();
+ break;
+ default:
+ return false;
+ }
+}
+
/*
* The Revision field in the IIDR have the following meanings:
*
diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c
index 97ca827fc4..946877bbac 100644
--- a/xen/arch/arm/vgic/vgic.c
+++ b/xen/arch/arm/vgic/vgic.c
@@ -865,9 +865,13 @@ struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu *v,
bool vgic_emulate(struct cpu_user_regs *regs, union hsr hsr)
{
- ASSERT(current->domain->arch.vgic.version == GIC_V3);
-
- return false;
+ switch ( current->domain->arch.vgic.version )
+ {
+ case GIC_V3:
+ return vgic_v3_emulate_reg(regs, hsr);
+ default:
+ return false;
+ }
}
/*
diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h
index b3bba7b5f3..0e0cf7b213 100644
--- a/xen/arch/arm/vgic/vgic.h
+++ b/xen/arch/arm/vgic/vgic.h
@@ -74,6 +74,7 @@ int vgic_register_dist_iodev(struct domain *d, gfn_t dist_base_fn,
#ifdef CONFIG_GICV3
void vgic_v3_fold_lr_state(struct vcpu *vcpu);
void vgic_v3_populate_lr(struct vcpu *vcpu, struct vgic_irq *irq, int lr);
+bool vgic_v3_emulate_reg(struct cpu_user_regs *regs, union hsr hsr);
unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev);
int vgic_v3_set_redist_base(struct domain *d, u32 index, u64 addr, u32 count);
int vgic_register_redist_iodev(struct vcpu *vcpu);
@@ -88,6 +89,10 @@ static inline unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev)
{
return 0;
}
+static inline bool vgic_v3_emulate_reg(struct cpu_user_regs *regs, union hsr hsr)
+{
+ return false;
+}
static inline int vgic_v3_set_redist_base(struct domain *d, u32 index, u64 addr, u32 count)
{
return 0;
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [XEN PATCH v2 07/25] arm: new VGIC: Add GICv3 IROUTER register handlers
2023-11-10 12:56 [XEN PATCH v2 00/25] arm: Add GICv3 support to the New VGIC Mykyta Poturai
` (5 preceding siblings ...)
2023-11-10 12:56 ` [XEN PATCH v2 08/25] arm: new VGIC: Add GICv3 SGI system register trap handler Mykyta Poturai
@ 2023-11-10 12:56 ` Mykyta Poturai
2023-11-10 12:56 ` [XEN PATCH v2 06/25] arm: new VGIC: Add GICv3 IDREGS register handler Mykyta Poturai
` (17 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Mykyta Poturai @ 2023-11-10 12:56 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org
Cc: Mykyta Poturai, Stefano Stabellini, Julien Grall,
Bertrand Marquis, Volodymyr Babchuk, Michal Orzel
Since GICv3 supports much more than the 8 CPUs the GICv2 ITARGETSR
register can handle, the new IROUTER register covers the whole range
of possible target (V)CPUs by using the same MPIDR that the cores
report themselves.
In addition to translating this MPIDR into a vcpu pointer we store
the originally written value as well. The architecture allows to
write any values into the register, which must be read back as written.
Since we don't support affinity level 3, we don't need to take care
about the upper word of this 64-bit register, which simplifies the
handling a bit.
Based on Linux commit 78a714aba03039 by Andre Przywara
Signed-off-by: Mykyta Poturai <mykyta_poturai@epam.com>
---
xen/arch/arm/vgic/vgic-mmio-v3.c | 59 +++++++++++++++++++++++++++++++-
1 file changed, 58 insertions(+), 1 deletion(-)
diff --git a/xen/arch/arm/vgic/vgic-mmio-v3.c b/xen/arch/arm/vgic/vgic-mmio-v3.c
index ccdf3b9456..3d892a68cb 100644
--- a/xen/arch/arm/vgic/vgic-mmio-v3.c
+++ b/xen/arch/arm/vgic/vgic-mmio-v3.c
@@ -22,6 +22,19 @@
#include "vgic.h"
#include "vgic-mmio.h"
+static struct vcpu *mpidr_to_vcpu(struct domain *d, unsigned long mpidr)
+{
+ struct vcpu *vcpu;
+
+ mpidr &= MPIDR_HWID_MASK;
+ for_each_vcpu(d, vcpu)
+ {
+ if ( mpidr == vcpuid_to_vaffinity(vcpu->vcpu_id) )
+ return vcpu;
+ }
+ return NULL;
+}
+
/* extract @num bytes at @offset bytes offset in data */
unsigned long extract_bytes(uint64_t data, unsigned int offset,
unsigned int num)
@@ -98,6 +111,50 @@ static void vgic_mmio_write_v3_misc(struct vcpu *vcpu, paddr_t addr,
}
}
+static unsigned long vgic_mmio_read_irouter(struct vcpu *vcpu, paddr_t addr,
+ unsigned int len)
+{
+ int intid = VGIC_ADDR_TO_INTID(addr, 64);
+ struct vgic_irq *irq = vgic_get_irq(vcpu->domain, NULL, intid);
+ unsigned long ret = 0;
+
+ if ( !irq )
+ return 0;
+
+ /* The upper word is RAZ for us. */
+ if ( !(addr & 4) )
+ ret = extract_bytes(irq->mpidr, addr & 7, len);
+
+ vgic_put_irq(vcpu->domain, irq);
+ return ret;
+}
+
+static void vgic_mmio_write_irouter(struct vcpu *vcpu, paddr_t addr,
+ unsigned int len, unsigned long val)
+{
+ int intid = VGIC_ADDR_TO_INTID(addr, 64);
+ struct vgic_irq *irq;
+ unsigned long flags;
+
+ /* The upper word is WI for us since we don't implement Aff3. */
+ if ( addr & 4 )
+ return;
+
+ irq = vgic_get_irq(vcpu->domain, NULL, intid);
+
+ if ( !irq )
+ return;
+
+ spin_lock_irqsave(&irq->irq_lock, flags);
+
+ /* We only care about and preserve Aff0, Aff1 and Aff2. */
+ irq->mpidr = val & GENMASK(23, 0);
+ irq->target_vcpu = mpidr_to_vcpu(vcpu->domain, irq->mpidr);
+
+ spin_unlock_irqrestore(&irq->irq_lock, flags);
+ vgic_put_irq(vcpu->domain, irq);
+}
+
static bool vgic_mmio_vcpu_rdist_is_last(struct vcpu *vcpu)
{
struct vgic_dist *vgic = &vcpu->domain->arch.vgic;
@@ -206,7 +263,7 @@ static const struct vgic_register_region vgic_v3_dist_registers[] = {
vgic_mmio_read_raz, vgic_mmio_write_wi, 1,
VGIC_ACCESS_32bit),
REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_IROUTER,
- vgic_mmio_read_raz, vgic_mmio_write_wi, 64,
+ vgic_mmio_read_irouter, vgic_mmio_write_irouter, 64,
VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
REGISTER_DESC_WITH_LENGTH(GICD_IDREGS,
vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [XEN PATCH v2 06/25] arm: new VGIC: Add GICv3 IDREGS register handler
2023-11-10 12:56 [XEN PATCH v2 00/25] arm: Add GICv3 support to the New VGIC Mykyta Poturai
` (6 preceding siblings ...)
2023-11-10 12:56 ` [XEN PATCH v2 07/25] arm: new VGIC: Add GICv3 IROUTER register handlers Mykyta Poturai
@ 2023-11-10 12:56 ` Mykyta Poturai
2023-11-10 12:56 ` [XEN PATCH v2 09/25] arm: new VGIC: vgic_init: implement map_resources Mykyta Poturai
` (16 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Mykyta Poturai @ 2023-11-10 12:56 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org
Cc: Mykyta Poturai, Stefano Stabellini, Julien Grall,
Bertrand Marquis, Volodymyr Babchuk, Michal Orzel
We implement the only one ID register that is required by the
architecture, also this is the one that Linux actually checks.
Based on Linux commit 54f59d2b3a0a3d by Andre Przywara
Signed-off-by: Mykyta Poturai <mykyta_poturai@epam.com>
---
xen/arch/arm/vgic/vgic-mmio-v3.c | 17 +++++++++++++++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/xen/arch/arm/vgic/vgic-mmio-v3.c b/xen/arch/arm/vgic/vgic-mmio-v3.c
index 707a38c727..ccdf3b9456 100644
--- a/xen/arch/arm/vgic/vgic-mmio-v3.c
+++ b/xen/arch/arm/vgic/vgic-mmio-v3.c
@@ -152,6 +152,19 @@ static unsigned long vgic_mmio_read_v3r_iidr(struct vcpu *vcpu, paddr_t addr,
(IMPLEMENTER_ARM << 0);
}
+static unsigned long vgic_mmio_read_v3_idregs(struct vcpu *vcpu, paddr_t addr,
+ unsigned int len)
+{
+ switch ( addr & 0xfff )
+ {
+ case GICD_ICPIDR2:
+ /* report a GICv3 compliant implementation */
+ return 0x3b;
+ }
+
+ return 0;
+}
+
static const struct vgic_register_region vgic_v3_dist_registers[] = {
REGISTER_DESC_WITH_LENGTH(GICD_CTLR,
vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc,
@@ -196,7 +209,7 @@ static const struct vgic_register_region vgic_v3_dist_registers[] = {
vgic_mmio_read_raz, vgic_mmio_write_wi, 64,
VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
REGISTER_DESC_WITH_LENGTH(GICD_IDREGS,
- vgic_mmio_read_raz, vgic_mmio_write_wi, 48,
+ vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
VGIC_ACCESS_32bit),
};
@@ -233,7 +246,7 @@ static const struct vgic_register_region vgic_v3_rd_registers[] = {
vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
VGIC_ACCESS_32bit),
REGISTER_DESC_WITH_LENGTH(GICR_IDREGS,
- vgic_mmio_read_raz, vgic_mmio_write_wi, 48,
+ vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
VGIC_ACCESS_32bit),
/* SGI_base registers */
REGISTER_DESC_WITH_LENGTH(SZ_64K + GICR_IGROUPR0,
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [XEN PATCH v2 09/25] arm: new VGIC: vgic_init: implement map_resources
2023-11-10 12:56 [XEN PATCH v2 00/25] arm: Add GICv3 support to the New VGIC Mykyta Poturai
` (7 preceding siblings ...)
2023-11-10 12:56 ` [XEN PATCH v2 06/25] arm: new VGIC: Add GICv3 IDREGS register handler Mykyta Poturai
@ 2023-11-10 12:56 ` Mykyta Poturai
2023-11-10 12:56 ` [XEN PATCH v2 10/25] arm: new VGIC: Add vgic_v3_enable Mykyta Poturai
` (15 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Mykyta Poturai @ 2023-11-10 12:56 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org
Cc: Mykyta Poturai, Stefano Stabellini, Julien Grall,
Bertrand Marquis, Volodymyr Babchuk, Michal Orzel
map_resources is the last initialization step needed before the first
VCPU is run. At that stage the code stores the MMIO base addresses used.
Also it registers the respective register frames with the MMIO framework.
This is based on Linux commit b0442ee227e826af by Eric Auger
Signed-off-by: Mykyta Poturai <mykyta_poturai@epam.com>
---
xen/arch/arm/vgic/vgic-init.c | 2 +-
xen/arch/arm/vgic/vgic-v3.c | 85 +++++++++++++++++++++++++++++++++++
xen/arch/arm/vgic/vgic.c | 13 +-----
xen/arch/arm/vgic/vgic.h | 5 +++
4 files changed, 93 insertions(+), 12 deletions(-)
diff --git a/xen/arch/arm/vgic/vgic-init.c b/xen/arch/arm/vgic/vgic-init.c
index c3b34be192..ca13cf385c 100644
--- a/xen/arch/arm/vgic/vgic-init.c
+++ b/xen/arch/arm/vgic/vgic-init.c
@@ -178,7 +178,7 @@ int domain_vgic_init(struct domain *d, unsigned int nr_spis)
if ( dist->version == GIC_V2 )
ret = vgic_v2_map_resources(d);
else
- ret = -ENXIO;
+ ret = vgic_v3_map_resources(d);
if ( ret )
return ret;
diff --git a/xen/arch/arm/vgic/vgic-v3.c b/xen/arch/arm/vgic/vgic-v3.c
index b018ee6040..470bb63147 100644
--- a/xen/arch/arm/vgic/vgic-v3.c
+++ b/xen/arch/arm/vgic/vgic-v3.c
@@ -14,11 +14,33 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <asm/new_vgic.h>
+#include <asm/gic_v3_defs.h>
#include <asm/gic.h>
#include <xen/sched.h>
#include "vgic.h"
+static struct {
+ bool enabled;
+ /* Distributor interface address */
+ paddr_t dbase;
+ /* Re-distributor regions */
+ unsigned int nr_rdist_regions;
+ const struct rdist_region *regions;
+ unsigned int intid_bits; /* Number of interrupt ID bits */
+} vgic_v3_hw_data;
+
+void vgic_v3_setup_hw(paddr_t dbase, unsigned int nr_rdist_regions,
+ const struct rdist_region *regions,
+ unsigned int intid_bits)
+{
+ vgic_v3_hw_data.enabled = true;
+ vgic_v3_hw_data.dbase = dbase;
+ vgic_v3_hw_data.nr_rdist_regions = nr_rdist_regions;
+ vgic_v3_hw_data.regions = regions;
+ vgic_v3_hw_data.intid_bits = intid_bits;
+}
+
/*
* transfer the content of the LRs back into the corresponding ap_list:
* - active bit is transferred as is
@@ -204,3 +226,66 @@ void vgic_v3_populate_lr(struct vcpu *vcpu, struct vgic_irq *irq, int lr)
gic_hw_ops->write_lr(lr, &lr_val);
}
+
+unsigned int vgic_v3_max_rdist_count(const struct domain *d)
+{
+ /*
+ * Normally there is only one GICv3 redistributor region.
+ * The GICv3 DT binding provisions for multiple regions, since there are
+ * platforms out there which need those (multi-socket systems).
+ * For domain using the host memory layout, we have to live with the MMIO
+ * layout the hardware provides, so we have to copy the multiple regions
+ * - as the first region may not provide enough space to hold all
+ * redistributors we need.
+ * All the other domains will get a constructed memory map, so we can go
+ * with the architected single redistributor region.
+ */
+ return domain_use_host_layout(d) ? vgic_v3_hw_data.nr_rdist_regions
+ : GUEST_GICV3_RDIST_REGIONS;
+}
+
+int vgic_v3_map_resources(struct domain *d)
+{
+ int rdist_count, i, ret;
+
+ /* Allocate memory for Re-distributor regions */
+ rdist_count = vgic_v3_max_rdist_count(d);
+
+ /*
+ * For domain using the host memory layout, it gets the hardware
+ * address.
+ * Other domains get the virtual platform layout.
+ */
+ if ( domain_use_host_layout(d) )
+ {
+ d->arch.vgic.dbase = vgic_v3_hw_data.dbase;
+
+ for ( i = 0; i < vgic_v3_hw_data.nr_rdist_regions; i++ )
+ {
+ vgic_v3_set_redist_base(d, i, vgic_v3_hw_data.regions[i].base,
+ vgic_v3_hw_data.regions[i].size /
+ GICV3_GICR_SIZE);
+ }
+ }
+ else
+ {
+ d->arch.vgic.dbase = GUEST_GICV3_GICD_BASE;
+
+ /* A single Re-distributor region is mapped for the guest. */
+ BUILD_BUG_ON(GUEST_GICV3_RDIST_REGIONS != 1);
+
+ /* The first redistributor should contain enough space for all CPUs */
+ BUILD_BUG_ON((GUEST_GICV3_GICR0_SIZE / GICV3_GICR_SIZE) <
+ MAX_VIRT_CPUS);
+ vgic_v3_set_redist_base(d, 0, GUEST_GICV3_GICR0_BASE,
+ GUEST_GICV3_GICR0_SIZE / GICV3_GICR_SIZE);
+ }
+
+ /* Register mmio handle for the Distributor */
+ ret =
+ vgic_register_dist_iodev(d, gaddr_to_gfn(d->arch.vgic.dbase), VGIC_V3);
+
+ d->arch.vgic.ready = true;
+
+ return 0;
+}
diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c
index 946877bbac..2f9644dc18 100644
--- a/xen/arch/arm/vgic/vgic.c
+++ b/xen/arch/arm/vgic/vgic.c
@@ -968,23 +968,14 @@ unsigned int vgic_max_vcpus(unsigned int domctl_vgic_version)
{
case XEN_DOMCTL_CONFIG_GIC_V2:
return VGIC_V2_MAX_CPUS;
+ case XEN_DOMCTL_CONFIG_GIC_V3:
+ return VGIC_V3_MAX_CPUS;
default:
return 0;
}
}
-#ifdef CONFIG_GICV3
-/* Dummy implementation to allow building without actual vGICv3 support. */
-void vgic_v3_setup_hw(paddr_t dbase,
- unsigned int nr_rdist_regions,
- const struct rdist_region *regions,
- unsigned int intid_bits)
-{
- panic("New VGIC implementation does not yet support GICv3\n");
-}
-#endif
-
/*
* Local variables:
* mode: C
diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h
index 0e0cf7b213..7dbadf7501 100644
--- a/xen/arch/arm/vgic/vgic.h
+++ b/xen/arch/arm/vgic/vgic.h
@@ -74,6 +74,7 @@ int vgic_register_dist_iodev(struct domain *d, gfn_t dist_base_fn,
#ifdef CONFIG_GICV3
void vgic_v3_fold_lr_state(struct vcpu *vcpu);
void vgic_v3_populate_lr(struct vcpu *vcpu, struct vgic_irq *irq, int lr);
+int vgic_v3_map_resources(struct domain *d);
bool vgic_v3_emulate_reg(struct cpu_user_regs *regs, union hsr hsr);
unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev);
int vgic_v3_set_redist_base(struct domain *d, u32 index, u64 addr, u32 count);
@@ -85,6 +86,10 @@ static inline void vgic_v3_fold_lr_state(struct vcpu *vcpu)
static inline void vgic_v3_populate_lr(struct vcpu *vcpu, struct vgic_irq *irq, int lr)
{
}
+static inline int vgic_v3_map_resources(struct domain *d)
+{
+ return 0;
+}
static inline unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev)
{
return 0;
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [XEN PATCH v2 10/25] arm: new VGIC: Add vgic_v3_enable
2023-11-10 12:56 [XEN PATCH v2 00/25] arm: Add GICv3 support to the New VGIC Mykyta Poturai
` (8 preceding siblings ...)
2023-11-10 12:56 ` [XEN PATCH v2 09/25] arm: new VGIC: vgic_init: implement map_resources Mykyta Poturai
@ 2023-11-10 12:56 ` Mykyta Poturai
2023-11-10 12:56 ` [XEN PATCH v2 11/25] arm: new VGIC: Add alternative redist region storage Mykyta Poturai
` (14 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Mykyta Poturai @ 2023-11-10 12:56 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org
Cc: Mykyta Poturai, Stefano Stabellini, Julien Grall,
Bertrand Marquis, Volodymyr Babchuk, Michal Orzel
Enable the VGIC operation by properly initialising the registers
in the hypervisor GIC interface.
This is based on Linux commit f7b6985cc3d0f by Eric Auger
Signed-off-by: Mykyta Poturai <mykyta_poturai@epam.com>
---
xen/arch/arm/vgic/vgic-init.c | 5 +++++
xen/arch/arm/vgic/vgic-v3.c | 6 ++++++
xen/arch/arm/vgic/vgic.h | 4 ++++
3 files changed, 15 insertions(+)
diff --git a/xen/arch/arm/vgic/vgic-init.c b/xen/arch/arm/vgic/vgic-init.c
index ca13cf385c..96f6669d38 100644
--- a/xen/arch/arm/vgic/vgic-init.c
+++ b/xen/arch/arm/vgic/vgic-init.c
@@ -209,9 +209,14 @@ int vcpu_vgic_init(struct vcpu *v)
vgic_vcpu_early_init(v);
if ( gic_hw_version() == GIC_V2 )
+ {
vgic_v2_enable(v);
+ }
else
+ {
vgic_register_redist_iodev(v);
+ vgic_v3_enable(v);
+ }
return ret;
}
diff --git a/xen/arch/arm/vgic/vgic-v3.c b/xen/arch/arm/vgic/vgic-v3.c
index 470bb63147..682d57b476 100644
--- a/xen/arch/arm/vgic/vgic-v3.c
+++ b/xen/arch/arm/vgic/vgic-v3.c
@@ -244,6 +244,12 @@ unsigned int vgic_v3_max_rdist_count(const struct domain *d)
: GUEST_GICV3_RDIST_REGIONS;
}
+void vgic_v3_enable(struct vcpu *vcpu)
+{
+ /* Get the show on the road... */
+ gic_hw_ops->update_hcr_status(GICH_HCR_EN, true);
+}
+
int vgic_v3_map_resources(struct domain *d)
{
int rdist_count, i, ret;
diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h
index 7dbadf7501..791c91ebb3 100644
--- a/xen/arch/arm/vgic/vgic.h
+++ b/xen/arch/arm/vgic/vgic.h
@@ -74,6 +74,7 @@ int vgic_register_dist_iodev(struct domain *d, gfn_t dist_base_fn,
#ifdef CONFIG_GICV3
void vgic_v3_fold_lr_state(struct vcpu *vcpu);
void vgic_v3_populate_lr(struct vcpu *vcpu, struct vgic_irq *irq, int lr);
+void vgic_v3_enable(struct vcpu *vcpu);
int vgic_v3_map_resources(struct domain *d);
bool vgic_v3_emulate_reg(struct cpu_user_regs *regs, union hsr hsr);
unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev);
@@ -86,6 +87,9 @@ static inline void vgic_v3_fold_lr_state(struct vcpu *vcpu)
static inline void vgic_v3_populate_lr(struct vcpu *vcpu, struct vgic_irq *irq, int lr)
{
}
+static inline void vgic_v3_enable(struct vcpu *vcpu)
+{
+}
static inline int vgic_v3_map_resources(struct domain *d)
{
return 0;
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [XEN PATCH v2 11/25] arm: new VGIC: Add alternative redist region storage
2023-11-10 12:56 [XEN PATCH v2 00/25] arm: Add GICv3 support to the New VGIC Mykyta Poturai
` (9 preceding siblings ...)
2023-11-10 12:56 ` [XEN PATCH v2 10/25] arm: new VGIC: Add vgic_v3_enable Mykyta Poturai
@ 2023-11-10 12:56 ` Mykyta Poturai
2023-11-10 12:56 ` [XEN PATCH v2 14/25] arm: new VGIC: its: Introduce ITS emulation file with MMIO framework Mykyta Poturai
` (13 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Mykyta Poturai @ 2023-11-10 12:56 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org
Cc: Mykyta Poturai, Stefano Stabellini, Julien Grall,
Bertrand Marquis, Volodymyr Babchuk, Michal Orzel
Guests DT creation requires redist regions to be stored in the specific
variables in struct vgic_dist. But in new VGIC a linked list is used for
that. To not clutter the DT creation code with ifdefs, add alternative
storage for redist regions in struct vgic_dist.
Signed-off-by: Mykyta Poturai <mykyta_poturai@epam.com>
---
xen/arch/arm/include/asm/new_vgic.h | 5 +++++
xen/arch/arm/vgic/vgic-v3.c | 8 ++++++++
2 files changed, 13 insertions(+)
diff --git a/xen/arch/arm/include/asm/new_vgic.h b/xen/arch/arm/include/asm/new_vgic.h
index 11d8f71851..9eafab45ff 100644
--- a/xen/arch/arm/include/asm/new_vgic.h
+++ b/xen/arch/arm/include/asm/new_vgic.h
@@ -21,6 +21,7 @@
#include <xen/list.h>
#include <xen/mm.h>
#include <xen/spinlock.h>
+#include <asm/gic_v3_defs.h>
#define VGIC_V3_MAX_CPUS 255
#define VGIC_V2_MAX_CPUS 8
@@ -136,6 +137,10 @@ struct vgic_dist {
paddr_t csize; /* CPU interface size */
paddr_t vbase; /* virtual CPU interface base address */
+ /* for compatibility with guests DT creation*/
+ uint32_t nr_regions;
+ struct rdist_region *rdist_regions;
+
/* distributor enabled */
bool enabled;
diff --git a/xen/arch/arm/vgic/vgic-v3.c b/xen/arch/arm/vgic/vgic-v3.c
index 682d57b476..8b700609f0 100644
--- a/xen/arch/arm/vgic/vgic-v3.c
+++ b/xen/arch/arm/vgic/vgic-v3.c
@@ -257,6 +257,10 @@ int vgic_v3_map_resources(struct domain *d)
/* Allocate memory for Re-distributor regions */
rdist_count = vgic_v3_max_rdist_count(d);
+ /*For compatibility with hwdom dt node creation*/
+ d->arch.vgic.nr_regions = rdist_count;
+ d->arch.vgic.rdist_regions = xzalloc_array(struct rdist_region, rdist_count);
+
/*
* For domain using the host memory layout, it gets the hardware
* address.
@@ -268,6 +272,8 @@ int vgic_v3_map_resources(struct domain *d)
for ( i = 0; i < vgic_v3_hw_data.nr_rdist_regions; i++ )
{
+ d->arch.vgic.rdist_regions[i].base = vgic_v3_hw_data.regions[i].base;
+ d->arch.vgic.rdist_regions[i].size = vgic_v3_hw_data.regions[i].size;
vgic_v3_set_redist_base(d, i, vgic_v3_hw_data.regions[i].base,
vgic_v3_hw_data.regions[i].size /
GICV3_GICR_SIZE);
@@ -276,6 +282,8 @@ int vgic_v3_map_resources(struct domain *d)
else
{
d->arch.vgic.dbase = GUEST_GICV3_GICD_BASE;
+ d->arch.vgic.rdist_regions[0].base = GUEST_GICV3_GICR0_BASE;
+ d->arch.vgic.rdist_regions[0].size = GUEST_GICV3_GICR0_SIZE;
/* A single Re-distributor region is mapped for the guest. */
BUILD_BUG_ON(GUEST_GICV3_RDIST_REGIONS != 1);
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [XEN PATCH v2 14/25] arm: new VGIC: its: Introduce ITS emulation file with MMIO framework
2023-11-10 12:56 [XEN PATCH v2 00/25] arm: Add GICv3 support to the New VGIC Mykyta Poturai
` (10 preceding siblings ...)
2023-11-10 12:56 ` [XEN PATCH v2 11/25] arm: new VGIC: Add alternative redist region storage Mykyta Poturai
@ 2023-11-10 12:56 ` Mykyta Poturai
2023-11-10 12:56 ` [XEN PATCH v2 13/25] arm: new VGIC: Handle ITS related GICv3 redistributor registers Mykyta Poturai
` (12 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Mykyta Poturai @ 2023-11-10 12:56 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org
Cc: Mykyta Poturai, Stefano Stabellini, Julien Grall,
Bertrand Marquis, Volodymyr Babchuk, Michal Orzel
The ARM GICv3 ITS emulation code goes into a separate file, but needs
to be connected to the GICv3 emulation, of which it is an option.
The ITS MMIO handlers require the respective ITS pointer to be passed in,
so we amend the existing VGIC MMIO framework to let it cope with that.
Also we introduce the basic ITS data structure and initialize it, but
don't return any success yet, as we are not yet ready for the show.
Based on Linux commit 59c5ab40989afa by 59c5ab40989afa
Signed-off-by: Mykyta Poturai <mykyta_poturai@epam.com>
---
xen/arch/arm/include/asm/gic_v3_defs.h | 3 +
xen/arch/arm/include/asm/gic_v3_its.h | 1 +
xen/arch/arm/include/asm/new_vgic.h | 13 ++
xen/arch/arm/vgic/vgic-its.c | 160 +++++++++++++++++++++++++
xen/arch/arm/vgic/vgic-mmio-v3.c | 52 +++++++-
xen/arch/arm/vgic/vgic-mmio.c | 6 +
xen/arch/arm/vgic/vgic-mmio.h | 11 ++
7 files changed, 245 insertions(+), 1 deletion(-)
create mode 100644 xen/arch/arm/vgic/vgic-its.c
diff --git a/xen/arch/arm/include/asm/gic_v3_defs.h b/xen/arch/arm/include/asm/gic_v3_defs.h
index 1e81687818..3f1f59d1c7 100644
--- a/xen/arch/arm/include/asm/gic_v3_defs.h
+++ b/xen/arch/arm/include/asm/gic_v3_defs.h
@@ -112,6 +112,9 @@
#define GICR_NSACR (0x0E00)
#define GICR_CTLR_ENABLE_LPIS (1U << 0)
+#define GICR_CTLR_CES (1UL << 1)
+#define GICR_CTLR_IR (1UL << 2)
+#define GICR_CTLR_RWP (1UL << 3)
#define GICR_TYPER_PLPIS (1U << 0)
#define GICR_TYPER_VLPIS (1U << 1)
diff --git a/xen/arch/arm/include/asm/gic_v3_its.h b/xen/arch/arm/include/asm/gic_v3_its.h
index f61a37a8fa..4e857cac1a 100644
--- a/xen/arch/arm/include/asm/gic_v3_its.h
+++ b/xen/arch/arm/include/asm/gic_v3_its.h
@@ -35,6 +35,7 @@
#define GITS_BASER5 0x128
#define GITS_BASER6 0x130
#define GITS_BASER7 0x138
+#define GITS_IDREGS_BASE 0xffd0
#define GITS_PIDR2 GICR_PIDR2
/* Register bits */
diff --git a/xen/arch/arm/include/asm/new_vgic.h b/xen/arch/arm/include/asm/new_vgic.h
index b037b6cf61..ec2882dcf1 100644
--- a/xen/arch/arm/include/asm/new_vgic.h
+++ b/xen/arch/arm/include/asm/new_vgic.h
@@ -34,6 +34,7 @@
#define VGIC_MIN_LPI 8192
#define VGIC_V3_DIST_SIZE SZ_64K
#define VGIC_V3_REDIST_SIZE (2 * SZ_64K)
+#define VGIC_V3_ITS_SIZE (2 * SZ_64K)
#define irq_is_ppi(irq) ((irq) >= VGIC_NR_SGIS && (irq) < VGIC_NR_PRIVATE_IRQS)
#define irq_is_spi(irq) ((irq) >= VGIC_NR_PRIVATE_IRQS && \
@@ -95,6 +96,7 @@ struct vgic_irq {
enum iodev_type {
IODEV_DIST,
IODEV_REDIST,
+ IODEV_ITS,
};
struct vgic_redist_region {
@@ -111,6 +113,16 @@ struct vgic_io_device {
const struct vgic_register_region *regions;
enum iodev_type iodev_type;
unsigned int nr_regions;
+ struct vgic_its *its;
+};
+
+struct vgic_its {
+ /* The base address of the ITS control register frame */
+ paddr_t vgic_its_base;
+
+ bool enabled;
+ struct vgic_io_device iodev;
+ paddr_t doorbell_address;
};
struct vgic_dist {
@@ -150,6 +162,7 @@ struct vgic_dist {
struct vgic_io_device dist_iodev;
bool has_its;
+ struct vgic_its *its;
/*
* Contains the attributes and gpa of the LPI configuration table.
diff --git a/xen/arch/arm/vgic/vgic-its.c b/xen/arch/arm/vgic/vgic-its.c
new file mode 100644
index 0000000000..0ae6048456
--- /dev/null
+++ b/xen/arch/arm/vgic/vgic-its.c
@@ -0,0 +1,160 @@
+/*
+ * Imported from Linux ("new" KVM VGIC) and heavily adapted to Xen.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <xen/sched.h>
+#include <xen/guest_access.h>
+#include <xen/sizes.h>
+#include <xen/err.h>
+#include <xen/list_sort.h>
+#include <asm/page.h>
+#include <asm/new_vgic.h>
+#include <asm/gic_v3_defs.h>
+#include <asm/gic_v3_its.h>
+
+#include "vgic.h"
+#include "vgic-mmio.h"
+
+static unsigned long its_mmio_read_raz(struct domain *d, struct vgic_its *its,
+ paddr_t addr, unsigned int len)
+{
+ return 0;
+}
+
+static void its_mmio_write_wi(struct domain *d, struct vgic_its *its,
+ paddr_t addr, unsigned int len, unsigned long val)
+{
+ /* Ignore */
+}
+
+#define REGISTER_ITS_DESC(off, rd, wr, length, acc) \
+ { \
+ .reg_offset = off, .len = length, .access_flags = acc, .its_read = rd, \
+ .its_write = wr, \
+ }
+
+static struct vgic_register_region its_registers[] = {
+ REGISTER_ITS_DESC(GITS_CTLR,
+ its_mmio_read_raz, its_mmio_write_wi, 4,
+ VGIC_ACCESS_32bit),
+ REGISTER_ITS_DESC(GITS_IIDR,
+ its_mmio_read_raz, its_mmio_write_wi, 4,
+ VGIC_ACCESS_32bit),
+ REGISTER_ITS_DESC(GITS_TYPER,
+ its_mmio_read_raz, its_mmio_write_wi, 8,
+ VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
+ REGISTER_ITS_DESC(GITS_CBASER,
+ its_mmio_read_raz, its_mmio_write_wi, 8,
+ VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
+ REGISTER_ITS_DESC(GITS_CWRITER,
+ its_mmio_read_raz, its_mmio_write_wi, 8,
+ VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
+ REGISTER_ITS_DESC(GITS_CREADR,
+ its_mmio_read_raz, its_mmio_write_wi, 8,
+ VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
+ REGISTER_ITS_DESC(GITS_BASER0,
+ its_mmio_read_raz, its_mmio_write_wi, 0x40,
+ VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
+ REGISTER_ITS_DESC(GITS_IDREGS_BASE,
+ its_mmio_read_raz, its_mmio_write_wi, 0x30,
+ VGIC_ACCESS_32bit),
+};
+
+static int vgic_register_its_iodev(struct domain *d, struct vgic_its *its,
+ u64 addr)
+{
+ struct vgic_io_device *iodev = &its->iodev;
+ int ret = 0;
+
+ if ( !IS_VGIC_ADDR_UNDEF(its->vgic_its_base) )
+ {
+ ret = -EBUSY;
+ goto out;
+ }
+
+ its->vgic_its_base = addr;
+ its->doorbell_address = addr + ITS_DOORBELL_OFFSET;
+ iodev->regions = its_registers;
+ iodev->nr_regions = ARRAY_SIZE(its_registers);
+
+ iodev->base_fn = gaddr_to_gfn(its->vgic_its_base);
+ iodev->iodev_type = IODEV_ITS;
+ iodev->its = its;
+ register_mmio_handler(d, &vgic_io_ops, its->vgic_its_base, VGIC_V3_ITS_SIZE,
+ iodev);
+out:
+ return ret;
+}
+
+static int vgic_its_create(struct domain *d, u64 addr)
+{
+ struct vgic_its *its;
+
+ its = xzalloc(struct vgic_its);
+ if ( !its )
+ return -ENOMEM;
+
+ d->arch.vgic.its = its;
+
+ its->vgic_its_base = VGIC_ADDR_UNDEF;
+
+ d->arch.vgic.msis_require_devid = true;
+ d->arch.vgic.has_its = true;
+ its->enabled = false;
+
+ vgic_register_its_iodev(d, its, addr);
+
+ its->doorbell_address = addr + ITS_DOORBELL_OFFSET;
+
+ return 0;
+}
+
+/*
+ * For a hardware domain, this will iterate over the host ITSes
+ * and map one virtual ITS per host ITS at the same address.
+ */
+int vgic_v3_its_init_domain(struct domain *d)
+{
+ int ret;
+
+ if ( is_hardware_domain(d) )
+ {
+ struct host_its *hw_its;
+
+ list_for_each_entry(hw_its, &host_its_list, entry)
+ {
+ /*
+ * For each host ITS create a virtual ITS using the same
+ * base and thus doorbell address.
+ * Use the same number of device ID and event ID bits as the host.
+ */
+ ret = vgic_its_create(d, hw_its->addr);
+ if ( ret )
+ return ret;
+ else
+ d->arch.vgic.has_its = true;
+ }
+ }
+
+ return 0;
+}
+
+void vgic_v3_its_free_domain(struct domain *d)
+{
+ struct vgic_its *its = d->arch.vgic.its;
+
+ xfree(its);
+ d->arch.vgic.its = NULL;
+}
diff --git a/xen/arch/arm/vgic/vgic-mmio-v3.c b/xen/arch/arm/vgic/vgic-mmio-v3.c
index 2fb44cfe6a..4bf8c21203 100644
--- a/xen/arch/arm/vgic/vgic-mmio-v3.c
+++ b/xen/arch/arm/vgic/vgic-mmio-v3.c
@@ -22,6 +22,16 @@
#include "vgic.h"
#include "vgic-mmio.h"
+bool vgic_has_its(struct domain *d)
+{
+ struct vgic_dist *dist = &d->arch.vgic;
+
+ if ( dist->version != GIC_V3 )
+ return false;
+
+ return false;
+}
+
static struct vcpu *mpidr_to_vcpu(struct domain *d, unsigned long mpidr)
{
struct vcpu *vcpu;
@@ -381,6 +391,46 @@ static unsigned long vgic_mmio_read_v3_idregs(struct vcpu *vcpu, paddr_t addr,
return 0;
}
+static unsigned long vgic_mmio_read_v3r_ctlr(struct vcpu *vcpu, paddr_t addr,
+ unsigned int len)
+{
+ struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic;
+ unsigned long val;
+
+ val = atomic_read(&vgic_cpu->ctlr);
+ val |= GICR_CTLR_IR | GICR_CTLR_CES;
+
+ return val;
+}
+
+static void vgic_mmio_write_v3r_ctlr(struct vcpu *vcpu, paddr_t addr,
+ unsigned int len, unsigned long val)
+{
+ struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic;
+ uint32_t ctlr;
+
+ if ( !vgic_has_its(vcpu->domain) )
+ return;
+
+ if ( !(val & GICR_CTLR_ENABLE_LPIS) )
+ {
+ /*
+ * Don't disable if RWP is set, as there already an
+ * ongoing disable. Funky guest...
+ */
+ ctlr = atomic_cmpxchg(&vgic_cpu->ctlr, GICR_CTLR_ENABLE_LPIS,
+ GICR_CTLR_RWP);
+ if ( ctlr != GICR_CTLR_ENABLE_LPIS )
+ return;
+ }
+ else
+ {
+ ctlr = atomic_cmpxchg(&vgic_cpu->ctlr, 0, GICR_CTLR_ENABLE_LPIS);
+ if ( ctlr != 0 )
+ return;
+ }
+}
+
bool vgic_lpis_enabled(struct vcpu *vcpu)
{
struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic;
@@ -584,7 +634,7 @@ static const struct vgic_register_region vgic_v3_dist_registers[] = {
static const struct vgic_register_region vgic_v3_rd_registers[] = {
/* RD_base registers */
REGISTER_DESC_WITH_LENGTH(GICR_CTLR,
- vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
+ vgic_mmio_read_v3r_ctlr, vgic_mmio_write_v3r_ctlr, 4,
VGIC_ACCESS_32bit),
REGISTER_DESC_WITH_LENGTH(GICR_STATUSR,
vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
diff --git a/xen/arch/arm/vgic/vgic-mmio.c b/xen/arch/arm/vgic/vgic-mmio.c
index 1c3f861887..7a28be53bc 100644
--- a/xen/arch/arm/vgic/vgic-mmio.c
+++ b/xen/arch/arm/vgic/vgic-mmio.c
@@ -570,6 +570,9 @@ static int dispatch_mmio_read(struct vcpu *vcpu, mmio_info_t *info,
case IODEV_REDIST:
data = region->read(iodev->redist_vcpu, addr, len);
break;
+ case IODEV_ITS:
+ data = region->its_read(vcpu->domain, iodev->its, addr, len);;
+ break;
}
memcpy(r, &data, len);
@@ -598,6 +601,9 @@ static int dispatch_mmio_write(struct vcpu *vcpu, mmio_info_t *info,
case IODEV_REDIST:
region->write(iodev->redist_vcpu, addr, len, data);
break;
+ case IODEV_ITS:
+ region->its_write(vcpu->domain, iodev->its, addr, len, data);
+ break;
}
return 1;
diff --git a/xen/arch/arm/vgic/vgic-mmio.h b/xen/arch/arm/vgic/vgic-mmio.h
index 3566cf237c..0a8deb46ba 100644
--- a/xen/arch/arm/vgic/vgic-mmio.h
+++ b/xen/arch/arm/vgic/vgic-mmio.h
@@ -21,10 +21,21 @@ struct vgic_register_region {
unsigned int len;
unsigned int bits_per_irq;
unsigned int access_flags;
+
+ union {
unsigned long (*read)(struct vcpu *vcpu, paddr_t addr,
unsigned int len);
+ unsigned long (*its_read)(struct domain *d, struct vgic_its *its,
+ paddr_t addr, unsigned int len);
+ };
+
+ union {
void (*write)(struct vcpu *vcpu, paddr_t addr,
unsigned int len, unsigned long val);
+ void (*its_write)(struct domain *d, struct vgic_its *its,
+ paddr_t addr, unsigned int len,
+ unsigned long val);
+ };
};
extern struct mmio_handler_ops vgic_io_ops;
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [XEN PATCH v2 13/25] arm: new VGIC: Handle ITS related GICv3 redistributor registers
2023-11-10 12:56 [XEN PATCH v2 00/25] arm: Add GICv3 support to the New VGIC Mykyta Poturai
` (11 preceding siblings ...)
2023-11-10 12:56 ` [XEN PATCH v2 14/25] arm: new VGIC: its: Introduce ITS emulation file with MMIO framework Mykyta Poturai
@ 2023-11-10 12:56 ` Mykyta Poturai
2023-11-10 12:56 ` [XEN PATCH v2 12/25] arm: new VGIC: Wire new GICv3 into the build system Mykyta Poturai
` (11 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Mykyta Poturai @ 2023-11-10 12:56 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org
Cc: Mykyta Poturai, Stefano Stabellini, Julien Grall,
Bertrand Marquis, Volodymyr Babchuk, Michal Orzel
In the GICv3 redistributor there are the PENDBASER and PROPBASER
registers which we did not emulate so far, as they only make sense
when having an ITS. In preparation for that emulate those MMIO
accesses by storing the 64-bit data written into it into a variable
which we later read in the ITS emulation.
We also sanitise the registers, making sure RES0 regions are respected
and checking for valid memory attributes.
Based on Linux commit 0aa1de57319c4 by Andre Przywara
Signed-off-by: Mykyta Poturai <mykyta_poturai@epam.com>
---
xen/arch/arm/include/asm/new_vgic.h | 3 +
xen/arch/arm/vgic/vgic-mmio-v3.c | 168 +++++++++++++++++++++++++++-
2 files changed, 169 insertions(+), 2 deletions(-)
diff --git a/xen/arch/arm/include/asm/new_vgic.h b/xen/arch/arm/include/asm/new_vgic.h
index 9eafab45ff..b037b6cf61 100644
--- a/xen/arch/arm/include/asm/new_vgic.h
+++ b/xen/arch/arm/include/asm/new_vgic.h
@@ -199,6 +199,9 @@ struct vgic_cpu {
/* Cache guest interrupt ID bits */
uint32_t num_id_bits;
+
+ /* GICR_CTLR.{ENABLE_LPIS,RWP} */
+ atomic_t ctlr;
};
static inline paddr_t vgic_cpu_base(const struct vgic_dist *vgic)
diff --git a/xen/arch/arm/vgic/vgic-mmio-v3.c b/xen/arch/arm/vgic/vgic-mmio-v3.c
index 19ebf723ee..2fb44cfe6a 100644
--- a/xen/arch/arm/vgic/vgic-mmio-v3.c
+++ b/xen/arch/arm/vgic/vgic-mmio-v3.c
@@ -42,6 +42,18 @@ unsigned long extract_bytes(uint64_t data, unsigned int offset,
return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0);
}
+uint64_t update_64bit_reg(u64 reg, unsigned int offset, unsigned int len,
+ unsigned long val)
+{
+ int lower = (offset & 4) * 8;
+ int upper = lower + 8 * len - 1;
+
+ reg &= ~GENMASK_ULL(upper, lower);
+ val &= GENMASK_ULL(len * 8 - 1, 0);
+
+ return reg | ((u64)val << lower);
+}
+
static int match_mpidr(u64 sgi_aff, u16 sgi_cpu_mask, struct vcpu *vcpu)
{
unsigned long affinity;
@@ -369,6 +381,158 @@ static unsigned long vgic_mmio_read_v3_idregs(struct vcpu *vcpu, paddr_t addr,
return 0;
}
+bool vgic_lpis_enabled(struct vcpu *vcpu)
+{
+ struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic;
+
+ return atomic_read(&vgic_cpu->ctlr) == GICR_CTLR_ENABLE_LPIS;
+}
+
+/* We want to avoid outer shareable. */
+u64 vgic_sanitise_shareability(u64 field)
+{
+ switch ( field )
+ {
+ case GIC_BASER_OuterShareable:
+ return GIC_BASER_InnerShareable;
+ default:
+ return field;
+ }
+}
+
+/* Avoid any inner non-cacheable mapping. */
+u64 vgic_sanitise_inner_cacheability(u64 field)
+{
+ switch ( field )
+ {
+ case GIC_BASER_CACHE_nCnB:
+ case GIC_BASER_CACHE_nC:
+ return GIC_BASER_CACHE_RaWb;
+ default:
+ return field;
+ }
+}
+
+/* Non-cacheable or same-as-inner are OK. */
+u64 vgic_sanitise_outer_cacheability(u64 field)
+{
+ switch ( field )
+ {
+ case GIC_BASER_CACHE_SameAsInner:
+ case GIC_BASER_CACHE_nC:
+ return field;
+ default:
+ return GIC_BASER_CACHE_SameAsInner;
+ }
+}
+
+u64 vgic_sanitise_field(u64 reg, u64 field_mask, int field_shift,
+ u64 (*sanitise_fn)(u64))
+{
+ u64 field = (reg & field_mask) >> field_shift;
+
+ field = sanitise_fn(field) << field_shift;
+ return (reg & ~field_mask) | field;
+}
+
+#define PROPBASER_RES0_MASK \
+ (GENMASK_ULL(63, 59) | GENMASK_ULL(55, 52) | GENMASK_ULL(6, 5))
+#define PENDBASER_RES0_MASK \
+ (BIT(63, ULL) | GENMASK_ULL(61, 59) | GENMASK_ULL(55, 52) | \
+ GENMASK_ULL(15, 12) | GENMASK_ULL(6, 0))
+
+static u64 vgic_sanitise_pendbaser(u64 reg)
+{
+ reg = vgic_sanitise_field(reg, GICR_PENDBASER_SHAREABILITY_MASK,
+ GICR_PENDBASER_SHAREABILITY_SHIFT,
+ vgic_sanitise_shareability);
+ reg = vgic_sanitise_field(reg, GICR_PENDBASER_INNER_CACHEABILITY_MASK,
+ GICR_PENDBASER_INNER_CACHEABILITY_SHIFT,
+ vgic_sanitise_inner_cacheability);
+ reg = vgic_sanitise_field(reg, GICR_PENDBASER_OUTER_CACHEABILITY_MASK,
+ GICR_PENDBASER_OUTER_CACHEABILITY_SHIFT,
+ vgic_sanitise_outer_cacheability);
+
+ reg &= ~PENDBASER_RES0_MASK;
+
+ return reg;
+}
+
+static u64 vgic_sanitise_propbaser(u64 reg)
+{
+ reg = vgic_sanitise_field(reg, GICR_PROPBASER_SHAREABILITY_MASK,
+ GICR_PROPBASER_SHAREABILITY_SHIFT,
+ vgic_sanitise_shareability);
+ reg = vgic_sanitise_field(reg, GICR_PROPBASER_INNER_CACHEABILITY_MASK,
+ GICR_PROPBASER_INNER_CACHEABILITY_SHIFT,
+ vgic_sanitise_inner_cacheability);
+ reg = vgic_sanitise_field(reg, GICR_PROPBASER_OUTER_CACHEABILITY_MASK,
+ GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT,
+ vgic_sanitise_outer_cacheability);
+
+ reg &= ~PROPBASER_RES0_MASK;
+ return reg;
+}
+
+static unsigned long vgic_mmio_read_propbase(struct vcpu *vcpu, paddr_t addr,
+ unsigned int len)
+{
+ struct vgic_dist *dist = &vcpu->domain->arch.vgic;
+
+ return extract_bytes(dist->propbaser, addr & 7, len);
+}
+
+static void vgic_mmio_write_propbase(struct vcpu *vcpu, paddr_t addr,
+ unsigned int len, unsigned long val)
+{
+ struct vgic_dist *dist = &vcpu->domain->arch.vgic;
+ u64 old_propbaser, propbaser;
+
+ /* Storing a value with LPIs already enabled is undefined */
+ if ( vgic_lpis_enabled(vcpu) )
+ return;
+
+ do
+ {
+ old_propbaser = dist->propbaser;
+ propbaser = old_propbaser;
+ propbaser = update_64bit_reg(propbaser, addr & 4, len, val);
+ propbaser = vgic_sanitise_propbaser(propbaser);
+ } while ( cmpxchg64(&dist->propbaser, old_propbaser, propbaser) !=
+ old_propbaser );
+}
+
+static unsigned long vgic_mmio_read_pendbase(struct vcpu *vcpu, paddr_t addr,
+ unsigned int len)
+{
+ struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic;
+ u64 value = vgic_cpu->pendbaser;
+
+ value &= ~GICR_PENDBASER_PTZ;
+
+ return extract_bytes(value, addr & 7, len);
+}
+
+static void vgic_mmio_write_pendbase(struct vcpu *vcpu, paddr_t addr,
+ unsigned int len, unsigned long val)
+{
+ struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic;
+ u64 old_pendbaser, pendbaser;
+
+ /* Storing a value with LPIs already enabled is undefined */
+ if ( vgic_lpis_enabled(vcpu) )
+ return;
+
+ do
+ {
+ old_pendbaser = vgic_cpu->pendbaser;
+ pendbaser = old_pendbaser;
+ pendbaser = update_64bit_reg(pendbaser, addr & 4, len, val);
+ pendbaser = vgic_sanitise_pendbaser(pendbaser);
+ } while ( cmpxchg64(&vgic_cpu->pendbaser, old_pendbaser, pendbaser) !=
+ old_pendbaser );
+}
+
static const struct vgic_register_region vgic_v3_dist_registers[] = {
REGISTER_DESC_WITH_LENGTH(GICD_CTLR,
vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc,
@@ -435,10 +599,10 @@ static const struct vgic_register_region vgic_v3_rd_registers[] = {
vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
VGIC_ACCESS_32bit),
REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER,
- vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
+ vgic_mmio_read_propbase, vgic_mmio_write_propbase, 8,
VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
REGISTER_DESC_WITH_LENGTH(GICR_PENDBASER,
- vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
+ vgic_mmio_read_pendbase, vgic_mmio_write_pendbase, 8,
VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
REGISTER_DESC_WITH_LENGTH(GICR_INVLPIR,
vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [XEN PATCH v2 12/25] arm: new VGIC: Wire new GICv3 into the build system
2023-11-10 12:56 [XEN PATCH v2 00/25] arm: Add GICv3 support to the New VGIC Mykyta Poturai
` (12 preceding siblings ...)
2023-11-10 12:56 ` [XEN PATCH v2 13/25] arm: new VGIC: Handle ITS related GICv3 redistributor registers Mykyta Poturai
@ 2023-11-10 12:56 ` Mykyta Poturai
2023-11-10 12:56 ` [XEN PATCH v2 15/25] arm: new VGIC: its: Introduce ITS device list Mykyta Poturai
` (10 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Mykyta Poturai @ 2023-11-10 12:56 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org
Cc: Mykyta Poturai, Stefano Stabellini, Julien Grall,
Bertrand Marquis, Volodymyr Babchuk, Michal Orzel
Remove !NEW_VGIC dependency from GICV3 config and add new GICv3 files to
the build system.
Signed-off-by: Mykyta Poturai <mykyta_poturai@epam.com>
---
xen/arch/arm/Kconfig | 1 -
xen/arch/arm/vgic/Makefile | 2 ++
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig
index 2939db429b..c91011bc15 100644
--- a/xen/arch/arm/Kconfig
+++ b/xen/arch/arm/Kconfig
@@ -82,7 +82,6 @@ config ARM_EFI
config GICV3
bool "GICv3 driver"
- depends on !NEW_VGIC
default n if ARM_32
default y if ARM_64
---help---
diff --git a/xen/arch/arm/vgic/Makefile b/xen/arch/arm/vgic/Makefile
index 806826948e..21a71d2502 100644
--- a/xen/arch/arm/vgic/Makefile
+++ b/xen/arch/arm/vgic/Makefile
@@ -1,5 +1,7 @@
obj-y += vgic.o
obj-y += vgic-v2.o
+obj-$(CONFIG_GICV3) += vgic-v3.o
obj-y += vgic-mmio.o
obj-y += vgic-mmio-v2.o
+obj-$(CONFIG_GICV3) += vgic-mmio-v3.o
obj-y += vgic-init.o
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [XEN PATCH v2 15/25] arm: new VGIC: its: Introduce ITS device list
2023-11-10 12:56 [XEN PATCH v2 00/25] arm: Add GICv3 support to the New VGIC Mykyta Poturai
` (13 preceding siblings ...)
2023-11-10 12:56 ` [XEN PATCH v2 12/25] arm: new VGIC: Wire new GICv3 into the build system Mykyta Poturai
@ 2023-11-10 12:56 ` Mykyta Poturai
2023-11-10 12:56 ` [XEN PATCH v2 16/25] arm: new VGIC: its: Implement basic ITS register handlers Mykyta Poturai
` (9 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Mykyta Poturai @ 2023-11-10 12:56 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org
Cc: Mykyta Poturai, Stefano Stabellini, Julien Grall,
Bertrand Marquis, Volodymyr Babchuk, Michal Orzel
Add the vgic_its_device structure and the list of devices to the vgic_its.
Implement the functions to allocate, free, add and delete the device from
the list. Add the function to find the device in the list by the device id.
And make them avaliable to the HW ITS code.
Signed-off-by: Mykyta Poturai <mykyta_poturai@epam.com>
---
xen/arch/arm/include/asm/new_vgic.h | 27 +++++++++
xen/arch/arm/vgic/vgic-its.c | 86 +++++++++++++++++++++++++++++
2 files changed, 113 insertions(+)
diff --git a/xen/arch/arm/include/asm/new_vgic.h b/xen/arch/arm/include/asm/new_vgic.h
index ec2882dcf1..00a5557921 100644
--- a/xen/arch/arm/include/asm/new_vgic.h
+++ b/xen/arch/arm/include/asm/new_vgic.h
@@ -122,9 +122,26 @@ struct vgic_its {
bool enabled;
struct vgic_io_device iodev;
+ struct list_head device_list;
paddr_t doorbell_address;
};
+struct vgic_its_device {
+ struct list_head dev_list;
+ struct domain *d;
+
+ /* the head for the list of ITTEs */
+ struct list_head itt_head;
+ u32 num_eventid_bits;
+ void* itt_addr;
+ struct host_its *hw_its;
+ paddr_t guest_doorbell; /* Identifies the virtual ITS */
+ uint32_t host_devid;
+ uint32_t guest_devid;
+ uint32_t eventids; /* Number of event IDs (MSIs) */
+ uint32_t *host_lpi_blocks; /* Which LPIs are used on the host */
+};
+
struct vgic_dist {
bool ready;
bool initialized;
@@ -171,6 +188,7 @@ struct vgic_dist {
* GICv3 spec: 6.1.2 "LPI Configuration tables"
*/
uint64_t propbaser;
+ spinlock_t its_devices_lock; /* Protects the its_devices list */
/* Protects the lpi_list and the count value below. */
spinlock_t lpi_list_lock;
@@ -227,6 +245,15 @@ static inline paddr_t vgic_dist_base(const struct vgic_dist *vgic)
return vgic->dbase;
}
+#ifdef CONFIG_HAS_ITS
+struct vgic_its_device *vgic_its_alloc_device(int nr_events);
+void vgic_its_free_device(struct vgic_its_device *its_dev);
+int vgic_its_add_device(struct domain *d, struct vgic_its_device *its_dev);
+void vgic_its_delete_device(struct domain *d, struct vgic_its_device *its_dev);
+struct vgic_its_device* vgic_its_get_device(struct domain *d, paddr_t vdoorbell,
+ uint32_t vdevid);
+#endif
+
#endif /* __ASM_ARM_NEW_VGIC_H */
/*
diff --git a/xen/arch/arm/vgic/vgic-its.c b/xen/arch/arm/vgic/vgic-its.c
index 0ae6048456..3eceadaa79 100644
--- a/xen/arch/arm/vgic/vgic-its.c
+++ b/xen/arch/arm/vgic/vgic-its.c
@@ -33,6 +33,92 @@ static unsigned long its_mmio_read_raz(struct domain *d, struct vgic_its *its,
return 0;
}
+/*
+ * Find and returns a device in the device table for an ITS.
+ * Must be called with the its_devices_lock mutex held.
+ */
+static struct vgic_its_device *find_its_device(struct vgic_its *its, u32 device_id)
+{
+ struct vgic_its_device *device;
+
+ list_for_each_entry(device, &its->device_list, dev_list)
+ if ( device_id == device->guest_devid )
+ return device;
+
+ return NULL;
+}
+
+/* Requires the its_devices_lock to be held. */
+void vgic_its_free_device(struct vgic_its_device *device)
+{
+ struct domain *d = device->d;
+
+ BUG_ON(!d);
+ list_del(&device->dev_list);
+ xfree(device);
+}
+
+/* Must be called with its_devices_lock mutex held */
+struct vgic_its_device* vgic_its_get_device(struct domain *d, paddr_t vdoorbell,
+ uint32_t vdevid)
+{
+ struct vgic_its *its = d->arch.vgic.its;
+ struct vgic_its_device *device;
+
+ if ( !its )
+ return NULL;
+
+ device = find_its_device(its, vdevid);
+ if ( !device )
+ return NULL;
+
+ return device;
+}
+
+/* Must be called with its_devices_lock mutex held */
+struct vgic_its_device *vgic_its_alloc_device(int nr_events)
+{
+ struct vgic_its_device *device;
+
+ device = xzalloc(struct vgic_its_device);
+ if ( !device )
+ goto fail;
+
+ INIT_LIST_HEAD(&device->itt_head);
+
+ device->host_lpi_blocks = xzalloc_array(uint32_t, nr_events);
+ if ( !device->host_lpi_blocks )
+ goto fail_host_lpi;
+
+ return device;
+fail_host_lpi:
+ xfree(device);
+fail:
+ return NULL;
+}
+
+/* Must be called with its_devices_lock mutex held */
+int vgic_its_add_device(struct domain *d, struct vgic_its_device *its_dev)
+{
+ struct vgic_its *its = d->arch.vgic.its;
+ if ( !its )
+ return -EINVAL;
+
+ list_add_tail(&its_dev->dev_list, &its->device_list);
+
+ return 0;
+}
+
+/* Must be called with its_devices_lock mutex held */
+void vgic_its_delete_device(struct domain *d, struct vgic_its_device *its_dev)
+{
+ struct vgic_its *its = d->arch.vgic.its;
+ if ( !its )
+ return;
+
+ list_del(&its_dev->dev_list);
+}
+
static void its_mmio_write_wi(struct domain *d, struct vgic_its *its,
paddr_t addr, unsigned int len, unsigned long val)
{
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [XEN PATCH v2 16/25] arm: new VGIC: its: Implement basic ITS register handlers
2023-11-10 12:56 [XEN PATCH v2 00/25] arm: Add GICv3 support to the New VGIC Mykyta Poturai
` (14 preceding siblings ...)
2023-11-10 12:56 ` [XEN PATCH v2 15/25] arm: new VGIC: its: Introduce ITS device list Mykyta Poturai
@ 2023-11-10 12:56 ` Mykyta Poturai
2023-11-10 12:56 ` [XEN PATCH v2 17/25] arm: new VGIC: its: Read initial LPI pending table Mykyta Poturai
` (8 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Mykyta Poturai @ 2023-11-10 12:56 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org
Cc: Mykyta Poturai, Stefano Stabellini, Julien Grall,
Bertrand Marquis, Volodymyr Babchuk, Michal Orzel
Add emulation for some basic MMIO registers used in the ITS emulation.
This includes:
- GITS_{CTLR,TYPER,IIDR}
- ID registers
- GITS_{CBASER,CREADR,CWRITER}
(which implement the ITS command buffer handling)
- GITS_BASER<n>
The registers holding base addresses and attributes are sanitised before
storing them.
Base on Linux commit 424c33830f53f2 by Andre Przywara
Signed-off-by: Mykyta Poturai <mykyta_poturai@epam.com>
---
xen/arch/arm/include/asm/gic_v3_defs.h | 4 +
xen/arch/arm/include/asm/gic_v3_its.h | 60 ++++
xen/arch/arm/include/asm/new_vgic.h | 18 +
xen/arch/arm/vgic/vgic-its.c | 465 ++++++++++++++++++++++++-
xen/arch/arm/vgic/vgic-mmio.h | 7 +
xen/arch/arm/vgic/vgic.h | 5 +
6 files changed, 546 insertions(+), 13 deletions(-)
diff --git a/xen/arch/arm/include/asm/gic_v3_defs.h b/xen/arch/arm/include/asm/gic_v3_defs.h
index 3f1f59d1c7..e4e4696de3 100644
--- a/xen/arch/arm/include/asm/gic_v3_defs.h
+++ b/xen/arch/arm/include/asm/gic_v3_defs.h
@@ -138,7 +138,11 @@
#define GIC_BASER_NonShareable 0ULL
#define GIC_BASER_InnerShareable 1ULL
#define GIC_BASER_OuterShareable 2ULL
+#define GIC_BASER_SHAREABILITY_MASK 3ULL
+#define GICR_PROPBASER_IDBITS_MASK (0x1f)
+#define GICR_PROPBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 12))
+#define GICR_PENDBASER_ADDRESS(x) ((x) & GENMASK_ULL(51, 16))
#define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT 56
#define GICR_PROPBASER_OUTER_CACHEABILITY_MASK \
(7ULL << GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT)
diff --git a/xen/arch/arm/include/asm/gic_v3_its.h b/xen/arch/arm/include/asm/gic_v3_its.h
index 4e857cac1a..b408441c6e 100644
--- a/xen/arch/arm/include/asm/gic_v3_its.h
+++ b/xen/arch/arm/include/asm/gic_v3_its.h
@@ -36,7 +36,16 @@
#define GITS_BASER6 0x130
#define GITS_BASER7 0x138
#define GITS_IDREGS_BASE 0xffd0
+#define GITS_PIDR0 0xffe0
+#define GITS_PIDR1 0xffe4
#define GITS_PIDR2 GICR_PIDR2
+#define GITS_PIDR4 0xffd0
+#define GITS_CIDR0 0xfff0
+#define GITS_CIDR1 0xfff4
+#define GITS_CIDR2 0xfff8
+#define GITS_CIDR3 0xfffc
+
+#define GITS_TRANSLATER 0x10040
/* Register bits */
#define GITS_VALID_BIT BIT(63, UL)
@@ -50,6 +59,11 @@
#define GITS_TYPER_DEVICE_ID_BITS(r) ((((r) & GITS_TYPER_DEVIDS_MASK) >> \
GITS_TYPER_DEVIDS_SHIFT) + 1)
+#define GITS_IIDR_REV_SHIFT 12
+#define GITS_IIDR_REV_MASK (0xf << GITS_IIDR_REV_SHIFT)
+#define GITS_IIDR_REV(r) (((r) >> GITS_IIDR_REV_SHIFT) & 0xf)
+#define GITS_IIDR_PRODUCTID_SHIFT 24
+
#define GITS_TYPER_IDBITS_SHIFT 8
#define GITS_TYPER_IDBITS_MASK (0x1fUL << GITS_TYPER_IDBITS_SHIFT)
#define GITS_TYPER_EVENT_ID_BITS(r) ((((r) & GITS_TYPER_IDBITS_MASK) >> \
@@ -61,10 +75,12 @@
GITS_TYPER_ITT_SIZE_SHIFT) + 1)
#define GITS_TYPER_PHYSICAL (1U << 0)
+#define GITS_BASER_VALID (1ULL << 63)
#define GITS_BASER_INDIRECT BIT(62, UL)
#define GITS_BASER_INNER_CACHEABILITY_SHIFT 59
#define GITS_BASER_TYPE_SHIFT 56
#define GITS_BASER_TYPE_MASK (7ULL << GITS_BASER_TYPE_SHIFT)
+#define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7)
#define GITS_BASER_OUTER_CACHEABILITY_SHIFT 53
#define GITS_BASER_TYPE_NONE 0UL
#define GITS_BASER_TYPE_DEVICE 1UL
@@ -77,6 +93,7 @@
#define GITS_BASER_ENTRY_SIZE_SHIFT 48
#define GITS_BASER_ENTRY_SIZE(reg) \
((((reg) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1)
+#define GITS_BASER_ENTRY_SIZE_MASK GENMASK_ULL(52, 48)
#define GITS_BASER_SHAREABILITY_SHIFT 10
#define GITS_BASER_PAGE_SIZE_SHIFT 8
#define GITS_BASER_SIZE_MASK 0xff
@@ -84,7 +101,48 @@
#define GITS_BASER_OUTER_CACHEABILITY_MASK (0x7ULL << GITS_BASER_OUTER_CACHEABILITY_SHIFT)
#define GITS_BASER_INNER_CACHEABILITY_MASK (0x7ULL << GITS_BASER_INNER_CACHEABILITY_SHIFT)
+#define GIC_PAGE_SIZE_4K 0ULL
+#define GIC_PAGE_SIZE_16K 1ULL
+#define GIC_PAGE_SIZE_64K 2ULL
+#define GIC_PAGE_SIZE_MASK 3ULL
+
+#define __GITS_BASER_PSZ(sz) \
+ (GIC_PAGE_SIZE_ ## sz << GITS_BASER_PAGE_SIZE_SHIFT)
+#define GITS_BASER_PAGE_SIZE_4K __GITS_BASER_PSZ(4K)
+#define GITS_BASER_PAGE_SIZE_16K __GITS_BASER_PSZ(16K)
+#define GITS_BASER_PAGE_SIZE_64K __GITS_BASER_PSZ(64K)
+#define GITS_BASER_PAGE_SIZE_MASK __GITS_BASER_PSZ(MASK)
+
+#define GITS_BASER_NR_PAGES(r) (((r) & 0xff) + 1)
+
+#define GITS_BASER_PHYS_52_to_48(phys) \
+ (((phys) & GENMASK_ULL(47, 16)) | (((phys) >> 48) & 0xf) << 12)
+#define GITS_BASER_ADDR_48_to_52(baser) \
+ (((baser) & GENMASK_ULL(47, 16)) | (((baser) >> 12) & 0xf) << 48)
+
+#define GIC_BASER_CACHEABILITY(reg, inner_outer, type) \
+ (GIC_BASER_CACHE_##type << reg##_##inner_outer##_CACHEABILITY_SHIFT)
+
+#define GIC_BASER_SHAREABILITY(reg, type) \
+ (GIC_BASER_##type << reg##_SHAREABILITY_SHIFT)
+
#define GITS_CBASER_SIZE_MASK 0xff
+#define GITS_CBASER_VALID (1ULL << 63)
+#define GITS_CBASER_SHAREABILITY_SHIFT (10)
+#define GITS_CBASER_INNER_CACHEABILITY_SHIFT (59)
+#define GITS_CBASER_OUTER_CACHEABILITY_SHIFT (53)
+#define GITS_CBASER_SHAREABILITY_MASK \
+ GIC_BASER_SHAREABILITY(GITS_CBASER, SHAREABILITY_MASK)
+#define GITS_CBASER_INNER_CACHEABILITY_MASK \
+ GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, MASK)
+#define GITS_CBASER_OUTER_CACHEABILITY_MASK \
+ GIC_BASER_CACHEABILITY(GITS_CBASER, OUTER, MASK)
+#define GITS_CBASER_CACHEABILITY_MASK GITS_CBASER_INNER_CACHEABILITY_MASK
+
+#define GITS_CBASER_InnerShareable \
+ GIC_BASER_SHAREABILITY(GITS_CBASER, InnerShareable)
+
+#define GITS_CBASER_ADDRESS(cbaser) ((cbaser) & GENMASK_ULL(51, 12))
/* ITS command definitions */
#define ITS_CMD_SIZE 32
@@ -104,6 +162,8 @@
#define ITS_DOORBELL_OFFSET 0x10040
#define GICV3_ITS_SIZE SZ_128K
+#define ITS_TRANSLATION_OFFSET 0x10000
+#define GIC_ENCODE_SZ(n, w) (((unsigned long)(n) - 1) & GENMASK_ULL(((w) - 1), 0))
#include <xen/device_tree.h>
#include <xen/rbtree.h>
diff --git a/xen/arch/arm/include/asm/new_vgic.h b/xen/arch/arm/include/asm/new_vgic.h
index 00a5557921..3048f39844 100644
--- a/xen/arch/arm/include/asm/new_vgic.h
+++ b/xen/arch/arm/include/asm/new_vgic.h
@@ -122,7 +122,25 @@ struct vgic_its {
bool enabled;
struct vgic_io_device iodev;
+ struct domain *domain;
+
+ /* These registers correspond to GITS_BASER{0,1} */
+ u64 baser_device_table;
+ u64 baser_coll_table;
+
+ /* Protects the command queue */
+ struct spinlock cmd_lock;
+ u64 cbaser;
+ u32 creadr;
+ u32 cwriter;
+
+ /* migration ABI revision in use */
+ u32 abi_rev;
+
+ /* Protects the device and collection lists */
+ struct spinlock its_lock;
struct list_head device_list;
+ struct list_head collection_list;
paddr_t doorbell_address;
};
diff --git a/xen/arch/arm/vgic/vgic-its.c b/xen/arch/arm/vgic/vgic-its.c
index 3eceadaa79..5e94f0144d 100644
--- a/xen/arch/arm/vgic/vgic-its.c
+++ b/xen/arch/arm/vgic/vgic-its.c
@@ -27,11 +27,22 @@
#include "vgic.h"
#include "vgic-mmio.h"
-static unsigned long its_mmio_read_raz(struct domain *d, struct vgic_its *its,
- paddr_t addr, unsigned int len)
-{
- return 0;
-}
+#define COLLECTION_NOT_MAPPED ((u32)~0)
+
+struct its_collection {
+ struct list_head coll_list;
+
+ u32 collection_id;
+ u32 target_addr;
+};
+
+struct its_ite {
+ struct list_head ite_list;
+
+ struct vgic_irq *irq;
+ struct its_collection *collection;
+ u32 event_id;
+};
/*
* Find and returns a device in the device table for an ITS.
@@ -48,16 +59,68 @@ static struct vgic_its_device *find_its_device(struct vgic_its *its, u32 device_
return NULL;
}
+#define VGIC_ITS_TYPER_IDBITS 16
+#define VGIC_ITS_TYPER_DEVBITS 16
+#define VGIC_ITS_TYPER_ITE_SIZE 8
+
+/* Requires the its_lock to be held. */
+static void its_free_ite(struct domain *d, struct its_ite *ite)
+{
+ list_del(&ite->ite_list);
+
+ /* This put matches the get in vgic_add_lpi. */
+ if ( ite->irq )
+ {
+ /* GICv4 style VLPIS are not yet supported */
+ WARN_ON(ite->irq->hw);
+
+ vgic_put_irq(d, ite->irq);
+ }
+
+ xfree(ite);
+}
+
/* Requires the its_devices_lock to be held. */
void vgic_its_free_device(struct vgic_its_device *device)
{
+ struct its_ite *ite, *temp;
struct domain *d = device->d;
BUG_ON(!d);
+ /*
+ * The spec says that unmapping a device with still valid
+ * ITTEs associated is UNPREDICTABLE. We remove all ITTEs,
+ * since we cannot leave the memory unreferenced.
+ */
+ list_for_each_entry_safe(ite, temp, &device->itt_head, ite_list)
+ its_free_ite(d, ite);
+
list_del(&device->dev_list);
xfree(device);
}
+/* its lock must be held */
+static void vgic_its_free_device_list(struct domain *d, struct vgic_its *its)
+{
+ struct vgic_its_device *cur, *temp;
+
+ list_for_each_entry_safe(cur, temp, &its->device_list, dev_list)
+ vgic_its_free_device(cur);
+}
+
+/* its lock must be held */
+static void vgic_its_free_collection_list(struct domain *d,
+ struct vgic_its *its)
+{
+ struct its_collection *cur, *temp;
+
+ list_for_each_entry_safe(cur, temp, &its->collection_list, coll_list)
+ {
+ list_del(&cur->coll_list);
+ xfree(cur);
+ }
+}
+
/* Must be called with its_devices_lock mutex held */
struct vgic_its_device* vgic_its_get_device(struct domain *d, paddr_t vdoorbell,
uint32_t vdevid)
@@ -119,6 +182,349 @@ void vgic_its_delete_device(struct domain *d, struct vgic_its_device *its_dev)
list_del(&its_dev->dev_list);
}
+/*
+ * This function is called with the its_cmd lock held, but the ITS data
+ * structure lock dropped.
+ */
+static int vgic_its_handle_command(struct domain *d, struct vgic_its *its,
+ u64 *its_cmd)
+{
+
+ return -ENODEV;
+}
+
+#define ITS_CMD_BUFFER_SIZE(baser) ((((baser)&0xff) + 1) << 12)
+#define ITS_CMD_SIZE 32
+#define ITS_CMD_OFFSET(reg) ((reg)&GENMASK(19, 5))
+
+/* Must be called with the cmd_lock held. */
+static void vgic_its_process_commands(struct domain *d, struct vgic_its *its)
+{
+ paddr_t cbaser;
+ u64 cmd_buf[4];
+
+ /* Commands are only processed when the ITS is enabled. */
+ if ( !its->enabled )
+ return;
+
+ cbaser = GITS_CBASER_ADDRESS(its->cbaser);
+
+ while ( its->cwriter != its->creadr )
+ {
+ int ret = access_guest_memory_by_gpa(d, cbaser + its->creadr, cmd_buf,
+ ITS_CMD_SIZE, false);
+ /*
+ * If kvm_read_guest() fails, this could be due to the guest
+ * programming a bogus value in CBASER or something else going
+ * wrong from which we cannot easily recover.
+ * According to section 6.3.2 in the GICv3 spec we can just
+ * ignore that command then.
+ */
+ if ( !ret )
+ vgic_its_handle_command(d, its, cmd_buf);
+
+ its->creadr += ITS_CMD_SIZE;
+ if ( its->creadr == ITS_CMD_BUFFER_SIZE(its->cbaser) )
+ its->creadr = 0;
+ }
+}
+
+static unsigned long vgic_mmio_read_its_ctlr(struct domain *d,
+ struct vgic_its *its, paddr_t addr,
+ unsigned int len)
+{
+ u32 reg = 0;
+
+ spin_lock(&its->cmd_lock);
+ if ( its->creadr == its->cwriter )
+ reg |= GITS_CTLR_QUIESCENT;
+ if ( its->enabled )
+ reg |= GITS_CTLR_ENABLE;
+ spin_unlock(&its->cmd_lock);
+
+ return reg;
+}
+
+static void vgic_mmio_write_its_ctlr(struct domain *d, struct vgic_its *its,
+ paddr_t addr, unsigned int len,
+ unsigned long val)
+{
+ spin_lock(&its->cmd_lock);
+
+ /*
+ * It is UNPREDICTABLE to enable the ITS if any of the CBASER or
+ * device/collection BASER are invalid
+ */
+ if ( !its->enabled && (val & GITS_CTLR_ENABLE) &&
+ (!(its->baser_device_table & GITS_VALID_BIT) ||
+ !(its->baser_coll_table & GITS_VALID_BIT) ||
+ !(its->cbaser & GITS_VALID_BIT)) )
+ goto out;
+
+ its->enabled = !!(val & GITS_CTLR_ENABLE);
+
+ /*
+ * Try to process any pending commands. This function bails out early
+ * if the ITS is disabled or no commands have been queued.
+ */
+ vgic_its_process_commands(d, its);
+
+out:
+ spin_unlock(&its->cmd_lock);
+}
+
+static unsigned long vgic_mmio_read_its_iidr(struct domain *d,
+ struct vgic_its *its, paddr_t addr,
+ unsigned int len)
+{
+ u32 val;
+
+ val = (its->abi_rev << GITS_IIDR_REV_SHIFT) & GITS_IIDR_REV_MASK;
+ val |= (PRODUCT_ID_KVM << GITS_IIDR_PRODUCTID_SHIFT) | IMPLEMENTER_ARM;
+ return val;
+}
+
+static unsigned long vgic_mmio_read_its_typer(struct domain *d,
+ struct vgic_its *its,
+ paddr_t addr, unsigned int len)
+{
+ u64 reg = GITS_TYPER_PHYSICAL;
+
+ /*
+ * We use linear CPU numbers for redistributor addressing,
+ * so GITS_TYPER.PTA is 0.
+ * Also we force all PROPBASER registers to be the same, so
+ * CommonLPIAff is 0 as well.
+ * To avoid memory waste in the guest, we keep the number of IDBits and
+ * DevBits low - as least for the time being.
+ */
+ reg |= GIC_ENCODE_SZ(VGIC_ITS_TYPER_DEVBITS, 5) << GITS_TYPER_DEVIDS_SHIFT;
+ reg |= GIC_ENCODE_SZ(VGIC_ITS_TYPER_IDBITS, 5) << GITS_TYPER_IDBITS_SHIFT;
+ reg |= GIC_ENCODE_SZ(VGIC_ITS_TYPER_ITE_SIZE, 4) << GITS_TYPER_ITT_SIZE_SHIFT;
+
+ return extract_bytes(reg, addr & 7, len);
+}
+
+static u64 vgic_sanitise_its_baser(u64 reg)
+{
+ reg = vgic_sanitise_field(reg, GITS_BASER_SHAREABILITY_MASK,
+ GITS_BASER_SHAREABILITY_SHIFT,
+ vgic_sanitise_shareability);
+ reg = vgic_sanitise_field(reg, GITS_BASER_INNER_CACHEABILITY_MASK,
+ GITS_BASER_INNER_CACHEABILITY_SHIFT,
+ vgic_sanitise_inner_cacheability);
+ reg = vgic_sanitise_field(reg, GITS_BASER_OUTER_CACHEABILITY_MASK,
+ GITS_BASER_OUTER_CACHEABILITY_SHIFT,
+ vgic_sanitise_outer_cacheability);
+
+ /* We support only one (ITS) page size: 64K */
+ reg = (reg & ~GITS_BASER_PAGE_SIZE_MASK) | GITS_BASER_PAGE_SIZE_64K;
+
+ return reg;
+}
+
+static u64 vgic_sanitise_its_cbaser(u64 reg)
+{
+ reg = vgic_sanitise_field(reg, GITS_CBASER_SHAREABILITY_MASK,
+ GITS_CBASER_SHAREABILITY_SHIFT,
+ vgic_sanitise_shareability);
+ reg = vgic_sanitise_field(reg, GITS_CBASER_INNER_CACHEABILITY_MASK,
+ GITS_CBASER_INNER_CACHEABILITY_SHIFT,
+ vgic_sanitise_inner_cacheability);
+ reg = vgic_sanitise_field(reg, GITS_CBASER_OUTER_CACHEABILITY_MASK,
+ GITS_CBASER_OUTER_CACHEABILITY_SHIFT,
+ vgic_sanitise_outer_cacheability);
+
+ /* Sanitise the physical address to be 64k aligned. */
+ reg &= ~GENMASK_ULL(15, 12);
+
+ return reg;
+}
+
+static unsigned long vgic_mmio_read_its_cbaser(struct domain *d,
+ struct vgic_its *its,
+ paddr_t addr, unsigned int len)
+{
+ return extract_bytes(its->cbaser, addr & 7, len);
+}
+
+static void vgic_mmio_write_its_cbaser(struct domain *d, struct vgic_its *its,
+ paddr_t addr, unsigned int len,
+ unsigned long val)
+{
+ /* When GITS_CTLR.Enable is 1, this register is RO. */
+ if ( its->enabled )
+ return;
+
+ spin_lock(&its->cmd_lock);
+ its->cbaser = update_64bit_reg(its->cbaser, addr & 7, len, val);
+ its->cbaser = vgic_sanitise_its_cbaser(its->cbaser);
+ its->creadr = 0;
+ /*
+ * CWRITER is architecturally UNKNOWN on reset, but we need to reset
+ * it to CREADR to make sure we start with an empty command buffer.
+ */
+ its->cwriter = its->creadr;
+ spin_unlock(&its->cmd_lock);
+}
+
+static unsigned long vgic_mmio_read_its_cwriter(struct domain *d,
+ struct vgic_its *its,
+ paddr_t addr, unsigned int len)
+{
+ return extract_bytes(its->cwriter, addr & 0x7, len);
+}
+
+/*
+ * By writing to CWRITER the guest announces new commands to be processed.
+ * To avoid any races in the first place, we take the its_cmd lock, which
+ * protects our ring buffer variables, so that there is only one user
+ * per ITS handling commands at a given time.
+ */
+static void vgic_mmio_write_its_cwriter(struct domain *d, struct vgic_its *its,
+ paddr_t addr, unsigned int len,
+ unsigned long val)
+{
+ u64 reg;
+
+ if ( !its )
+ return;
+
+ spin_lock(&its->cmd_lock);
+
+ reg = update_64bit_reg(its->cwriter, addr & 7, len, val);
+ reg = ITS_CMD_OFFSET(reg);
+ if ( reg >= ITS_CMD_BUFFER_SIZE(its->cbaser) )
+ {
+ spin_unlock(&its->cmd_lock);
+ return;
+ }
+ its->cwriter = reg;
+
+ vgic_its_process_commands(d, its);
+
+ spin_unlock(&its->cmd_lock);
+}
+
+static unsigned long vgic_mmio_read_its_creadr(struct domain *d,
+ struct vgic_its *its,
+ paddr_t addr, unsigned int len)
+{
+ return extract_bytes(its->creadr, addr & 0x7, len);
+}
+
+#define BASER_INDEX(addr) (((addr) / sizeof(u64)) & 0x7)
+
+static unsigned long vgic_mmio_read_its_baser(struct domain *d,
+ struct vgic_its *its,
+ paddr_t addr, unsigned int len)
+{
+ uint64_t reg;
+
+ switch ( BASER_INDEX(addr) )
+ {
+ case 0:
+ reg = its->baser_device_table;
+ break;
+ case 1:
+ reg = its->baser_coll_table;
+ break;
+ default:
+ reg = 0;
+ break;
+ }
+
+ return extract_bytes(reg, addr & 7, len);
+}
+
+#define GITS_BASER_RO_MASK (GENMASK_ULL(52, 48) | GENMASK_ULL(58, 56))
+#define VGIC_ITS_BASER_DTE_SIZE 8
+#define VGIC_ITS_BASER_CTE_SIZE 8
+
+static void vgic_mmio_write_its_baser(struct domain *d, struct vgic_its *its,
+ paddr_t addr, unsigned int len,
+ unsigned long val)
+{
+ u64 entry_size, table_type;
+ u64 reg, *regptr, clearbits = 0;
+
+ /* When GITS_CTLR.Enable is 1, we ignore write accesses. */
+ if ( its->enabled )
+ return;
+
+ switch ( BASER_INDEX(addr) )
+ {
+ case 0:
+ regptr = &its->baser_device_table;
+ entry_size = VGIC_ITS_BASER_DTE_SIZE;
+ table_type = GITS_BASER_TYPE_DEVICE;
+ break;
+ case 1:
+ regptr = &its->baser_coll_table;
+ entry_size = VGIC_ITS_BASER_CTE_SIZE;
+ table_type = GITS_BASER_TYPE_COLLECTION;
+ clearbits = GITS_BASER_INDIRECT;
+ break;
+ default:
+ return;
+ }
+
+ reg = update_64bit_reg(*regptr, addr & 7, len, val);
+ reg &= ~GITS_BASER_RO_MASK;
+ reg &= ~clearbits;
+
+ reg |= (entry_size - 1) << GITS_BASER_ENTRY_SIZE_SHIFT;
+ reg |= table_type << GITS_BASER_TYPE_SHIFT;
+ reg = vgic_sanitise_its_baser(reg);
+
+ *regptr = reg;
+
+ if ( !(reg & GITS_BASER_VALID) )
+ {
+ /* Take the its_lock to prevent a race with a save/restore */
+ spin_lock(&its->its_lock);
+ switch ( table_type )
+ {
+ case GITS_BASER_TYPE_DEVICE:
+ vgic_its_free_device_list(d, its);
+ break;
+ case GITS_BASER_TYPE_COLLECTION:
+ vgic_its_free_collection_list(d, its);
+ break;
+ }
+ spin_unlock(&its->its_lock);
+ }
+}
+
+
+static unsigned long vgic_mmio_read_its_idregs(struct domain *d,
+ struct vgic_its *its,
+ paddr_t addr, unsigned int len)
+{
+ switch ( addr & 0xffff )
+ {
+ case GITS_PIDR0:
+ return 0x92; /* part number, bits[7:0] */
+ case GITS_PIDR1:
+ return 0xb4; /* part number, bits[11:8] */
+ case GITS_PIDR2:
+ return GIC_PIDR2_ARCH_GICv3 | 0x0b;
+ case GITS_PIDR4:
+ return 0x40; /* This is a 64K software visible page */
+ /* The following are the ID registers for (any) GIC. */
+ case GITS_CIDR0:
+ return 0x0d;
+ case GITS_CIDR1:
+ return 0xf0;
+ case GITS_CIDR2:
+ return 0x05;
+ case GITS_CIDR3:
+ return 0xb1;
+ }
+
+ return 0;
+}
+
static void its_mmio_write_wi(struct domain *d, struct vgic_its *its,
paddr_t addr, unsigned int len, unsigned long val)
{
@@ -133,28 +539,28 @@ static void its_mmio_write_wi(struct domain *d, struct vgic_its *its,
static struct vgic_register_region its_registers[] = {
REGISTER_ITS_DESC(GITS_CTLR,
- its_mmio_read_raz, its_mmio_write_wi, 4,
+ vgic_mmio_read_its_ctlr, vgic_mmio_write_its_ctlr, 4,
VGIC_ACCESS_32bit),
REGISTER_ITS_DESC(GITS_IIDR,
- its_mmio_read_raz, its_mmio_write_wi, 4,
+ vgic_mmio_read_its_iidr, its_mmio_write_wi, 4,
VGIC_ACCESS_32bit),
REGISTER_ITS_DESC(GITS_TYPER,
- its_mmio_read_raz, its_mmio_write_wi, 8,
+ vgic_mmio_read_its_typer, its_mmio_write_wi, 8,
VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
REGISTER_ITS_DESC(GITS_CBASER,
- its_mmio_read_raz, its_mmio_write_wi, 8,
+ vgic_mmio_read_its_cbaser, vgic_mmio_write_its_cbaser, 8,
VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
REGISTER_ITS_DESC(GITS_CWRITER,
- its_mmio_read_raz, its_mmio_write_wi, 8,
+ vgic_mmio_read_its_cwriter, vgic_mmio_write_its_cwriter, 8,
VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
REGISTER_ITS_DESC(GITS_CREADR,
- its_mmio_read_raz, its_mmio_write_wi, 8,
+ vgic_mmio_read_its_creadr, its_mmio_write_wi, 8,
VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
REGISTER_ITS_DESC(GITS_BASER0,
- its_mmio_read_raz, its_mmio_write_wi, 0x40,
+ vgic_mmio_read_its_baser, vgic_mmio_write_its_baser, 0x40,
VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
REGISTER_ITS_DESC(GITS_IDREGS_BASE,
- its_mmio_read_raz, its_mmio_write_wi, 0x30,
+ vgic_mmio_read_its_idregs, its_mmio_write_wi, 0x30,
VGIC_ACCESS_32bit),
};
@@ -184,6 +590,17 @@ out:
return ret;
}
+#define INITIAL_BASER_VALUE \
+ (GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWb) | \
+ GIC_BASER_CACHEABILITY(GITS_BASER, OUTER, SameAsInner) | \
+ GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable) | \
+ GITS_BASER_PAGE_SIZE_64K)
+
+#define INITIAL_PROPBASER_VALUE \
+ (GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, RaWb) | \
+ GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, SameAsInner) | \
+ GIC_BASER_SHAREABILITY(GICR_PROPBASER, InnerShareable))
+
static int vgic_its_create(struct domain *d, u64 addr)
{
struct vgic_its *its;
@@ -194,11 +611,25 @@ static int vgic_its_create(struct domain *d, u64 addr)
d->arch.vgic.its = its;
+ spin_lock_init(&its->its_lock);
+ spin_lock_init(&its->cmd_lock);
+
its->vgic_its_base = VGIC_ADDR_UNDEF;
+ INIT_LIST_HEAD(&its->device_list);
+ INIT_LIST_HEAD(&its->collection_list);
+ spin_lock_init(&d->arch.vgic.its_devices_lock);
+
d->arch.vgic.msis_require_devid = true;
d->arch.vgic.has_its = true;
its->enabled = false;
+ its->domain = d;
+
+ its->baser_device_table = INITIAL_BASER_VALUE | ((u64)GITS_BASER_TYPE_DEVICE
+ << GITS_BASER_TYPE_SHIFT);
+ its->baser_coll_table = INITIAL_BASER_VALUE |
+ ((u64)GITS_BASER_TYPE_COLLECTION << GITS_BASER_TYPE_SHIFT);
+ d->arch.vgic.propbaser = INITIAL_PROPBASER_VALUE;
vgic_register_its_iodev(d, its, addr);
@@ -241,6 +672,14 @@ void vgic_v3_its_free_domain(struct domain *d)
{
struct vgic_its *its = d->arch.vgic.its;
+ spin_lock(&its->its_lock);
+ spin_lock(&d->arch.vgic.its_devices_lock);
+
+ vgic_its_free_device_list(d, its);
+ vgic_its_free_collection_list(d, its);
+
+ spin_unlock(&d->arch.vgic.its_devices_lock);
+ spin_unlock(&its->its_lock);
xfree(its);
d->arch.vgic.its = NULL;
}
diff --git a/xen/arch/arm/vgic/vgic-mmio.h b/xen/arch/arm/vgic/vgic-mmio.h
index 0a8deb46ba..edf8665cda 100644
--- a/xen/arch/arm/vgic/vgic-mmio.h
+++ b/xen/arch/arm/vgic/vgic-mmio.h
@@ -146,4 +146,11 @@ void vgic_mmio_write_config(struct vcpu *vcpu,
unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev);
+/* extract @num bytes at @offset bytes offset in data */
+unsigned long extract_bytes(uint64_t data, unsigned int offset,
+ unsigned int num);
+
+uint64_t update_64bit_reg(u64 reg, unsigned int offset, unsigned int len,
+ unsigned long val);
+
#endif
diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h
index 791c91ebb3..a14b519f77 100644
--- a/xen/arch/arm/vgic/vgic.h
+++ b/xen/arch/arm/vgic/vgic.h
@@ -80,6 +80,11 @@ bool vgic_v3_emulate_reg(struct cpu_user_regs *regs, union hsr hsr);
unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev);
int vgic_v3_set_redist_base(struct domain *d, u32 index, u64 addr, u32 count);
int vgic_register_redist_iodev(struct vcpu *vcpu);
+u64 vgic_sanitise_field(u64 reg, u64 field_mask, int field_shift,
+ u64 (*sanitise_fn)(u64));
+u64 vgic_sanitise_shareability(u64 field);
+u64 vgic_sanitise_inner_cacheability(u64 field);
+u64 vgic_sanitise_outer_cacheability(u64 field);
#else
static inline void vgic_v3_fold_lr_state(struct vcpu *vcpu)
{
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [XEN PATCH v2 17/25] arm: new VGIC: its: Read initial LPI pending table
2023-11-10 12:56 [XEN PATCH v2 00/25] arm: Add GICv3 support to the New VGIC Mykyta Poturai
` (15 preceding siblings ...)
2023-11-10 12:56 ` [XEN PATCH v2 16/25] arm: new VGIC: its: Implement basic ITS register handlers Mykyta Poturai
@ 2023-11-10 12:56 ` Mykyta Poturai
2023-11-10 12:56 ` [XEN PATCH v2 19/25] arm: new VGIC: its: Add LPI translation cache definition Mykyta Poturai
` (7 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Mykyta Poturai @ 2023-11-10 12:56 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org
Cc: Mykyta Poturai, Stefano Stabellini, Julien Grall,
Bertrand Marquis, Volodymyr Babchuk, Michal Orzel
The LPI pending status for a GICv3 redistributor is held in a table
in (guest) memory. To achieve reasonable performance, we cache the
pending bit in our struct vgic_irq. The initial pending state must be
read from guest memory upon enabling LPIs for this redistributor.
As we can't access the guest memory while we hold the lpi_list spinlock,
we create a snapshot of the LPI list and iterate over that.
Based on Linux commit 33d3bc9556a7d by Andre Przywara
Signed-off-by: Mykyta Poturai <mykyta_poturai@epam.com>
---
xen/arch/arm/include/asm/new_vgic.h | 5 ++
xen/arch/arm/vgic/vgic-its.c | 104 ++++++++++++++++++++++++++++
2 files changed, 109 insertions(+)
diff --git a/xen/arch/arm/include/asm/new_vgic.h b/xen/arch/arm/include/asm/new_vgic.h
index 3048f39844..d0fd15e154 100644
--- a/xen/arch/arm/include/asm/new_vgic.h
+++ b/xen/arch/arm/include/asm/new_vgic.h
@@ -264,12 +264,17 @@ static inline paddr_t vgic_dist_base(const struct vgic_dist *vgic)
}
#ifdef CONFIG_HAS_ITS
+void vgic_enable_lpis(struct vcpu *vcpu);
struct vgic_its_device *vgic_its_alloc_device(int nr_events);
void vgic_its_free_device(struct vgic_its_device *its_dev);
int vgic_its_add_device(struct domain *d, struct vgic_its_device *its_dev);
void vgic_its_delete_device(struct domain *d, struct vgic_its_device *its_dev);
struct vgic_its_device* vgic_its_get_device(struct domain *d, paddr_t vdoorbell,
uint32_t vdevid);
+#else
+static inline void vgic_enable_lpis(struct vcpu *vcpu)
+{
+}
#endif
#endif /* __ASM_ARM_NEW_VGIC_H */
diff --git a/xen/arch/arm/vgic/vgic-its.c b/xen/arch/arm/vgic/vgic-its.c
index 5e94f0144d..af19cf4414 100644
--- a/xen/arch/arm/vgic/vgic-its.c
+++ b/xen/arch/arm/vgic/vgic-its.c
@@ -63,6 +63,47 @@ static struct vgic_its_device *find_its_device(struct vgic_its *its, u32 device_
#define VGIC_ITS_TYPER_DEVBITS 16
#define VGIC_ITS_TYPER_ITE_SIZE 8
+/*
+ * Create a snapshot of the current LPIs targeting @vcpu, so that we can
+ * enumerate those LPIs without holding any lock.
+ * Returns their number and puts the kmalloc'ed array into intid_ptr.
+ */
+int vgic_copy_lpi_list(struct domain *d, struct vcpu *vcpu, u32 **intid_ptr)
+{
+ struct vgic_dist *dist = &d->arch.vgic;
+ struct vgic_irq *irq;
+ unsigned long flags;
+ u32 *intids;
+ int irq_count, i = 0;
+
+ /*
+ * There is an obvious race between allocating the array and LPIs
+ * being mapped/unmapped. If we ended up here as a result of a
+ * command, we're safe (locks are held, preventing another
+ * command). If coming from another path (such as enabling LPIs),
+ * we must be careful not to overrun the array.
+ */
+ irq_count = ACCESS_ONCE(dist->lpi_list_count);
+ intids = xmalloc_array(u32, irq_count);
+ if ( !intids )
+ return -ENOMEM;
+
+ spin_lock_irqsave(&dist->lpi_list_lock, flags);
+ list_for_each_entry(irq, &dist->lpi_list_head, lpi_list)
+ {
+ if ( i == irq_count )
+ break;
+ /* We don't need to "get" the IRQ, as we hold the list lock. */
+ if ( vcpu && irq->target_vcpu != vcpu )
+ continue;
+ intids[i++] = irq->intid;
+ }
+ spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
+
+ *intid_ptr = intids;
+ return i;
+}
+
/* Requires the its_lock to be held. */
static void its_free_ite(struct domain *d, struct its_ite *ite)
{
@@ -284,6 +325,62 @@ static unsigned long vgic_mmio_read_its_iidr(struct domain *d,
return val;
}
+/*
+ * Sync the pending table pending bit of LPIs targeting @vcpu
+ * with our own data structures. This relies on the LPI being
+ * mapped before.
+ */
+static int its_sync_lpi_pending_table(struct vcpu *vcpu)
+{
+ paddr_t pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic.pendbaser);
+ struct vgic_irq *irq;
+ int last_byte_offset = -1;
+ int ret = 0;
+ u32 *intids;
+ int nr_irqs, i;
+ unsigned long flags;
+ u8 pendmask;
+
+ nr_irqs = vgic_copy_lpi_list(vcpu->domain, vcpu, &intids);
+ if ( nr_irqs < 0 )
+ return nr_irqs;
+
+ for ( i = 0; i < nr_irqs; i++ )
+ {
+ int byte_offset, bit_nr;
+
+ byte_offset = intids[i] / BITS_PER_BYTE;
+ bit_nr = intids[i] % BITS_PER_BYTE;
+
+ /*
+ * For contiguously allocated LPIs chances are we just read
+ * this very same byte in the last iteration. Reuse that.
+ */
+ if ( byte_offset != last_byte_offset )
+ {
+ ret = access_guest_memory_by_gpa(vcpu->domain,
+ pendbase + byte_offset, &pendmask,
+ 1, false);
+ if ( ret )
+ {
+ xfree(intids);
+ return ret;
+ }
+ last_byte_offset = byte_offset;
+ }
+
+ irq = vgic_get_irq(vcpu->domain, NULL, intids[i]);
+ spin_lock_irqsave(&irq->irq_lock, flags);
+ irq->pending_latch = pendmask & (1U << bit_nr);
+ vgic_queue_irq_unlock(vcpu->domain, irq, flags);
+ vgic_put_irq(vcpu->domain, irq);
+ }
+
+ xfree(intids);
+
+ return ret;
+}
+
static unsigned long vgic_mmio_read_its_typer(struct domain *d,
struct vgic_its *its,
paddr_t addr, unsigned int len)
@@ -564,6 +661,13 @@ static struct vgic_register_region its_registers[] = {
VGIC_ACCESS_32bit),
};
+/* This is called on setting the LPI enable bit in the redistributor. */
+void vgic_enable_lpis(struct vcpu *vcpu)
+{
+ if ( !(vcpu->arch.vgic.pendbaser & GICR_PENDBASER_PTZ) )
+ its_sync_lpi_pending_table(vcpu);
+}
+
static int vgic_register_its_iodev(struct domain *d, struct vgic_its *its,
u64 addr)
{
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [XEN PATCH v2 19/25] arm: new VGIC: its: Add LPI translation cache definition
2023-11-10 12:56 [XEN PATCH v2 00/25] arm: Add GICv3 support to the New VGIC Mykyta Poturai
` (16 preceding siblings ...)
2023-11-10 12:56 ` [XEN PATCH v2 17/25] arm: new VGIC: its: Read initial LPI pending table Mykyta Poturai
@ 2023-11-10 12:56 ` Mykyta Poturai
2023-11-10 12:56 ` [XEN PATCH v2 20/25] arm: new VGIC: its: Implement ITS command queue command handlers Mykyta Poturai
` (6 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Mykyta Poturai @ 2023-11-10 12:56 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org
Cc: Mykyta Poturai, Stefano Stabellini, Julien Grall,
Bertrand Marquis, Volodymyr Babchuk, Michal Orzel
Add the basic data structure that expresses an MSI to LPI
translation as well as the allocation/release hooks.
Implement cache invalidation, lookup and storage.
The size of the cache is arbitrarily defined as 16*nr_vcpus.
This is based on Linux commits 24cab82c34aa6f, 7d825fd6eaa7467,
89489ee9ced8 and 86a7dae884f38 by Marc Zyngier
Signed-off-by: Mykyta Poturai <mykyta_poturai@epam.com>
---
xen/arch/arm/include/asm/new_vgic.h | 3 +
xen/arch/arm/vgic/vgic-its.c | 195 ++++++++++++++++++++++++++++
2 files changed, 198 insertions(+)
diff --git a/xen/arch/arm/include/asm/new_vgic.h b/xen/arch/arm/include/asm/new_vgic.h
index d0fd15e154..b038fb7861 100644
--- a/xen/arch/arm/include/asm/new_vgic.h
+++ b/xen/arch/arm/include/asm/new_vgic.h
@@ -212,6 +212,9 @@ struct vgic_dist {
spinlock_t lpi_list_lock;
struct list_head lpi_list_head;
unsigned int lpi_list_count;
+
+ /* LPI translation cache */
+ struct list_head lpi_translation_cache;
};
struct vgic_cpu {
diff --git a/xen/arch/arm/vgic/vgic-its.c b/xen/arch/arm/vgic/vgic-its.c
index 6c726dde3a..48dfa09115 100644
--- a/xen/arch/arm/vgic/vgic-its.c
+++ b/xen/arch/arm/vgic/vgic-its.c
@@ -44,6 +44,14 @@ struct its_ite {
u32 event_id;
};
+struct vgic_translation_cache_entry {
+ struct list_head entry;
+ paddr_t db;
+ u32 devid;
+ u32 eventid;
+ struct vgic_irq *irq;
+};
+
/*
* Find and returns a device in the device table for an ITS.
* Must be called with the its_devices_lock mutex held.
@@ -152,6 +160,144 @@ int vgic_copy_lpi_list(struct domain *d, struct vcpu *vcpu, u32 **intid_ptr)
return i;
}
+void __vgic_put_lpi_locked(struct domain *d, struct vgic_irq *irq)
+{
+ struct vgic_dist *dist = &d->arch.vgic;
+
+ if ( !atomic_dec_and_test(&irq->refcount) )
+ {
+ return;
+ };
+
+ list_del(&irq->lpi_list);
+ dist->lpi_list_count--;
+
+ xfree(irq);
+}
+
+static struct vgic_irq *__vgic_its_check_cache(struct vgic_dist *dist,
+ paddr_t db, u32 devid,
+ u32 eventid)
+{
+ struct vgic_translation_cache_entry *cte, *fcte;
+
+ list_for_each_entry(cte, &dist->lpi_translation_cache, entry)
+ {
+ /*
+ * If we hit a NULL entry, there is nothing after this
+ * point.
+ */
+ if ( !cte->irq )
+ break;
+
+ if ( cte->db != db || cte->devid != devid || cte->eventid != eventid )
+ continue;
+
+ /*
+ * Move this entry to the head, as it is the most
+ * recently used.
+ */
+ fcte = list_first_entry(&dist->lpi_translation_cache,
+ struct vgic_translation_cache_entry, entry);
+
+ if ( fcte->irq != cte->irq )
+ list_move(&cte->entry, &dist->lpi_translation_cache);
+
+ return cte->irq;
+ }
+
+ return NULL;
+}
+
+static struct vgic_irq *vgic_its_check_cache(struct domain *d, paddr_t db,
+ u32 devid, u32 eventid)
+{
+ struct vgic_dist *dist = &d->arch.vgic;
+ struct vgic_irq *irq;
+
+ spin_lock(&dist->lpi_list_lock);
+ irq = __vgic_its_check_cache(dist, db, devid, eventid);
+ spin_unlock(&dist->lpi_list_lock);
+
+ return irq;
+}
+
+static void vgic_its_cache_translation(struct domain *d, struct vgic_its *its,
+ u32 devid, u32 eventid,
+ struct vgic_irq *irq)
+{
+ struct vgic_dist *dist = &d->arch.vgic;
+ struct vgic_translation_cache_entry *cte;
+ unsigned long flags;
+ paddr_t db;
+
+ /* Do not cache a directly injected interrupt */
+ if ( irq->hw )
+ return;
+
+ spin_lock_irqsave(&dist->lpi_list_lock, flags);
+
+ if ( unlikely(list_empty(&dist->lpi_translation_cache)) )
+ goto out;
+
+ /*
+ * We could have raced with another CPU caching the same
+ * translation behind our back, so let's check it is not in
+ * already
+ */
+ db = its->vgic_its_base + GITS_TRANSLATER;
+ if ( __vgic_its_check_cache(dist, db, devid, eventid) )
+ goto out;
+
+ /* Always reuse the last entry (LRU policy) */
+ cte = list_last_entry(&dist->lpi_translation_cache, typeof(*cte), entry);
+
+ /*
+ * Caching the translation implies having an extra reference
+ * to the interrupt, so drop the potential reference on what
+ * was in the cache, and increment it on the new interrupt.
+ */
+ if ( cte->irq )
+ __vgic_put_lpi_locked(d, cte->irq);
+
+ vgic_get_irq_kref(irq);
+
+ cte->db = db;
+ cte->devid = devid;
+ cte->eventid = eventid;
+ cte->irq = irq;
+
+ /* Move the new translation to the head of the list */
+ list_move(&cte->entry, &dist->lpi_translation_cache);
+
+out:
+ spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
+}
+
+void vgic_its_invalidate_cache(struct domain *d)
+{
+ struct vgic_dist *dist = &d->arch.vgic;
+ struct vgic_translation_cache_entry *cte;
+ unsigned long flags;
+
+ spin_lock_irqsave(&dist->lpi_list_lock, flags);
+
+ list_for_each_entry(cte, &dist->lpi_translation_cache, entry)
+ {
+ /*
+ * If we hit a NULL entry, there is nothing after this
+ * point.
+ */
+ if ( !cte->irq )
+ break;
+
+ __vgic_put_lpi_locked(d, cte->irq);
+ cte->irq = NULL;
+ }
+
+ spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
+}
+
/* Requires the its_lock to be held. */
static void its_free_ite(struct domain *d, struct its_ite *ite)
{
@@ -184,6 +330,8 @@ void vgic_its_free_device(struct vgic_its_device *device)
list_for_each_entry_safe(ite, temp, &device->itt_head, ite_list)
its_free_ite(d, ite);
+ vgic_its_invalidate_cache(d);
+
list_del(&device->dev_list);
xfree(device);
}
@@ -351,6 +499,8 @@ static void vgic_mmio_write_its_ctlr(struct domain *d, struct vgic_its *its,
goto out;
its->enabled = !!(val & GITS_CTLR_ENABLE);
+ if ( !its->enabled )
+ vgic_its_invalidate_cache(d);
/*
* Try to process any pending commands. This function bails out early
@@ -742,6 +892,48 @@ out:
return ret;
}
+/* Default is 16 cached LPIs per vcpu */
+#define LPI_DEFAULT_PCPU_CACHE_SIZE 16
+
+void vgic_lpi_translation_cache_init(struct domain *d)
+{
+ struct vgic_dist *dist = &d->arch.vgic;
+ unsigned int sz;
+ int i;
+
+ if ( !list_empty(&dist->lpi_translation_cache) )
+ return;
+
+ sz = d->max_vcpus * LPI_DEFAULT_PCPU_CACHE_SIZE;
+
+ for ( i = 0; i < sz; i++ )
+ {
+ struct vgic_translation_cache_entry *cte;
+
+ /* An allocation failure is not fatal */
+ cte = xzalloc(struct vgic_translation_cache_entry);
+ if ( WARN_ON(!cte) )
+ break;
+
+ INIT_LIST_HEAD(&cte->entry);
+ list_add(&cte->entry, &dist->lpi_translation_cache);
+ }
+}
+
+void vgic_lpi_translation_cache_destroy(struct domain *d)
+{
+ struct vgic_dist *dist = &d->arch.vgic;
+ struct vgic_translation_cache_entry *cte, *tmp;
+
+ vgic_its_invalidate_cache(d);
+
+ list_for_each_entry_safe(cte, tmp, &dist->lpi_translation_cache, entry)
+ {
+ list_del(&cte->entry);
+ xfree(cte);
+ }
+}
+
#define INITIAL_BASER_VALUE \
(GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWb) | \
GIC_BASER_CACHEABILITY(GITS_BASER, OUTER, SameAsInner) | \
@@ -763,6 +955,8 @@ static int vgic_its_create(struct domain *d, u64 addr)
d->arch.vgic.its = its;
+ vgic_lpi_translation_cache_init(d);
+
spin_lock_init(&its->its_lock);
spin_lock_init(&its->cmd_lock);
@@ -829,6 +1023,7 @@ void vgic_v3_its_free_domain(struct domain *d)
vgic_its_free_device_list(d, its);
vgic_its_free_collection_list(d, its);
+ vgic_lpi_translation_cache_destroy(d);
spin_unlock(&d->arch.vgic.its_devices_lock);
spin_unlock(&its->its_lock);
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [XEN PATCH v2 20/25] arm: new VGIC: its: Implement ITS command queue command handlers
2023-11-10 12:56 [XEN PATCH v2 00/25] arm: Add GICv3 support to the New VGIC Mykyta Poturai
` (17 preceding siblings ...)
2023-11-10 12:56 ` [XEN PATCH v2 19/25] arm: new VGIC: its: Add LPI translation cache definition Mykyta Poturai
@ 2023-11-10 12:56 ` Mykyta Poturai
2023-11-10 12:56 ` [XEN PATCH v2 18/25] arm: new VGIC: its: Allow updates of LPI configuration table Mykyta Poturai
` (5 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Mykyta Poturai @ 2023-11-10 12:56 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org
Cc: Mykyta Poturai, Stefano Stabellini, Julien Grall,
Bertrand Marquis, Volodymyr Babchuk, Michal Orzel
The connection between a device, an event ID, the LPI number and the
associated CPU is stored in in-memory tables in a GICv3, but their
format is not specified by the spec. Instead software uses a command
queue in a ring buffer to let an ITS implementation use its own
format.
Implement handlers for the various ITS commands and let them store
the requested relation into our own data structures. Those data
structures are protected by the its_lock mutex.
Error handling is very basic at the moment, as we don't have a good
way of communicating errors to the guest (usually an SError).
The INT command handler is missing from this patch, as we gain the
capability of actually injecting MSIs into the guest only later on.
Based on Linux commit df9f58fbea9b by Andre Przywara
Signed-off-by: Mykyta Poturai <mykyta_poturai@epam.com>
---
xen/arch/arm/include/asm/gic_v3_its.h | 19 +
xen/arch/arm/vgic/vgic-its.c | 888 +++++++++++++++++++++++++-
xen/arch/arm/vgic/vgic.h | 6 +
3 files changed, 908 insertions(+), 5 deletions(-)
diff --git a/xen/arch/arm/include/asm/gic_v3_its.h b/xen/arch/arm/include/asm/gic_v3_its.h
index b408441c6e..cbfd854af6 100644
--- a/xen/arch/arm/include/asm/gic_v3_its.h
+++ b/xen/arch/arm/include/asm/gic_v3_its.h
@@ -160,6 +160,25 @@
#define GITS_CMD_MOVALL 0x0e
#define GITS_CMD_DISCARD 0x0f
+/*
+ * ITS error numbers
+ */
+#define E_ITS_MOVI_UNMAPPED_INTERRUPT 0x010107
+#define E_ITS_MOVI_UNMAPPED_COLLECTION 0x010109
+#define E_ITS_INT_UNMAPPED_INTERRUPT 0x010307
+#define E_ITS_CLEAR_UNMAPPED_INTERRUPT 0x010507
+#define E_ITS_MAPD_DEVICE_OOR 0x010801
+#define E_ITS_MAPD_ITTSIZE_OOR 0x010802
+#define E_ITS_MAPC_PROCNUM_OOR 0x010902
+#define E_ITS_MAPC_COLLECTION_OOR 0x010903
+#define E_ITS_MAPTI_UNMAPPED_DEVICE 0x010a04
+#define E_ITS_MAPTI_ID_OOR 0x010a05
+#define E_ITS_MAPTI_PHYSICALID_OOR 0x010a06
+#define E_ITS_INV_UNMAPPED_INTERRUPT 0x010c07
+#define E_ITS_INVALL_UNMAPPED_COLLECTION 0x010d09
+#define E_ITS_MOVALL_PROCNUM_OOR 0x010e01
+#define E_ITS_DISCARD_UNMAPPED_INTERRUPT 0x010f07
+
#define ITS_DOORBELL_OFFSET 0x10040
#define GICV3_ITS_SIZE SZ_128K
#define ITS_TRANSLATION_OFFSET 0x10000
diff --git a/xen/arch/arm/vgic/vgic-its.c b/xen/arch/arm/vgic/vgic-its.c
index 48dfa09115..9a30087d3d 100644
--- a/xen/arch/arm/vgic/vgic-its.c
+++ b/xen/arch/arm/vgic/vgic-its.c
@@ -52,6 +52,9 @@ struct vgic_translation_cache_entry {
struct vgic_irq *irq;
};
+#define its_is_collection_mapped(coll) \
+ ((coll) && ((coll)->target_addr != COLLECTION_NOT_MAPPED))
+
/*
* Find and returns a device in the device table for an ITS.
* Must be called with the its_devices_lock mutex held.
@@ -71,8 +74,55 @@ static struct vgic_its_device *find_its_device(struct vgic_its *its, u32 device_
#define VGIC_ITS_TYPER_DEVBITS 16
#define VGIC_ITS_TYPER_ITE_SIZE 8
+/*
+ * Find and returns an interrupt translation table entry (ITTE) for a given
+ * Device ID/Event ID pair on an ITS.
+ * Must be called with the its_lock mutex held.
+ */
+static struct its_ite *find_ite(struct vgic_its *its, u32 device_id,
+ u32 event_id)
+{
+ struct vgic_its_device *device;
+ struct its_ite *ite;
+
+ spin_lock(&its->domain->arch.vgic.its_devices_lock);
+ device = find_its_device(its, device_id);
+ spin_unlock(&its->domain->arch.vgic.its_devices_lock);
+ if ( device == NULL )
+ return NULL;
+
+ list_for_each_entry(ite, &device->itt_head, ite_list)
+ if ( ite->event_id == event_id )
+ return ite;
+
+ return NULL;
+}
+
+/* To be used as an iterator this macro misses the enclosing parentheses */
+#define for_each_lpi_its(dev, ite, its) \
+ list_for_each_entry(dev, &(its)->device_list, dev_list) \
+ list_for_each_entry(ite, &(dev)->itt_head, ite_list)
+
#define GIC_LPI_OFFSET 8192
+#define VITS_TYPER_IDBITS 16
+#define VITS_TYPER_DEVBITS 16
+#define VITS_DTE_MAX_DEVID_OFFSET (BIT(14, UL) - 1)
+#define VITS_ITE_MAX_EVENTID_OFFSET (BIT(16, UL) - 1)
+
+static struct its_collection *find_collection(struct vgic_its *its, int coll_id)
+{
+ struct its_collection *collection;
+
+ list_for_each_entry(collection, &its->collection_list, coll_list)
+ {
+ if ( coll_id == collection->collection_id )
+ return collection;
+ }
+
+ return NULL;
+}
+
#define LPI_PROP_ENABLE_BIT(p) ((p)&LPI_PROP_ENABLED)
#define LPI_PROP_PRIORITY(p) ((p)&0xfc)
@@ -118,6 +168,156 @@ static int update_lpi_config(struct domain *d, struct vgic_irq *irq,
return 0;
}
+static int vgic_v3_lpi_sync_pending_status(struct domain *d, struct vgic_irq *irq)
+{
+ struct vcpu *vcpu;
+ int byte_offset, bit_nr;
+ paddr_t pendbase, ptr;
+ bool status;
+ u8 val;
+ int ret;
+ unsigned long flags;
+
+retry:
+ vcpu = irq->target_vcpu;
+ if ( !vcpu )
+ return 0;
+
+ pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic.pendbaser);
+
+ byte_offset = irq->intid / BITS_PER_BYTE;
+ bit_nr = irq->intid % BITS_PER_BYTE;
+ ptr = pendbase + byte_offset;
+
+ ret = access_guest_memory_by_gpa(d, ptr, &val, 1, false);
+ if ( ret )
+ return ret;
+
+ status = val & (1 << bit_nr);
+
+ spin_lock_irqsave(&irq->irq_lock, flags);
+ if ( irq->target_vcpu != vcpu )
+ {
+ spin_unlock_irqrestore(&irq->irq_lock, flags);
+ goto retry;
+ }
+ irq->pending_latch = status;
+ vgic_queue_irq_unlock(vcpu->domain, irq, flags);
+
+ if ( status )
+ {
+ /* clear consumed data */
+ val &= ~(1 << bit_nr);
+ ret = access_guest_memory_by_gpa(d, ptr, &val, 1, true);
+ if ( ret )
+ return ret;
+ }
+ return 0;
+}
+
+/*
+ * Creates a new (reference to a) struct vgic_irq for a given LPI.
+ * If this LPI is already mapped on another ITS, we increase its refcount
+ * and return a pointer to the existing structure.
+ * If this is a "new" LPI, we allocate and initialize a new struct vgic_irq.
+ * This function returns a pointer to the _unlocked_ structure.
+ */
+static struct vgic_irq *vgic_add_lpi(struct domain *d, struct vgic_its *its,
+ u32 intid, u32 devid, u32 eventid,
+ struct vcpu *vcpu)
+{
+ struct vgic_dist *dist = &d->arch.vgic;
+ struct vgic_irq *irq = vgic_get_irq(d, NULL, intid), *oldirq;
+ uint32_t host_lpi;
+ unsigned long flags;
+ int ret;
+
+ /* In this case there is no put, since we keep the reference. */
+ if ( irq )
+ return irq;
+
+ host_lpi = gicv3_its_get_host_lpi(its->domain,
+ its->vgic_its_base + ITS_DOORBELL_OFFSET,
+ devid, eventid);
+
+ if ( host_lpi == INVALID_LPI )
+ return ERR_PTR(-EINVAL);
+
+ gicv3_lpi_update_host_entry(host_lpi, d->domain_id, intid);
+
+ irq = xzalloc(struct vgic_irq);
+
+ if ( !irq )
+ return ERR_PTR(-ENOMEM);
+
+ memset(irq, 0, sizeof(*irq));
+
+ INIT_LIST_HEAD(&irq->lpi_list);
+ INIT_LIST_HEAD(&irq->ap_list);
+ spin_lock_init(&irq->irq_lock);
+
+ irq->config = VGIC_CONFIG_EDGE;
+ atomic_set(&irq->refcount, 1);
+ irq->intid = intid;
+ irq->target_vcpu = vcpu;
+
+ spin_lock_irqsave(&dist->lpi_list_lock, flags);
+
+ /*
+ * There could be a race with another vgic_add_lpi(), so we need to
+ * check that we don't add a second list entry with the same LPI.
+ */
+ list_for_each_entry(oldirq, &dist->lpi_list_head, lpi_list)
+ {
+ if ( oldirq->intid != intid )
+ continue;
+
+ /* Someone was faster with adding this LPI, lets use that. */
+ gicv3_lpi_update_host_entry(host_lpi, d->domain_id, INVALID_LPI);
+ irq = oldirq;
+
+ /*
+ * This increases the refcount, the caller is expected to
+ * call vgic_put_irq() on the returned pointer once it's
+ * finished with the IRQ.
+ */
+ vgic_get_irq_kref(irq);
+
+ goto out_unlock;
+ }
+
+ list_add_tail(&irq->lpi_list, &dist->lpi_list_head);
+ dist->lpi_list_count++;
+
+out_unlock:
+ spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
+
+ /*
+ * We "cache" the configuration table entries in our struct vgic_irq's.
+ * However we only have those structs for mapped IRQs, so we read in
+ * the respective config data from memory here upon mapping the LPI.
+ *
+ * Should any of these fail, behave as if we couldn't create the LPI
+ * by dropping the refcount and returning the error.
+ */
+ ret = update_lpi_config(d, irq, NULL, false);
+ if ( ret )
+ {
+ vgic_put_irq(d, irq);
+ gicv3_lpi_update_host_entry(host_lpi, d->domain_id, INVALID_LPI);
+ return ERR_PTR(ret);
+ }
+
+ ret = vgic_v3_lpi_sync_pending_status(d, irq);
+ if ( ret )
+ {
+ vgic_put_irq(d, irq);
+ gicv3_lpi_update_host_entry(host_lpi, d->domain_id, INVALID_LPI);
+ return ERR_PTR(ret);
+ }
+
+ return irq;
+}
/*
* Create a snapshot of the current LPIs targeting @vcpu, so that we can
@@ -160,6 +360,57 @@ int vgic_copy_lpi_list(struct domain *d, struct vcpu *vcpu, u32 **intid_ptr)
return i;
}
+static int update_affinity(struct vgic_irq *irq, struct vcpu *vcpu)
+{
+ int ret = 0;
+ unsigned long flags;
+
+ spin_lock_irqsave(&irq->irq_lock, flags);
+ irq->target_vcpu = vcpu;
+ spin_unlock_irqrestore(&irq->irq_lock, flags);
+
+ /* GICv4 style VLPIS are not yet supported */
+ WARN_ON(irq->hw);
+
+ return ret;
+}
+
+/*
+ * Promotes the ITS view of affinity of an ITTE (which redistributor this LPI
+ * is targeting) to the VGIC's view, which deals with target VCPUs.
+ * Needs to be called whenever either the collection for a LPIs has
+ * changed or the collection itself got retargeted.
+ */
+static void update_affinity_ite(struct domain *d, struct its_ite *ite)
+{
+ struct vcpu *vcpu;
+
+ if ( !its_is_collection_mapped(ite->collection) )
+ return;
+
+ vcpu = d->vcpu[ite->collection->target_addr];
+ update_affinity(ite->irq, vcpu);
+}
+
+/*
+ * Updates the target VCPU for every LPI targeting this collection.
+ * Must be called with the its_lock mutex held.
+ */
+static void update_affinity_collection(struct domain *d, struct vgic_its *its,
+ struct its_collection *coll)
+{
+ struct vgic_its_device *device;
+ struct its_ite *ite;
+
+ for_each_lpi_its(device, ite, its)
+ {
+ if ( !ite->collection || coll != ite->collection )
+ continue;
+
+ update_affinity_ite(d, ite);
+ }
+}
+
void __vgic_put_lpi_locked(struct domain *d, struct vgic_irq *irq)
{
struct vgic_dist *dist = &d->arch.vgic;
@@ -175,6 +426,7 @@ void __vgic_put_lpi_locked(struct domain *d, struct vgic_irq *irq)
xfree(irq);
}
+
static struct vgic_irq *__vgic_its_check_cache(struct vgic_dist *dist,
paddr_t db, u32 devid,
u32 eventid)
@@ -298,6 +550,18 @@ void vgic_its_invalidate_cache(struct domain *d)
spin_unlock_irqrestore(&dist->lpi_list_lock, flags);
}
+static u32 max_lpis_propbaser(u64 propbaser)
+{
+ int nr_idbits = (propbaser & 0x1f) + 1;
+
+ return 1U << min(nr_idbits, INTERRUPT_ID_BITS_ITS);
+}
+
+static u64 its_cmd_mask_field(u64 *its_cmd, int word, int shift, int size)
+{
+ return (le64_to_cpu(its_cmd[word]) >> shift) & (BIT(size, ULL) - 1);
+}
+
/* Requires the its_lock to be held. */
static void its_free_ite(struct domain *d, struct its_ite *ite)
{
@@ -315,6 +579,194 @@ static void its_free_ite(struct domain *d, struct its_ite *ite)
xfree(ite);
}
+/* Must be called with its_lock mutex held */
+static struct its_ite *vgic_its_alloc_ite(struct vgic_its_device *device,
+ struct its_collection *collection,
+ u32 event_id)
+{
+ struct its_ite *ite;
+
+ ite = xzalloc(struct its_ite);
+ if ( !ite )
+ return ERR_PTR(-ENOMEM);
+
+ ite->event_id = event_id;
+ ite->collection = collection;
+
+ list_add_tail(&ite->ite_list, &device->itt_head);
+ return ite;
+}
+
+#define its_cmd_get_command(cmd) its_cmd_mask_field(cmd, 0, 0, 8)
+#define its_cmd_get_deviceid(cmd) its_cmd_mask_field(cmd, 0, 32, 32)
+#define its_cmd_get_size(cmd) (its_cmd_mask_field(cmd, 1, 0, 5) + 1)
+#define its_cmd_get_id(cmd) its_cmd_mask_field(cmd, 1, 0, 32)
+#define its_cmd_get_physical_id(cmd) its_cmd_mask_field(cmd, 1, 32, 32)
+#define its_cmd_get_collection(cmd) its_cmd_mask_field(cmd, 2, 0, 16)
+#define its_cmd_get_ittaddr(cmd) (its_cmd_mask_field(cmd, 2, 8, 44) << 8)
+#define its_cmd_get_target_addr(cmd) its_cmd_mask_field(cmd, 2, 16, 32)
+#define its_cmd_get_validbit(cmd) its_cmd_mask_field(cmd, 2, 63, 1)
+
+/*
+ * Check whether a guest physical address is owned by it
+*/
+static bool __is_visible_gfn_locked(struct vgic_its *its, paddr_t gpa)
+{
+ gfn_t gfn = gaddr_to_gfn(gpa);
+ volatile struct domain *d;
+ struct page_info *page;
+
+ page = mfn_to_page(gfn_to_mfn(its->domain, gfn));
+ if ( !page )
+ return false;
+
+ d = page_get_owner(page);
+ if ( !d )
+ return false;
+
+ return d == its->domain;
+}
+
+/*
+ * Check whether an event ID can be stored in the corresponding Interrupt
+ * Translation Table, which starts at device->itt_addr.
+ */
+static bool vgic_its_check_event_id(struct vgic_its *its,
+ struct vgic_its_device *device, u32 event_id)
+{
+ int ite_esz = VGIC_ITS_TYPER_ITE_SIZE;
+ paddr_t gpa;
+
+ /* max table size is: BIT_ULL(device->num_eventid_bits) * ite_esz */
+ if ( event_id >= BIT(device->num_eventid_bits, ULL) )
+ return false;
+
+ gpa = (paddr_t)device->itt_addr + event_id * ite_esz;
+ return __is_visible_gfn_locked(its, gpa);
+}
+
+/*
+ * Check whether an ID can be stored into the corresponding guest table.
+ * For a direct table this is pretty easy, but gets a bit nasty for
+ * indirect tables. We check whether the resulting guest physical address
+ * is actually valid (covered by a memslot and guest accessible).
+ * For this we have to read the respective first level entry.
+ */
+static bool vgic_its_check_id(struct vgic_its *its, u64 baser, u32 id,
+ paddr_t *eaddr)
+{
+ int l1_tbl_size = GITS_BASER_NR_PAGES(baser) * SZ_64K;
+ u64 indirect_ptr, type = GITS_BASER_TYPE(baser);
+ paddr_t base = GITS_BASER_ADDR_48_to_52(baser);
+ int esz = GITS_BASER_ENTRY_SIZE(baser);
+ int index;
+
+ switch ( type )
+ {
+ case GITS_BASER_TYPE_DEVICE:
+ if ( id >= BIT(VITS_TYPER_DEVBITS, ULL) )
+ return false;
+ break;
+ case GITS_BASER_TYPE_COLLECTION:
+ /* as GITS_TYPER.CIL == 0, ITS supports 16-bit collection ID */
+ if ( id >= BIT(16, ULL) )
+ return false;
+ break;
+ default:
+ return false;
+ }
+
+ if ( !(baser & GITS_BASER_INDIRECT) )
+ {
+ paddr_t addr;
+
+ if ( id >= (l1_tbl_size / esz) )
+ return false;
+
+ addr = base + id * esz;
+
+ if ( eaddr )
+ *eaddr = addr;
+
+ return __is_visible_gfn_locked(its, addr);
+ }
+
+ /* calculate and check the index into the 1st level */
+ index = id / (SZ_64K / esz);
+ if ( index >= (l1_tbl_size / sizeof(u64)) )
+ return false;
+
+ /* Each 1st level entry is represented by a 64-bit value. */
+ if ( access_guest_memory_by_gpa(its->domain,
+ base + index * sizeof(indirect_ptr),
+ &indirect_ptr, sizeof(indirect_ptr), 0) )
+ return false;
+
+ indirect_ptr = le64_to_cpu(indirect_ptr);
+
+ /* check the valid bit of the first level entry */
+ if ( !(indirect_ptr & BIT(63, ULL)) )
+ return false;
+
+ /* Mask the guest physical address and calculate the frame number. */
+ indirect_ptr &= GENMASK_ULL(51, 16);
+
+ /* Find the address of the actual entry */
+ index = id % (SZ_64K / esz);
+ indirect_ptr += index * esz;
+
+ if ( eaddr )
+ *eaddr = indirect_ptr;
+
+ return __is_visible_gfn_locked(its, indirect_ptr);
+}
+
+/*
+ * Add a new collection into the ITS collection table.
+ * Returns 0 on success, and a negative error value for generic errors.
+ */
+static int vgic_its_alloc_collection(struct vgic_its *its,
+ struct its_collection **colp, u32 coll_id)
+{
+ struct its_collection *collection;
+
+ collection = xzalloc(struct its_collection);
+ if ( !collection )
+ return -ENOMEM;
+
+ collection->collection_id = coll_id;
+ collection->target_addr = COLLECTION_NOT_MAPPED;
+
+ list_add_tail(&collection->coll_list, &its->collection_list);
+ *colp = collection;
+
+ return 0;
+}
+
+
+static void vgic_its_free_collection(struct vgic_its *its, u32 coll_id)
+{
+ struct its_collection *collection;
+ struct vgic_its_device *device;
+ struct its_ite *ite;
+
+ /*
+ * Clearing the mapping for that collection ID removes the
+ * entry from the list. If there wasn't any before, we can
+ * go home early.
+ */
+ collection = find_collection(its, coll_id);
+ if ( !collection )
+ return;
+
+ for_each_lpi_its( device, ite, its)
+ if ( ite->collection && ite->collection->collection_id == coll_id )
+ ite->collection = NULL;
+
+ list_del(&collection->coll_list);
+ xfree(collection);
+}
+
/* Requires the its_devices_lock to be held. */
void vgic_its_free_device(struct vgic_its_device *device)
{
@@ -352,10 +804,7 @@ static void vgic_its_free_collection_list(struct domain *d,
struct its_collection *cur, *temp;
list_for_each_entry_safe(cur, temp, &its->collection_list, coll_list)
- {
- list_del(&cur->coll_list);
- xfree(cur);
- }
+ vgic_its_free_collection(its, cur->collection_id);
}
/* Must be called with its_devices_lock mutex held */
@@ -419,6 +868,390 @@ void vgic_its_delete_device(struct domain *d, struct vgic_its_device *its_dev)
list_del(&its_dev->dev_list);
}
+/*
+ * MAPD maps or unmaps a device ID to Interrupt Translation Tables (ITTs).
+ * Must be called with the its_lock mutex held.
+ */
+
+static int vgic_its_cmd_handle_mapd(struct domain *d, struct vgic_its *its,
+ u64 *its_cmd)
+{
+ uint32_t guest_devid = its_cmd_get_deviceid(its_cmd);
+ bool valid = its_cmd_get_validbit(its_cmd);
+ u8 num_eventid_bits = its_cmd_get_size(its_cmd);
+ paddr_t itt_addr = its_cmd_get_ittaddr(its_cmd);
+ int ret = 0;
+ struct vgic_its_device *device;
+
+ if ( !vgic_its_check_id(its, its->baser_device_table, guest_devid, NULL) )
+ return E_ITS_MAPD_DEVICE_OOR;
+
+ if ( valid && num_eventid_bits > VITS_TYPER_IDBITS )
+ return E_ITS_MAPD_ITTSIZE_OOR;
+
+ /*
+ * There is no easy and clean way for Xen to know the ITS device ID of a
+ * particular (PCI) device, so we have to rely on the guest telling
+ * us about it. For *now* we are just using the device ID *Dom0* uses,
+ * because the driver there has the actual knowledge.
+ * Eventually this will be replaced with a dedicated hypercall to
+ * announce pass-through of devices.
+ */
+ if ( is_hardware_domain(its->domain) )
+ {
+ ret = gicv3_its_map_guest_device(its->domain, its->doorbell_address,
+ guest_devid,
+ its->vgic_its_base + ITS_DOORBELL_OFFSET,
+ guest_devid, BIT(num_eventid_bits, UL),
+ valid);
+ }
+
+ if ( !ret && valid ) {
+ device = vgic_its_get_device(d, its->vgic_its_base + ITS_DOORBELL_OFFSET, guest_devid);
+
+ device->itt_addr = (void *)itt_addr;
+ device->num_eventid_bits = num_eventid_bits;
+ }
+
+ return ret;
+}
+
+/*
+ * The MAPC command maps collection IDs to redistributors.
+ * Must be called with the its_lock mutex held.
+ */
+static int vgic_its_cmd_handle_mapc(struct domain *d, struct vgic_its *its,
+ u64 *its_cmd)
+{
+ u16 coll_id;
+ u32 target_addr;
+ struct its_collection *collection;
+ bool valid;
+
+ valid = its_cmd_get_validbit(its_cmd);
+ coll_id = its_cmd_get_collection(its_cmd);
+ target_addr = its_cmd_get_target_addr(its_cmd);
+
+ if ( target_addr >= d->max_vcpus )
+ return E_ITS_MAPC_PROCNUM_OOR;
+
+ if ( !valid )
+ {
+ vgic_its_free_collection(its, coll_id);
+ vgic_its_invalidate_cache(d);
+ }
+ else
+ {
+ collection = find_collection(its, coll_id);
+
+ if ( !collection )
+ {
+ int ret;
+
+ if ( !vgic_its_check_id(its, its->baser_coll_table, coll_id, NULL) )
+ return E_ITS_MAPC_COLLECTION_OOR;
+
+ ret = vgic_its_alloc_collection(its, &collection, coll_id);
+ if ( ret )
+ return ret;
+ collection->target_addr = target_addr;
+ }
+ else
+ {
+ collection->target_addr = target_addr;
+ update_affinity_collection(d, its, collection);
+ }
+ }
+
+ return 0;
+}
+
+
+/*
+ * The MAPTI and MAPI commands map LPIs to ITTEs.
+ * Must be called with its_lock mutex held.
+ */
+static int vgic_its_cmd_handle_mapi(struct domain *d, struct vgic_its *its,
+ u64 *its_cmd)
+{
+ u32 device_id = its_cmd_get_deviceid(its_cmd);
+ u32 event_id = its_cmd_get_id(its_cmd);
+ u32 coll_id = its_cmd_get_collection(its_cmd);
+ struct its_ite *ite;
+ struct vcpu *vcpu = NULL;
+ struct vgic_its_device *device;
+ struct its_collection *collection, *new_coll = NULL;
+ struct vgic_irq *irq;
+ int lpi_nr;
+
+ spin_lock(&d->arch.vgic.its_devices_lock);
+ device = find_its_device(its, device_id);
+ spin_unlock(&d->arch.vgic.its_devices_lock);
+ if ( !device )
+ return E_ITS_MAPTI_UNMAPPED_DEVICE;
+
+ if ( !vgic_its_check_event_id(its, device, event_id) )
+ return E_ITS_MAPTI_ID_OOR;
+
+ if ( its_cmd_get_command(its_cmd) == GITS_CMD_MAPTI )
+ lpi_nr = its_cmd_get_physical_id(its_cmd);
+ else
+ lpi_nr = event_id;
+ if ( lpi_nr < GIC_LPI_OFFSET ||
+ lpi_nr >= max_lpis_propbaser(d->arch.vgic.propbaser) )
+ return E_ITS_MAPTI_PHYSICALID_OOR;
+
+ /* If there is an existing mapping, behavior is UNPREDICTABLE. */
+ if ( find_ite(its, device_id, event_id) )
+ return 0;
+
+ collection = find_collection(its, coll_id);
+ if ( !collection )
+ {
+ int ret;
+
+ if ( !vgic_its_check_id(its, its->baser_coll_table, coll_id, NULL) )
+ return E_ITS_MAPC_COLLECTION_OOR;
+
+ ret = vgic_its_alloc_collection(its, &collection, coll_id);
+ if ( ret )
+ return ret;
+ new_coll = collection;
+ }
+
+ ite = vgic_its_alloc_ite(device, collection, event_id);
+ if ( IS_ERR(ite) )
+ {
+ if ( new_coll )
+ vgic_its_free_collection(its, coll_id);
+ return PTR_ERR(ite);
+ }
+
+ if ( its_is_collection_mapped(collection) )
+ vcpu = d->vcpu[collection->target_addr];
+
+ irq = vgic_add_lpi(d, its, lpi_nr, device_id, event_id, vcpu);
+ if ( IS_ERR(irq) )
+ {
+ if ( new_coll )
+ vgic_its_free_collection(its, coll_id);
+ its_free_ite(d, ite);
+ return PTR_ERR(irq);
+ }
+ ite->irq = irq;
+
+ return 0;
+}
+
+/*
+ * The MOVI command moves an ITTE to a different collection.
+ * Must be called with the its_lock mutex held.
+ */
+static int vgic_its_cmd_handle_movi(struct domain *d, struct vgic_its *its,
+ u64 *its_cmd)
+{
+ u32 device_id = its_cmd_get_deviceid(its_cmd);
+ u32 event_id = its_cmd_get_id(its_cmd);
+ u32 coll_id = its_cmd_get_collection(its_cmd);
+ struct vcpu *vcpu;
+ struct its_ite *ite;
+ struct its_collection *collection;
+
+ ite = find_ite(its, device_id, event_id);
+ if ( !ite )
+ return E_ITS_MOVI_UNMAPPED_INTERRUPT;
+
+ if ( !its_is_collection_mapped(ite->collection) )
+ return E_ITS_MOVI_UNMAPPED_COLLECTION;
+
+ collection = find_collection(its, coll_id);
+ if ( !its_is_collection_mapped(collection) )
+ return E_ITS_MOVI_UNMAPPED_COLLECTION;
+
+ ite->collection = collection;
+ vcpu = d->vcpu[collection->target_addr];
+
+ vgic_its_invalidate_cache(d);
+
+ return update_affinity(ite->irq, vcpu);
+}
+
+/*
+ * The DISCARD command frees an Interrupt Translation Table Entry (ITTE).
+ * Must be called with the its_lock mutex held.
+ */
+static int vgic_its_cmd_handle_discard(struct domain *d, struct vgic_its *its,
+ u64 *its_cmd)
+{
+ u32 device_id = its_cmd_get_deviceid(its_cmd);
+ u32 event_id = its_cmd_get_id(its_cmd);
+ struct its_ite *ite;
+
+ ite = find_ite(its, device_id, event_id);
+ if ( ite && its_is_collection_mapped(ite->collection) )
+ {
+ /*
+ * Though the spec talks about removing the pending state, we
+ * don't bother here since we clear the ITTE anyway and the
+ * pending state is a property of the ITTE struct.
+ */
+ vgic_its_invalidate_cache(d);
+
+ its_free_ite(d, ite);
+ return 0;
+ }
+
+ return E_ITS_DISCARD_UNMAPPED_INTERRUPT;
+}
+
+/*
+ * The CLEAR command removes the pending state for a particular LPI.
+ * Must be called with the its_lock mutex held.
+ */
+static int vgic_its_cmd_handle_clear(struct domain *d, struct vgic_its *its,
+ u64 *its_cmd)
+{
+ u32 device_id = its_cmd_get_deviceid(its_cmd);
+ u32 event_id = its_cmd_get_id(its_cmd);
+ struct its_ite *ite;
+
+ ite = find_ite(its, device_id, event_id);
+ if ( !ite )
+ return E_ITS_CLEAR_UNMAPPED_INTERRUPT;
+
+ ite->irq->pending_latch = false;
+
+ /* GICv4 style VLPIS are not yet supported */
+ WARN_ON(ite->irq->hw);
+
+ return 0;
+}
+
+/*
+ * The MOVALL command moves the pending state of all IRQs targeting one
+ * redistributor to another. We don't hold the pending state in the VCPUs,
+ * but in the IRQs instead, so there is really not much to do for us here.
+ * However the spec says that no IRQ must target the old redistributor
+ * afterwards, so we make sure that no LPI is using the associated target_vcpu.
+ * This command affects all LPIs in the system that target that redistributor.
+ */
+static int vgic_its_cmd_handle_movall(struct domain *d, struct vgic_its *its,
+ u64 *its_cmd)
+{
+ u32 target1_addr = its_cmd_get_target_addr(its_cmd);
+ u32 target2_addr = its_cmd_mask_field(its_cmd, 3, 16, 32);
+ struct vcpu *vcpu1, *vcpu2;
+ struct vgic_irq *irq;
+ u32 *intids;
+ int irq_count, i;
+
+ if ( target1_addr >= d->max_vcpus || target2_addr >= d->max_vcpus )
+ return E_ITS_MOVALL_PROCNUM_OOR;
+
+ if ( target1_addr == target2_addr )
+ return 0;
+
+ vcpu1 = d->vcpu[target1_addr];
+ vcpu2 = d->vcpu[target2_addr];
+
+ irq_count = vgic_copy_lpi_list(d, vcpu1, &intids);
+ if ( irq_count < 0 )
+ return irq_count;
+
+ for ( i = 0; i < irq_count; i++ )
+ {
+ irq = vgic_get_irq(d, NULL, intids[i]);
+
+ update_affinity(irq, vcpu2);
+
+ vgic_put_irq(d, irq);
+ }
+
+ vgic_its_invalidate_cache(d);
+
+ xfree(intids);
+ return 0;
+}
+
+int vgic_its_inv_lpi(struct domain *d, struct vgic_irq *irq)
+{
+ return update_lpi_config(d, irq, NULL, true);
+}
+
+/*
+ * The INV command syncs the configuration bits from the memory table.
+ * Must be called with the its_lock mutex held.
+ */
+static int vgic_its_cmd_handle_inv(struct domain *d, struct vgic_its *its,
+ u64 *its_cmd)
+{
+ u32 device_id = its_cmd_get_deviceid(its_cmd);
+ u32 event_id = its_cmd_get_id(its_cmd);
+ struct its_ite *ite;
+
+ ite = find_ite(its, device_id, event_id);
+ if ( !ite )
+ return E_ITS_INV_UNMAPPED_INTERRUPT;
+
+ return vgic_its_inv_lpi(d, ite->irq);
+}
+
+/**
+ * vgic_its_invall - invalidate all LPIs targetting a given vcpu
+ * @vcpu: the vcpu for which the RD is targetted by an invalidation
+ *
+ * Contrary to the INVALL command, this targets a RD instead of a
+ * collection, and we don't need to hold the its_lock, since no ITS is
+ * involved here.
+ */
+int vgic_its_invall(struct vcpu *vcpu)
+{
+ struct domain *d = vcpu->domain;
+ int irq_count, i = 0;
+ u32 *intids;
+
+ irq_count = vgic_copy_lpi_list(d, vcpu, &intids);
+ if ( irq_count < 0 )
+ return irq_count;
+
+ for ( i = 0; i < irq_count; i++ )
+ {
+ struct vgic_irq *irq = vgic_get_irq(d, NULL, intids[i]);
+ if ( !irq )
+ continue;
+ update_lpi_config(d, irq, vcpu, false);
+ vgic_put_irq(d, irq);
+ }
+
+ xfree(intids);
+ return 0;
+}
+
+/*
+ * The INVALL command requests flushing of all IRQ data in this collection.
+ * Find the VCPU mapped to that collection, then iterate over the VM's list
+ * of mapped LPIs and update the configuration for each IRQ which targets
+ * the specified vcpu. The configuration will be read from the in-memory
+ * configuration table.
+ * Must be called with the its_lock mutex held.
+ */
+static int vgic_its_cmd_handle_invall(struct domain *d, struct vgic_its *its,
+ u64 *its_cmd)
+{
+ u32 coll_id = its_cmd_get_collection(its_cmd);
+ struct its_collection *collection;
+ struct vcpu *vcpu;
+
+ collection = find_collection(its, coll_id);
+ if ( !its_is_collection_mapped(collection) )
+ return E_ITS_INVALL_UNMAPPED_COLLECTION;
+
+ vcpu = d->vcpu[collection->target_addr];
+ vgic_its_invall(vcpu);
+
+ return 0;
+}
+
/*
* This function is called with the its_cmd lock held, but the ITS data
* structure lock dropped.
@@ -426,8 +1259,53 @@ void vgic_its_delete_device(struct domain *d, struct vgic_its_device *its_dev)
static int vgic_its_handle_command(struct domain *d, struct vgic_its *its,
u64 *its_cmd)
{
+ int ret = -ENODEV;
+
+ spin_lock(&its->its_lock);
+ switch ( its_cmd_get_command(its_cmd) )
+ {
+ case GITS_CMD_MAPD:
+ ret = vgic_its_cmd_handle_mapd(d, its, its_cmd);
+ break;
+ case GITS_CMD_MAPC:
+ ret = vgic_its_cmd_handle_mapc(d, its, its_cmd);
+ break;
+ case GITS_CMD_MAPI:
+ ret = vgic_its_cmd_handle_mapi(d, its, its_cmd);
+ break;
+ case GITS_CMD_MAPTI:
+ ret = vgic_its_cmd_handle_mapi(d, its, its_cmd);
+ break;
+ case GITS_CMD_MOVI:
+ ret = vgic_its_cmd_handle_movi(d, its, its_cmd);
+ break;
+ case GITS_CMD_DISCARD:
+ ret = vgic_its_cmd_handle_discard(d, its, its_cmd);
+ break;
+ case GITS_CMD_CLEAR:
+ ret = vgic_its_cmd_handle_clear(d, its, its_cmd);
+ break;
+ case GITS_CMD_MOVALL:
+ ret = vgic_its_cmd_handle_movall(d, its, its_cmd);
+ break;
+ case GITS_CMD_INV:
+ ret = vgic_its_cmd_handle_inv(d, its, its_cmd);
+ break;
+ case GITS_CMD_INVALL:
+ ret = vgic_its_cmd_handle_invall(d, its, its_cmd);
+ break;
+ case GITS_CMD_SYNC:
+ /* we ignore this command: we are in sync all of the time */
+ ret = 0;
+ break;
+ default:
+ printk("Unknown GITS command\n");
+ ret = -EINVAL;
+ break;
+ }
+ spin_unlock(&its->its_lock);
- return -ENODEV;
+ return ret;
}
#define ITS_CMD_BUFFER_SIZE(baser) ((((baser)&0xff) + 1) << 12)
diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h
index a14b519f77..2bcc62432a 100644
--- a/xen/arch/arm/vgic/vgic.h
+++ b/xen/arch/arm/vgic/vgic.h
@@ -29,6 +29,7 @@
#define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF)
#define INTERRUPT_ID_BITS_SPIS 10
+#define INTERRUPT_ID_BITS_ITS 16
#define VGIC_PRI_BITS 5
#define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS)
@@ -77,6 +78,7 @@ void vgic_v3_populate_lr(struct vcpu *vcpu, struct vgic_irq *irq, int lr);
void vgic_v3_enable(struct vcpu *vcpu);
int vgic_v3_map_resources(struct domain *d);
bool vgic_v3_emulate_reg(struct cpu_user_regs *regs, union hsr hsr);
+bool vgic_lpis_enabled(struct vcpu *vcpu);
unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev);
int vgic_v3_set_redist_base(struct domain *d, u32 index, u64 addr, u32 count);
int vgic_register_redist_iodev(struct vcpu *vcpu);
@@ -111,6 +113,10 @@ static inline int vgic_v3_set_redist_base(struct domain *d, u32 index, u64 addr,
{
return 0;
}
+static inline bool vgic_lpis_enabled(struct vcpu *vcpu)
+{
+ return false;
+}
static inline int vgic_register_redist_iodev(struct vcpu *vcpu)
{
return 0;
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [XEN PATCH v2 18/25] arm: new VGIC: its: Allow updates of LPI configuration table
2023-11-10 12:56 [XEN PATCH v2 00/25] arm: Add GICv3 support to the New VGIC Mykyta Poturai
` (18 preceding siblings ...)
2023-11-10 12:56 ` [XEN PATCH v2 20/25] arm: new VGIC: its: Implement ITS command queue command handlers Mykyta Poturai
@ 2023-11-10 12:56 ` Mykyta Poturai
2023-11-10 12:56 ` [XEN PATCH v2 22/25] arm: new VGIC: its: Implement MMIO-based LPI invalidation Mykyta Poturai
` (4 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Mykyta Poturai @ 2023-11-10 12:56 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org
Cc: Mykyta Poturai, Stefano Stabellini, Julien Grall,
Bertrand Marquis, Volodymyr Babchuk, Michal Orzel
The (system-wide) LPI configuration table is held in a table in
(guest) memory. To achieve reasonable performance, we cache this data
in our struct vgic_irq. If the guest updates the configuration data
(which consists of the enable bit and the priority value), it issues
an INV or INVALL command to allow us to update our information.
Provide functions that update that information for one LPI or all LPIs
mapped to a specific collection.
Based on Linux commit f9f77af9e2a551 by Andre Przywara
Signed-off-by: Mykyta Poturai <mykyta_poturai@epam.com>
---
xen/arch/arm/vgic/vgic-its.c | 48 ++++++++++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/xen/arch/arm/vgic/vgic-its.c b/xen/arch/arm/vgic/vgic-its.c
index af19cf4414..6c726dde3a 100644
--- a/xen/arch/arm/vgic/vgic-its.c
+++ b/xen/arch/arm/vgic/vgic-its.c
@@ -63,6 +63,54 @@ static struct vgic_its_device *find_its_device(struct vgic_its *its, u32 device_
#define VGIC_ITS_TYPER_DEVBITS 16
#define VGIC_ITS_TYPER_ITE_SIZE 8
+#define GIC_LPI_OFFSET 8192
+
+#define LPI_PROP_ENABLE_BIT(p) ((p)&LPI_PROP_ENABLED)
+#define LPI_PROP_PRIORITY(p) ((p)&0xfc)
+
+/*
+ * Reads the configuration data for a given LPI from guest memory and
+ * updates the fields in struct vgic_irq.
+ * If filter_vcpu is not NULL, applies only if the IRQ is targeting this
+ * VCPU. Unconditionally applies if filter_vcpu is NULL.
+ */
+static int update_lpi_config(struct domain *d, struct vgic_irq *irq,
+ struct vcpu *filter_vcpu, bool needs_inv)
+{
+ u64 propbase = GICR_PROPBASER_ADDRESS(d->arch.vgic.propbaser);
+ u8 prop;
+ int ret;
+ unsigned long flags;
+
+ ret = access_guest_memory_by_gpa(d, propbase + irq->intid - GIC_LPI_OFFSET,
+ &prop, 1, false);
+
+ if ( ret )
+ return ret;
+
+ spin_lock_irqsave(&irq->irq_lock, flags);
+
+ if ( !filter_vcpu || filter_vcpu == irq->target_vcpu )
+ {
+ irq->priority = LPI_PROP_PRIORITY(prop);
+ irq->enabled = LPI_PROP_ENABLE_BIT(prop);
+
+ if ( !irq->hw )
+ {
+ vgic_queue_irq_unlock(d, irq, flags);
+ return 0;
+ }
+ }
+
+ spin_unlock_irqrestore(&irq->irq_lock, flags);
+
+ /* GICv4 style VLPIS are not yet supported */
+ WARN_ON(irq->hw);
+
+ return 0;
+}
+
+
/*
* Create a snapshot of the current LPIs targeting @vcpu, so that we can
* enumerate those LPIs without holding any lock.
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [XEN PATCH v2 22/25] arm: new VGIC: its: Implement MMIO-based LPI invalidation
2023-11-10 12:56 [XEN PATCH v2 00/25] arm: Add GICv3 support to the New VGIC Mykyta Poturai
` (19 preceding siblings ...)
2023-11-10 12:56 ` [XEN PATCH v2 18/25] arm: new VGIC: its: Allow updates of LPI configuration table Mykyta Poturai
@ 2023-11-10 12:56 ` Mykyta Poturai
2023-11-10 12:56 ` [XEN PATCH v2 21/25] arm: new VGIC: its: Implement MSI injection in ITS emulation Mykyta Poturai
` (3 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Mykyta Poturai @ 2023-11-10 12:56 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org
Cc: Mykyta Poturai, Stefano Stabellini, Julien Grall,
Bertrand Marquis, Volodymyr Babchuk, Michal Orzel
Since GICv4.1, it has become legal for an implementation to advertise
GICR_{INVLPIR,INVALLR,SYNCR} while having an ITS, allowing for a more
efficient invalidation scheme (no guest command queue contention when
multiple CPUs are generating invalidations).
Provide the invalidation registers as a primitive to their ITS
counterpart. Note that we don't advertise them to the guest yet.
Based on Linux commit 4645d11f4a553 by Marc Zyngier
Signed-off-by: Mykyta Poturai <mykyta_poturai@epam.com>
---
xen/arch/arm/include/asm/new_vgic.h | 1 +
xen/arch/arm/vgic/vgic-mmio-v3.c | 65 +++++++++++++++++++++++++++--
xen/arch/arm/vgic/vgic-mmio.h | 15 +++++++
3 files changed, 78 insertions(+), 3 deletions(-)
diff --git a/xen/arch/arm/include/asm/new_vgic.h b/xen/arch/arm/include/asm/new_vgic.h
index b038fb7861..dfc434ab41 100644
--- a/xen/arch/arm/include/asm/new_vgic.h
+++ b/xen/arch/arm/include/asm/new_vgic.h
@@ -239,6 +239,7 @@ struct vgic_cpu {
struct vgic_io_device rd_iodev;
struct vgic_redist_region *rdreg;
uint32_t rdreg_index;
+ atomic_t syncr_busy;
struct vgic_io_device sgi_iodev;
/* Contains the attributes and gpa of the LPI pending tables. */
diff --git a/xen/arch/arm/vgic/vgic-mmio-v3.c b/xen/arch/arm/vgic/vgic-mmio-v3.c
index 4bf8c21203..0e3835d38a 100644
--- a/xen/arch/arm/vgic/vgic-mmio-v3.c
+++ b/xen/arch/arm/vgic/vgic-mmio-v3.c
@@ -583,6 +583,65 @@ static void vgic_mmio_write_pendbase(struct vcpu *vcpu, paddr_t addr,
old_pendbaser );
}
+static unsigned long vgic_mmio_read_sync(struct vcpu *vcpu, paddr_t addr,
+ unsigned int len)
+{
+ return !!atomic_read(&vcpu->arch.vgic.syncr_busy);
+}
+
+static void vgic_set_rdist_busy(struct vcpu *vcpu, bool busy)
+{
+ if ( busy )
+ {
+ atomic_inc(&vcpu->arch.vgic.syncr_busy);
+ smp_mb__after_atomic();
+ }
+ else
+ {
+ smp_mb__before_atomic();
+ atomic_dec(&vcpu->arch.vgic.syncr_busy);
+ }
+}
+
+static void vgic_mmio_write_invlpi(struct vcpu *vcpu, paddr_t addr,
+ unsigned int len, unsigned long val)
+{
+ struct vgic_irq *irq;
+
+ /*
+ * If the guest wrote only to the upper 32bit part of the
+ * register, drop the write on the floor, as it is only for
+ * vPEs (which we don't support for obvious reasons).
+ *
+ * Also discard the access if LPIs are not enabled.
+ */
+ if ( (addr & 4) || !vgic_lpis_enabled(vcpu) )
+ return;
+
+ vgic_set_rdist_busy(vcpu, true);
+
+ irq = vgic_get_irq(vcpu->domain, NULL, val & 0xffffffff);
+ if ( irq )
+ {
+ vgic_its_inv_lpi(vcpu->domain, irq);
+ vgic_put_irq(vcpu->domain, irq);
+ }
+
+ vgic_set_rdist_busy(vcpu, false);
+}
+
+static void vgic_mmio_write_invall(struct vcpu *vcpu, paddr_t addr,
+ unsigned int len, unsigned long val)
+{
+ /* See vgic_mmio_write_invlpi() for the early return rationale */
+ if ( (addr & 4) || !vgic_lpis_enabled(vcpu) )
+ return;
+
+ vgic_set_rdist_busy(vcpu, true);
+ vgic_its_invall(vcpu);
+ vgic_set_rdist_busy(vcpu, false);
+}
+
static const struct vgic_register_region vgic_v3_dist_registers[] = {
REGISTER_DESC_WITH_LENGTH(GICD_CTLR,
vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc,
@@ -655,13 +714,13 @@ static const struct vgic_register_region vgic_v3_rd_registers[] = {
vgic_mmio_read_pendbase, vgic_mmio_write_pendbase, 8,
VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
REGISTER_DESC_WITH_LENGTH(GICR_INVLPIR,
- vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
+ vgic_mmio_read_raz, vgic_mmio_write_invlpi, 8,
VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
REGISTER_DESC_WITH_LENGTH(GICR_INVALLR,
- vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
+ vgic_mmio_read_raz, vgic_mmio_write_invall, 8,
VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
REGISTER_DESC_WITH_LENGTH(GICR_SYNCR,
- vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
+ vgic_mmio_read_sync, vgic_mmio_write_wi, 4,
VGIC_ACCESS_32bit),
REGISTER_DESC_WITH_LENGTH(GICR_IDREGS,
vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
diff --git a/xen/arch/arm/vgic/vgic-mmio.h b/xen/arch/arm/vgic/vgic-mmio.h
index edf8665cda..12f4d690f6 100644
--- a/xen/arch/arm/vgic/vgic-mmio.h
+++ b/xen/arch/arm/vgic/vgic-mmio.h
@@ -153,4 +153,19 @@ unsigned long extract_bytes(uint64_t data, unsigned int offset,
uint64_t update_64bit_reg(u64 reg, unsigned int offset, unsigned int len,
unsigned long val);
+#ifdef CONFIG_HAS_ITS
+int vgic_its_inv_lpi(struct domain *d, struct vgic_irq *irq);
+int vgic_its_invall(struct vcpu *vcpu);
+#else
+static inline int vgic_its_inv_lpi(struct domain *d, struct vgic_irq *irq)
+{
+ return 0;
+}
+
+static inline int vgic_its_invall(struct vcpu *vcpu)
+{
+ return 0;
+}
+#endif
+
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [XEN PATCH v2 21/25] arm: new VGIC: its: Implement MSI injection in ITS emulation
2023-11-10 12:56 [XEN PATCH v2 00/25] arm: Add GICv3 support to the New VGIC Mykyta Poturai
` (20 preceding siblings ...)
2023-11-10 12:56 ` [XEN PATCH v2 22/25] arm: new VGIC: its: Implement MMIO-based LPI invalidation Mykyta Poturai
@ 2023-11-10 12:56 ` Mykyta Poturai
2023-11-10 12:56 ` [XEN PATCH v2 23/25] arm: new VGIC: its: Enable ITS emulation as a virtual MSI controller Mykyta Poturai
` (2 subsequent siblings)
24 siblings, 0 replies; 26+ messages in thread
From: Mykyta Poturai @ 2023-11-10 12:56 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org
Cc: Mykyta Poturai, Stefano Stabellini, Julien Grall,
Bertrand Marquis, Volodymyr Babchuk, Michal Orzel
Implement handling of the ITS INT command.
With the help of the IO bus framework we learn the corresponding
ITS from the doorbell address. We then use our wrapper functions to
iterate the linked lists and find the proper Interrupt Translation Table
Entry (ITTE) and thus the corresponding struct vgic_irq to finally set
the pending bit.
Based on Linux commit 2891a7dfb6c4a by Andre Przywara
Signed-off-by: Mykyta Poturai <mykyta_poturai@epam.com>
---
xen/arch/arm/vgic/vgic-its.c | 112 +++++++++++++++++++++++++++++++++++
1 file changed, 112 insertions(+)
diff --git a/xen/arch/arm/vgic/vgic-its.c b/xen/arch/arm/vgic/vgic-its.c
index 9a30087d3d..9534b26334 100644
--- a/xen/arch/arm/vgic/vgic-its.c
+++ b/xen/arch/arm/vgic/vgic-its.c
@@ -557,6 +557,81 @@ static u32 max_lpis_propbaser(u64 propbaser)
return 1U << min(nr_idbits, INTERRUPT_ID_BITS_ITS);
}
+int vgic_its_resolve_lpi(struct domain *d, struct vgic_its *its, u32 devid,
+ u32 eventid, struct vgic_irq **irq)
+{
+ struct vcpu *vcpu;
+ struct its_ite *ite;
+
+ if ( !its->enabled )
+ return -EBUSY;
+
+ ite = find_ite(its, devid, eventid);
+ if ( !ite || !its_is_collection_mapped(ite->collection) )
+ return E_ITS_INT_UNMAPPED_INTERRUPT;
+
+ vcpu = d->vcpu[ite->collection->target_addr];
+ if ( !vcpu )
+ return E_ITS_INT_UNMAPPED_INTERRUPT;
+
+ if ( !vgic_lpis_enabled(vcpu) )
+ return -EBUSY;
+
+ vgic_its_cache_translation(d, its, devid, eventid, ite->irq);
+
+ *irq = ite->irq;
+ return 0;
+}
+
+int vgic_its_inject_cached_translation(struct domain *d, struct vgic_its *its, u32 devid, u32 eventid)
+{
+ struct vgic_irq *irq;
+ unsigned long flags;
+ paddr_t db;
+
+ db = its->vgic_its_base + GITS_TRANSLATER;
+ irq = vgic_its_check_cache(d, db, devid, eventid);
+ if (!irq)
+ return -EWOULDBLOCK;
+
+ spin_lock_irqsave(&irq->irq_lock, flags);
+ irq->pending_latch = true;
+ vgic_queue_irq_unlock(d, irq, flags);
+
+ return 0;
+}
+
+/*
+ * Find the target VCPU and the LPI number for a given devid/eventid pair
+ * and make this IRQ pending, possibly injecting it.
+ * Must be called with the its_lock mutex held.
+ * Returns 0 on success, a positive error value for any ITS mapping
+ * related errors and negative error values for generic errors.
+ */
+static int vgic_its_trigger_msi(struct domain *d, struct vgic_its *its,
+ u32 devid, u32 eventid)
+{
+ struct vgic_irq *irq = NULL;
+ unsigned long flags;
+ int err;
+
+ if (!vgic_its_inject_cached_translation(d, its, devid, eventid))
+ return 1;
+
+ err = vgic_its_resolve_lpi(d, its, devid, eventid, &irq);
+ if ( err )
+ return err;
+
+ /* GICv4 style VLPIS are not yet supported */
+ WARN_ON(irq->hw);
+
+ spin_lock_irqsave(&irq->irq_lock, flags);
+ irq->pending_latch = true;
+ vgic_queue_irq_unlock(d, irq, flags);
+
+ return 0;
+}
+
static u64 its_cmd_mask_field(u64 *its_cmd, int word, int shift, int size)
{
return (le64_to_cpu(its_cmd[word]) >> shift) & (BIT(size, ULL) - 1);
@@ -868,6 +943,27 @@ void vgic_its_delete_device(struct domain *d, struct vgic_its_device *its_dev)
list_del(&its_dev->dev_list);
}
+void vgic_vcpu_inject_lpi(struct domain *d, unsigned int virq)
+{
+ /*
+ * TODO: this assumes that the struct pending_irq stays valid all of
+ * the time. We cannot properly protect this with the current locking
+ * scheme, but the future per-IRQ lock will solve this problem.
+ */
+ struct vgic_irq *p = vgic_get_irq(d, d->vcpu[0], virq);
+ unsigned int vcpu_id;
+
+ if ( !p )
+ return;
+
+ vcpu_id = ACCESS_ONCE(p->target_vcpu->vcpu_id);
+ if ( vcpu_id >= d->max_vcpus )
+ return;
+
+ vgic_put_irq(d, p);
+ vgic_inject_irq(d, d->vcpu[vcpu_id], virq, true);
+}
+
/*
* MAPD maps or unmaps a device ID to Interrupt Translation Tables (ITTs).
* Must be called with the its_lock mutex held.
@@ -1173,6 +1269,19 @@ static int vgic_its_cmd_handle_movall(struct domain *d, struct vgic_its *its,
return 0;
}
+/*
+ * The INT command injects the LPI associated with that DevID/EvID pair.
+ * Must be called with the its_lock mutex held.
+ */
+static int vgic_its_cmd_handle_int(struct domain *d, struct vgic_its *its,
+ u64 *its_cmd)
+{
+ u32 msi_data = its_cmd_get_id(its_cmd);
+ u64 msi_devid = its_cmd_get_deviceid(its_cmd);
+
+ return vgic_its_trigger_msi(d, its, msi_devid, msi_data);
+}
+
int vgic_its_inv_lpi(struct domain *d, struct vgic_irq *irq)
{
return update_lpi_config(d, irq, NULL, true);
@@ -1288,6 +1397,9 @@ static int vgic_its_handle_command(struct domain *d, struct vgic_its *its,
case GITS_CMD_MOVALL:
ret = vgic_its_cmd_handle_movall(d, its, its_cmd);
break;
+ case GITS_CMD_INT:
+ ret = vgic_its_cmd_handle_int(d, its, its_cmd);
+ break;
case GITS_CMD_INV:
ret = vgic_its_cmd_handle_inv(d, its, its_cmd);
break;
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [XEN PATCH v2 23/25] arm: new VGIC: its: Enable ITS emulation as a virtual MSI controller
2023-11-10 12:56 [XEN PATCH v2 00/25] arm: Add GICv3 support to the New VGIC Mykyta Poturai
` (21 preceding siblings ...)
2023-11-10 12:56 ` [XEN PATCH v2 21/25] arm: new VGIC: its: Implement MSI injection in ITS emulation Mykyta Poturai
@ 2023-11-10 12:56 ` Mykyta Poturai
2023-11-10 12:56 ` [XEN PATCH v2 24/25] arm: new VGIC: its: Wire new ITS into the build system Mykyta Poturai
2023-11-10 12:56 ` [XEN PATCH v2 25/25] arm: new VGIC: Improve MMIO handling Mykyta Poturai
24 siblings, 0 replies; 26+ messages in thread
From: Mykyta Poturai @ 2023-11-10 12:56 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org
Cc: Mykyta Poturai, Stefano Stabellini, Julien Grall,
Bertrand Marquis, Volodymyr Babchuk, Michal Orzel
Now that all ITS emulation functionality is in place, we advertise
the ITS device to the guest.
Based on Linux commit 0e4e82f154e38 by Andre Przywara
Signed-off-by: Mykyta Poturai <mykyta_poturai@epam.com>
---
xen/arch/arm/vgic/vgic-init.c | 7 +++++
xen/arch/arm/vgic/vgic-its.c | 2 +-
xen/arch/arm/vgic/vgic-mmio-v3.c | 44 ++++++++++++++++++++++++++++++--
xen/arch/arm/vgic/vgic-mmio.h | 5 ++++
4 files changed, 55 insertions(+), 3 deletions(-)
diff --git a/xen/arch/arm/vgic/vgic-init.c b/xen/arch/arm/vgic/vgic-init.c
index 96f6669d38..fb27e440fc 100644
--- a/xen/arch/arm/vgic/vgic-init.c
+++ b/xen/arch/arm/vgic/vgic-init.c
@@ -18,6 +18,7 @@
#include <xen/lib.h>
#include <xen/sched.h>
#include <asm/new_vgic.h>
+#include <asm/gic_v3_its.h>
#include "vgic.h"
@@ -173,8 +174,14 @@ int domain_vgic_init(struct domain *d, unsigned int nr_spis)
}
INIT_LIST_HEAD(&dist->lpi_list_head);
+ INIT_LIST_HEAD(&dist->lpi_translation_cache);
+ dist->lpi_list_count=0;
spin_lock_init(&dist->lpi_list_lock);
+ ret = vgic_v3_its_init_domain(d);
+ if ( ret )
+ return ret;
+
if ( dist->version == GIC_V2 )
ret = vgic_v2_map_resources(d);
else
diff --git a/xen/arch/arm/vgic/vgic-its.c b/xen/arch/arm/vgic/vgic-its.c
index 9534b26334..3b097bd0c4 100644
--- a/xen/arch/arm/vgic/vgic-its.c
+++ b/xen/arch/arm/vgic/vgic-its.c
@@ -168,7 +168,7 @@ static int update_lpi_config(struct domain *d, struct vgic_irq *irq,
return 0;
}
-static int vgic_v3_lpi_sync_pending_status(struct domain *d, struct vgic_irq *irq)
+int vgic_v3_lpi_sync_pending_status(struct domain *d, struct vgic_irq *irq)
{
struct vcpu *vcpu;
int byte_offset, bit_nr;
diff --git a/xen/arch/arm/vgic/vgic-mmio-v3.c b/xen/arch/arm/vgic/vgic-mmio-v3.c
index 0e3835d38a..84aa8568dc 100644
--- a/xen/arch/arm/vgic/vgic-mmio-v3.c
+++ b/xen/arch/arm/vgic/vgic-mmio-v3.c
@@ -29,7 +29,7 @@ bool vgic_has_its(struct domain *d)
if ( dist->version != GIC_V3 )
return false;
- return false;
+ return dist->has_its;
}
static struct vcpu *mpidr_to_vcpu(struct domain *d, unsigned long mpidr)
@@ -211,6 +211,29 @@ bool vgic_v3_emulate_reg(struct cpu_user_regs *regs, union hsr hsr)
}
}
+void vgic_flush_pending_lpis(struct vcpu *vcpu)
+{
+ struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic;
+ struct vgic_irq *irq, *tmp;
+ unsigned long flags;
+
+ spin_lock_irqsave(&vgic_cpu->ap_list_lock, flags);
+
+ list_for_each_entry_safe(irq, tmp, &vgic_cpu->ap_list_head, ap_list)
+ {
+ if ( irq->intid >= VGIC_MIN_LPI )
+ {
+ spin_lock(&irq->irq_lock);
+ list_del(&irq->ap_list);
+ irq->vcpu = NULL;
+ spin_unlock(&irq->irq_lock);
+ vgic_put_irq(vcpu->domain, irq);
+ }
+ }
+
+ spin_unlock_irqrestore(&vgic_cpu->ap_list_lock, flags);
+}
+
/*
* The Revision field in the IIDR have the following meanings:
*
@@ -234,7 +257,15 @@ static unsigned long vgic_mmio_read_v3_misc(struct vcpu *vcpu, paddr_t addr,
case GICD_TYPER:
value = vgic->nr_spis + VGIC_NR_PRIVATE_IRQS;
value = (value >> 5) - 1;
- value |= (INTERRUPT_ID_BITS_SPIS - 1) << 19;
+ if ( vgic_has_its(vcpu->domain) )
+ {
+ value |= (INTERRUPT_ID_BITS_ITS - 1) << 19;
+ value |= GICD_TYPE_LPIS;
+ }
+ else
+ {
+ value |= (INTERRUPT_ID_BITS_SPIS - 1) << 19;
+ }
break;
case GICD_TYPER2:
break;
@@ -365,6 +396,9 @@ static unsigned long vgic_mmio_read_v3r_typer(struct vcpu *vcpu, paddr_t addr,
value = (u64)(mpidr & GENMASK(23, 0)) << 32;
value |= ((target_vcpu_id & 0xffff) << 8);
+ if ( vgic_has_its(vcpu->domain) )
+ value |= GICR_TYPER_PLPIS;
+
if ( vgic_mmio_vcpu_rdist_is_last(vcpu) )
value |= GICR_TYPER_LAST;
@@ -422,12 +456,18 @@ static void vgic_mmio_write_v3r_ctlr(struct vcpu *vcpu, paddr_t addr,
GICR_CTLR_RWP);
if ( ctlr != GICR_CTLR_ENABLE_LPIS )
return;
+
+ vgic_flush_pending_lpis(vcpu);
+ vgic_its_invalidate_cache(vcpu->domain);
+ atomic_set(&vgic_cpu->ctlr, 0);
}
else
{
ctlr = atomic_cmpxchg(&vgic_cpu->ctlr, 0, GICR_CTLR_ENABLE_LPIS);
if ( ctlr != 0 )
return;
+
+ vgic_enable_lpis(vcpu);
}
}
diff --git a/xen/arch/arm/vgic/vgic-mmio.h b/xen/arch/arm/vgic/vgic-mmio.h
index 12f4d690f6..32fc7a6ba2 100644
--- a/xen/arch/arm/vgic/vgic-mmio.h
+++ b/xen/arch/arm/vgic/vgic-mmio.h
@@ -156,6 +156,7 @@ uint64_t update_64bit_reg(u64 reg, unsigned int offset, unsigned int len,
#ifdef CONFIG_HAS_ITS
int vgic_its_inv_lpi(struct domain *d, struct vgic_irq *irq);
int vgic_its_invall(struct vcpu *vcpu);
+void vgic_its_invalidate_cache(struct domain *d);
#else
static inline int vgic_its_inv_lpi(struct domain *d, struct vgic_irq *irq)
{
@@ -166,6 +167,10 @@ static inline int vgic_its_invall(struct vcpu *vcpu)
{
return 0;
}
+
+static inline void vgic_its_invalidate_cache(struct domain *d)
+{
+}
#endif
#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [XEN PATCH v2 24/25] arm: new VGIC: its: Wire new ITS into the build system
2023-11-10 12:56 [XEN PATCH v2 00/25] arm: Add GICv3 support to the New VGIC Mykyta Poturai
` (22 preceding siblings ...)
2023-11-10 12:56 ` [XEN PATCH v2 23/25] arm: new VGIC: its: Enable ITS emulation as a virtual MSI controller Mykyta Poturai
@ 2023-11-10 12:56 ` Mykyta Poturai
2023-11-10 12:56 ` [XEN PATCH v2 25/25] arm: new VGIC: Improve MMIO handling Mykyta Poturai
24 siblings, 0 replies; 26+ messages in thread
From: Mykyta Poturai @ 2023-11-10 12:56 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org
Cc: Mykyta Poturai, Stefano Stabellini, Julien Grall,
Bertrand Marquis, Volodymyr Babchuk, Michal Orzel
Add vgic-its.o to the build system.
Remove the dependency on !NEW_VGIC from CONFIG_HAS_ITS.
Signed-off-by: Mykyta Poturai <mykyta_poturai@epam.com>
---
xen/arch/arm/Kconfig | 4 ++--
xen/arch/arm/vgic/Makefile | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig
index c91011bc15..d803793b09 100644
--- a/xen/arch/arm/Kconfig
+++ b/xen/arch/arm/Kconfig
@@ -90,8 +90,8 @@ config GICV3
If unsure, use the default setting.
config HAS_ITS
- bool "GICv3 ITS MSI controller support (UNSUPPORTED)" if UNSUPPORTED
- depends on GICV3 && !NEW_VGIC && !ARM_32
+ bool "GICv3 ITS MSI controller support (UNSUPPORTED on old VGIC)" if UNSUPPORTED || NEW_VGIC
+ depends on GICV3 && !ARM_32
config OVERLAY_DTB
bool "DTB overlay support (UNSUPPORTED)" if UNSUPPORTED
diff --git a/xen/arch/arm/vgic/Makefile b/xen/arch/arm/vgic/Makefile
index 21a71d2502..fe6821c724 100644
--- a/xen/arch/arm/vgic/Makefile
+++ b/xen/arch/arm/vgic/Makefile
@@ -5,3 +5,4 @@ obj-y += vgic-mmio.o
obj-y += vgic-mmio-v2.o
obj-$(CONFIG_GICV3) += vgic-mmio-v3.o
obj-y += vgic-init.o
+obj-$(CONFIG_HAS_ITS) += vgic-its.o
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [XEN PATCH v2 25/25] arm: new VGIC: Improve MMIO handling
2023-11-10 12:56 [XEN PATCH v2 00/25] arm: Add GICv3 support to the New VGIC Mykyta Poturai
` (23 preceding siblings ...)
2023-11-10 12:56 ` [XEN PATCH v2 24/25] arm: new VGIC: its: Wire new ITS into the build system Mykyta Poturai
@ 2023-11-10 12:56 ` Mykyta Poturai
24 siblings, 0 replies; 26+ messages in thread
From: Mykyta Poturai @ 2023-11-10 12:56 UTC (permalink / raw)
To: xen-devel@lists.xenproject.org
Cc: Mykyta Poturai, Stefano Stabellini, Julien Grall,
Bertrand Marquis, Volodymyr Babchuk, Michal Orzel
Currently the full register address is used in VGIC MMIO handlers. This
can cause issues when VGIC_ADDR_TO_IRQ_MASK overlaps with the base address.
For example the current GUEST_GICV3_GICD_BASE overlaps with addr to irq
mask for 64 bit registers, causing intids to be calculated incorrectly.
This patch fixes the issue by subtracting the base address from the full
register address before passing it to the MMIO handlers. Thus giving the
MMIO handler only the relevant offset.
Signed-off-by: Mykyta Poturai <mykyta_poturai@epam.com>
---
xen/arch/arm/vgic/vgic-mmio.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/xen/arch/arm/vgic/vgic-mmio.c b/xen/arch/arm/vgic/vgic-mmio.c
index 7a28be53bc..abf7854af0 100644
--- a/xen/arch/arm/vgic/vgic-mmio.c
+++ b/xen/arch/arm/vgic/vgic-mmio.c
@@ -540,7 +540,7 @@ vgic_get_mmio_region(struct vcpu *vcpu, struct vgic_io_device *iodev,
region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,
addr - gfn_to_gaddr(iodev->base_fn));
- if ( !region || !check_region(vcpu->domain, region, addr, len) )
+ if ( !region || !check_region(vcpu->domain, region, addr - gfn_to_gaddr(iodev->base_fn), len) )
return NULL;
return region;
@@ -565,13 +565,13 @@ static int dispatch_mmio_read(struct vcpu *vcpu, mmio_info_t *info,
switch (iodev->iodev_type)
{
case IODEV_DIST:
- data = region->read(vcpu, addr, len);
+ data = region->read(vcpu, addr - gfn_to_gaddr(iodev->base_fn), len);
break;
case IODEV_REDIST:
- data = region->read(iodev->redist_vcpu, addr, len);
+ data = region->read(iodev->redist_vcpu, addr - gfn_to_gaddr(iodev->base_fn), len);
break;
case IODEV_ITS:
- data = region->its_read(vcpu->domain, iodev->its, addr, len);;
+ data = region->its_read(vcpu->domain, iodev->its, addr - gfn_to_gaddr(iodev->base_fn), len);;
break;
}
@@ -596,13 +596,13 @@ static int dispatch_mmio_write(struct vcpu *vcpu, mmio_info_t *info,
switch (iodev->iodev_type)
{
case IODEV_DIST:
- region->write(vcpu, addr, len, data);
+ region->write(vcpu, addr - gfn_to_gaddr(iodev->base_fn), len, data);
break;
case IODEV_REDIST:
- region->write(iodev->redist_vcpu, addr, len, data);
+ region->write(iodev->redist_vcpu, addr - gfn_to_gaddr(iodev->base_fn), len, data);
break;
case IODEV_ITS:
- region->its_write(vcpu->domain, iodev->its, addr, len, data);
+ region->its_write(vcpu->domain, iodev->its, addr - gfn_to_gaddr(iodev->base_fn), len, data);
break;
}
--
2.34.1
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