[PATCH v3 0/1] phy: rockchip: snps-pcie3: Fix bifurcation and spelling

[PATCH v3 0/1] phy: rockchip: snps-pcie3: Fix bifurcation and spelling

[Sebastian Kropatsch]

This is only patch 2/5 from the previous v2 patch series since the other
patches are already merged.
The title has been kept the same as v2 for patch management purposes.

Cheers,
Sebastian
---

Changes v2 -> v3:

 - Select only patch 2/5
 - Call 'dev_read_addr(udev)' only once by using 'addr' in 'priv->mmio ='
 - Remove debugging printf statements
 - Collect "Reviewed-by: Kever Yang" tag
 - Link to v2: https://lore.kernel.org/u-boot/cover.1721161722.git.seb-dev@mail.de/T/

Changes v1 -> v2:

 - Add new patch "phy: rockchip: naneng-combphy: Introduce PHY-IDs to fix RK3588 muxing"
 - Collect "Reviewed-by: Kever Yang" tags for all previous patches
 - Link to v1: https://lore.kernel.org/u-boot/cover.1720988760.git.seb-dev@mail.de/T/

---
Sebastian Kropatsch (1):
  phy: rockchip: naneng-combphy: Introduce PHY-IDs to fix RK3588 muxing

 .../rockchip/phy-rockchip-naneng-combphy.c    | 46 +++++++++++++++++--
 1 file changed, 43 insertions(+), 3 deletions(-)

-- 
2.43.0

[PATCH v3 1/1] phy: rockchip: naneng-combphy: Introduce PHY-IDs to fix RK3588 muxing

[Sebastian Kropatsch]

Fix multiplex configuration for PCIe1L0 and PCIe1L1 in PCIESEL_CON for
RK3588 to correctly select between Combo PHYs and PCIe3 PHY.
Currently, the code incorrectly muxes both ports to Combo PHYs,
interfering with PCIe3 PHY settings.
Introduce PHY identifiers to identify the correct Combo PHY and set
the necessary bits accordingly.

This fix is adapted from the upstream Linux commit by Sebastian Reichel:
d16d4002fea6 ("phy: rockchip: naneng-combphy: Fix mux on rk3588")

Fixes: b37260bca1aa ("phy: rockchip: naneng-combphy: Use signal from comb PHY on RK3588")
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Sebastian Kropatsch <seb-dev@mail.de>
---
 .../rockchip/phy-rockchip-naneng-combphy.c    | 46 +++++++++++++++++--
 1 file changed, 43 insertions(+), 3 deletions(-)

diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index 1b85cbcce8..5145b517aa 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -67,12 +67,15 @@ struct rockchip_combphy_grfcfg {
 };
 
 struct rockchip_combphy_cfg {
+	unsigned int num_phys;
+	unsigned int phy_ids[3];
 	const struct rockchip_combphy_grfcfg *grfcfg;
 	int (*combphy_cfg)(struct rockchip_combphy_priv *priv);
 };
 
 struct rockchip_combphy_priv {
 	u32 mode;
+	int id;
 	void __iomem *mmio;
 	struct udevice *dev;
 	struct regmap *pipe_grf;
@@ -270,8 +273,13 @@ static int rockchip_combphy_probe(struct udevice *udev)
 {
 	struct rockchip_combphy_priv *priv = dev_get_priv(udev);
 	const struct rockchip_combphy_cfg *phy_cfg;
+	fdt_addr_t addr = dev_read_addr(udev);
+	if (addr == FDT_ADDR_T_NONE) {
+		dev_err(udev, "No valid device address found\n");
+		return -EINVAL;
+	}
 
-	priv->mmio = (void __iomem *)dev_read_addr(udev);
+	priv->mmio = (void __iomem *)addr;
 	if (IS_ERR(priv->mmio))
 		return PTR_ERR(priv->mmio);
 
@@ -281,6 +289,20 @@ static int rockchip_combphy_probe(struct udevice *udev)
 		return -EINVAL;
 	}
 
+	/* Find the phy-id based on the device's I/O-address */
+	priv->id = -ENODEV;
+	for (int id = 0; id < phy_cfg->num_phys; id++) {
+		if (addr == phy_cfg->phy_ids[id]) {
+			priv->id = id;
+			break;
+		}
+	}
+
+	if (priv->id == -ENODEV) {
+		dev_err(udev, "Failed to find PHY ID\n");
+		return -ENODEV;
+	}
+
 	priv->dev = udev;
 	priv->mode = PHY_TYPE_SATA;
 	priv->cfg = phy_cfg;
@@ -421,6 +443,12 @@ static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = {
 };
 
 static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {
+	.num_phys = 3,
+	.phy_ids = {
+		0xfe820000,
+		0xfe830000,
+		0xfe840000,
+	},
 	.grfcfg		= &rk3568_combphy_grfcfgs,
 	.combphy_cfg	= rk3568_combphy_cfg,
 };
@@ -436,8 +464,14 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
 		param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
 		param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
 		param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
-		param_write(priv->pipe_grf, &cfg->pipe_pcie1l0_sel, true);
-		param_write(priv->pipe_grf, &cfg->pipe_pcie1l1_sel, true);
+		switch (priv->id) {
+		case 1:
+			param_write(priv->pipe_grf, &cfg->pipe_pcie1l0_sel, true);
+			break;
+		case 2:
+			param_write(priv->pipe_grf, &cfg->pipe_pcie1l1_sel, true);
+			break;
+		}
 		break;
 	case PHY_TYPE_USB3:
 		param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
@@ -515,6 +549,12 @@ static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = {
 };
 
 static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = {
+	.num_phys = 3,
+	.phy_ids = {
+		0xfee00000,
+		0xfee10000,
+		0xfee20000,
+	},
 	.grfcfg		= &rk3588_combphy_grfcfgs,
 	.combphy_cfg	= rk3588_combphy_cfg,
 };
-- 
2.43.0