From: Chao Liu <lc00631@tecorigin.com>
To: bmeng.cn@gmail.com, liwei1518@gmail.com, palmer@dabbelt.com,
alistair.francis@wdc.com
Cc: zhiwei_liu@linux.alibaba.com, dbarboza@ventanamicro.com,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
Chao Liu <lc00631@tecorigin.com>
Subject: [PATCH v1 0/1] Add vtype.vill FIELD macro definition
Date: Wed, 11 Dec 2024 21:47:14 +0800 [thread overview]
Message-ID: <cover.1733922709.git.lc00631@tecorigin.com> (raw)
Hi, all:
According to the "The RISC-V Instruction Set Manual Volume I: Unprivileged
Architecture" Version 20240411, Section 31.3.4 "Vector type register, vtype",
and Table 40 "vtype register layout", this patch adds the definition for the
vill field of the vtype register. The bit position for vill is [63].
This change ensures that our implementation remains in line with the latest
RISC-V specifications, thereby maintaining compatibility and correctness.
Chao Liu (1):
target/riscv: add VILL field for vtype register macro definition
target/riscv/cpu.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
--
2.47.0
next reply other threads:[~2024-12-11 14:01 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-11 13:47 Chao Liu [this message]
2024-12-11 13:47 ` [PATCH v1 1/1] target/riscv: add VILL field for vtype register macro definition Chao Liu
2024-12-11 14:05 ` Richard Henderson
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