* [PATCH v1 0/1] Add vtype.vill FIELD macro definition @ 2024-12-11 13:47 Chao Liu 2024-12-11 13:47 ` [PATCH v1 1/1] target/riscv: add VILL field for vtype register " Chao Liu 0 siblings, 1 reply; 3+ messages in thread From: Chao Liu @ 2024-12-11 13:47 UTC (permalink / raw) To: bmeng.cn, liwei1518, palmer, alistair.francis Cc: zhiwei_liu, dbarboza, qemu-devel, qemu-riscv, Chao Liu Hi, all: According to the "The RISC-V Instruction Set Manual Volume I: Unprivileged Architecture" Version 20240411, Section 31.3.4 "Vector type register, vtype", and Table 40 "vtype register layout", this patch adds the definition for the vill field of the vtype register. The bit position for vill is [63]. This change ensures that our implementation remains in line with the latest RISC-V specifications, thereby maintaining compatibility and correctness. Chao Liu (1): target/riscv: add VILL field for vtype register macro definition target/riscv/cpu.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.47.0 ^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH v1 1/1] target/riscv: add VILL field for vtype register macro definition 2024-12-11 13:47 [PATCH v1 0/1] Add vtype.vill FIELD macro definition Chao Liu @ 2024-12-11 13:47 ` Chao Liu 2024-12-11 14:05 ` Richard Henderson 0 siblings, 1 reply; 3+ messages in thread From: Chao Liu @ 2024-12-11 13:47 UTC (permalink / raw) To: bmeng.cn, liwei1518, palmer, alistair.francis Cc: zhiwei_liu, dbarboza, qemu-devel, qemu-riscv, Chao Liu Signed-off-by: Chao Liu <lc00631@tecorigin.com> --- target/riscv/cpu.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 284b112821..fc286484b8 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -170,7 +170,8 @@ FIELD(VTYPE, VSEW, 3, 3) FIELD(VTYPE, VTA, 6, 1) FIELD(VTYPE, VMA, 7, 1) FIELD(VTYPE, VEDIV, 8, 2) -FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) +FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 12) +FIELD(VTYPE, VILL, 63, 1) typedef struct PMUCTRState { /* Current value of a counter */ -- 2.47.0 ^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v1 1/1] target/riscv: add VILL field for vtype register macro definition 2024-12-11 13:47 ` [PATCH v1 1/1] target/riscv: add VILL field for vtype register " Chao Liu @ 2024-12-11 14:05 ` Richard Henderson 0 siblings, 0 replies; 3+ messages in thread From: Richard Henderson @ 2024-12-11 14:05 UTC (permalink / raw) To: qemu-devel On 12/11/24 07:47, Chao Liu wrote: > Signed-off-by: Chao Liu <lc00631@tecorigin.com> > --- > target/riscv/cpu.h | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 284b112821..fc286484b8 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -170,7 +170,8 @@ FIELD(VTYPE, VSEW, 3, 3) > FIELD(VTYPE, VTA, 6, 1) > FIELD(VTYPE, VMA, 7, 1) > FIELD(VTYPE, VEDIV, 8, 2) > -FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) > +FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 12) > +FIELD(VTYPE, VILL, 63, 1) It's 63 for rv64, but it's 31 for rv32. We handle this one manually. r~ ^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2024-12-11 14:06 UTC | newest] Thread overview: 3+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-12-11 13:47 [PATCH v1 0/1] Add vtype.vill FIELD macro definition Chao Liu 2024-12-11 13:47 ` [PATCH v1 1/1] target/riscv: add VILL field for vtype register " Chao Liu 2024-12-11 14:05 ` Richard Henderson
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