[PATCH v3 0/2] x86: Add Support for Paging-Write Feature

[PATCH v3 0/2] x86: Add Support for Paging-Write Feature

[Petr Beneš]

From: Petr Beneš <w1benny@gmail.com>

Changes since v2:
- Reset entry->pw in all cases in p2m_set_entry, except for p2m_access_r_pw

Changes since v1:
- Added signed-off-by tags

This patch introduces a new XENMEM_access_r_pw permission. Functionally, it is similar to XENMEM_access_r, but for processors with TERTIARY_EXEC_EPT_PAGING_WRITE support (Intel 12th Gen/Alder Lake and later), it also permits the CPU to write to the page during guest page-table walks (e.g., updating A/D bits) without triggering an EPT violation.

This behavior works by both enabling the EPT paging-write feature and setting the EPT paging-write flag in the EPT leaf entry.

This feature provides a significant performance boost for introspection tools that monitor guest page-table updates. Previously, every page-table modification by the guest—including routine updates like setting A/D bits—triggered an EPT violation, adding unnecessary overhead. The new XENMEM_access_r_pw permission allows these "uninteresting" updates to occur without EPT violations, improving efficiency.

Additionally, this feature simplifies the handling of race conditions in scenarios where an introspection tool:

- Sets an "invisible breakpoint" in the altp2m view for a function F
- Monitors guest page-table updates to track whether the page containing F is paged out
- Encounters a cleared Access (A) bit on the page containing F while the guest is about to execute the breakpoint

In the current implementation:

- If xc_monitor_inguest_pagefault() is enabled, the introspection tool must emulate both the breakpoint and the setting of the Access bit.
- If xc_monitor_inguest_pagefault() is disabled, Xen handles the EPT violation without notifying the introspection tool, setting the Access bit and emulating the instruction. However, Xen fetches the instruction from the default view instead of the altp2m view, potentially causing the breakpoint to be missed.

With this patch, setting XENMEM_access_r_pw for monitored guest page-tables prevents EPT violations in these cases. This change enhances performance and reduces complexity for introspection tools, ensuring seamless breakpoint handling while tracking guest page-table updates.


Petr Beneš (2):
  x86: Rename _rsvd field to pw and move it to the bit 58
  x86: Add Support for Paging-Write Feature

 xen/arch/arm/mem_access.c               |  4 ++++
 xen/arch/arm/mmu/p2m.c                  |  1 +
 xen/arch/x86/hvm/hvm.c                  |  1 +
 xen/arch/x86/hvm/monitor.c              |  1 +
 xen/arch/x86/hvm/vmx/vmcs.c             |  4 +++-
 xen/arch/x86/include/asm/hvm/vmx/vmcs.h |  3 +++
 xen/arch/x86/include/asm/hvm/vmx/vmx.h  |  4 ++--
 xen/arch/x86/include/asm/p2m.h          |  1 +
 xen/arch/x86/mm/hap/nested_hap.c        |  3 +++
 xen/arch/x86/mm/mem_access.c            |  3 +++
 xen/arch/x86/mm/p2m-ept.c               | 12 ++++++++++++
 xen/include/public/memory.h             |  9 +++++++++
 xen/include/xen/mem_access.h            |  6 ++++++
 13 files changed, 49 insertions(+), 3 deletions(-)

-- 
2.34.1

[PATCH v3 1/2] x86: Rename _rsvd field to pw and move it to the bit 58

[Petr Beneš]

From: Petr Beneš <w1benny@gmail.com>

The EPT Paging-write feature (when enabled by the TERTIARY_EXEC_EPT_PAGING_WRITE bit) uses bit 58 of the EPT entry to indicate that guest paging may update the page, even if the W access is not set.

This patch is a preparation for the EPT Paging-write feature.

Signed-off-by: Petr Beneš <w1benny@gmail.com>
Acked-by: Tamas K Lengyel <tamas@tklengyel.com>
---
 xen/arch/x86/include/asm/hvm/vmx/vmx.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/xen/arch/x86/include/asm/hvm/vmx/vmx.h b/xen/arch/x86/include/asm/hvm/vmx/vmx.h
index f0ec459622..d920de96b7 100644
--- a/xen/arch/x86/include/asm/hvm/vmx/vmx.h
+++ b/xen/arch/x86/include/asm/hvm/vmx/vmx.h
@@ -34,8 +34,8 @@ typedef union {
                                EPT/VT-d usage */
         mfn         :   40, /* bits 51:12 - Machine physical frame number */
         sa_p2mt     :   6,  /* bits 57:52 - Software available 2 */
-        access      :   4,  /* bits 61:58 - p2m_access_t */
-        _rsvd       :   1,  /* bit 62 - reserved */
+        pw          :   1,  /* bit 58 - Paging-write access */
+        access      :   4,  /* bits 62:59 - p2m_access_t */
         suppress_ve :   1;  /* bit 63 - suppress #VE */
     };
     u64 epte;
-- 
2.34.1

Re: [PATCH v3 1/2] x86: Rename _rsvd field to pw and move it to the bit 58

[Jan Beulich]

On 02.01.2025 18:13, Petr Beneš wrote:
> From: Petr Beneš <w1benny@gmail.com>
> 
> The EPT Paging-write feature (when enabled by the TERTIARY_EXEC_EPT_PAGING_WRITE bit) uses bit 58 of the EPT entry to indicate that guest paging may update the page, even if the W access is not set.
> 
> This patch is a preparation for the EPT Paging-write feature.
> 
> Signed-off-by: Petr Beneš <w1benny@gmail.com>
> Acked-by: Tamas K Lengyel <tamas@tklengyel.com>

Acked-by: Jan Beulich <jbeulich@suse.com>

[PATCH v3 2/2] x86: Add Support for Paging-Write Feature

[Petr Beneš]

From: Petr Beneš <w1benny@gmail.com>

This patch introduces a new XENMEM_access_r_pw permission. Functionally, it is similar to XENMEM_access_r, but for processors with TERTIARY_EXEC_EPT_PAGING_WRITE support (Intel 12th Gen/Alder Lake and later), it also permits the CPU to write to the page during guest page-table walks (e.g., updating A/D bits) without triggering an EPT violation.

This behavior works by both enabling the EPT paging-write feature and setting the EPT paging-write flag in the EPT leaf entry.

This feature provides a significant performance boost for introspection tools that monitor guest page-table updates. Previously, every page-table modification by the guest—including routine updates like setting A/D bits—triggered an EPT violation, adding unnecessary overhead. The new XENMEM_access_r_pw permission allows these "uninteresting" updates to occur without EPT violations, improving efficiency.

Additionally, this feature simplifies the handling of race conditions in scenarios where an introspection tool:

- Sets an "invisible breakpoint" in the altp2m view for a function F
- Monitors guest page-table updates to track whether the page containing F is paged out
- Encounters a cleared Access (A) bit on the page containing F while the guest is about to execute the breakpoint

In the current implementation:

- If xc_monitor_inguest_pagefault() is enabled, the introspection tool must emulate both the breakpoint and the setting of the Access bit.
- If xc_monitor_inguest_pagefault() is disabled, Xen handles the EPT violation without notifying the introspection tool, setting the Access bit and emulating the instruction. However, Xen fetches the instruction from the default view instead of the altp2m view, potentially causing the breakpoint to be missed.

With this patch, setting XENMEM_access_r_pw for monitored guest page-tables prevents EPT violations in these cases. This change enhances performance and reduces complexity for introspection tools, ensuring seamless breakpoint handling while tracking guest page-table updates.

Signed-off-by: Petr Beneš <w1benny@gmail.com>
Acked-by: Tamas K Lengyel <tamas@tklengyel.com>
---
 xen/arch/arm/mem_access.c               |  4 ++++
 xen/arch/arm/mmu/p2m.c                  |  1 +
 xen/arch/x86/hvm/hvm.c                  |  1 +
 xen/arch/x86/hvm/monitor.c              |  1 +
 xen/arch/x86/hvm/vmx/vmcs.c             |  4 +++-
 xen/arch/x86/include/asm/hvm/vmx/vmcs.h |  3 +++
 xen/arch/x86/include/asm/p2m.h          |  1 +
 xen/arch/x86/mm/hap/nested_hap.c        |  3 +++
 xen/arch/x86/mm/mem_access.c            |  3 +++
 xen/arch/x86/mm/p2m-ept.c               | 12 ++++++++++++
 xen/include/public/memory.h             |  9 +++++++++
 xen/include/xen/mem_access.h            |  6 ++++++
 12 files changed, 47 insertions(+), 1 deletion(-)

diff --git a/xen/arch/arm/mem_access.c b/xen/arch/arm/mem_access.c
index 0ec3462364..2af92bb402 100644
--- a/xen/arch/arm/mem_access.c
+++ b/xen/arch/arm/mem_access.c
@@ -32,6 +32,7 @@ static int __p2m_get_mem_access(struct domain *d, gfn_t gfn,
             ACCESS(rwx),
             ACCESS(rx2rw),
             ACCESS(n2rwx),
+            ACCESS(r_pw),
 #undef ACCESS
     };
 
@@ -172,6 +173,7 @@ p2m_mem_access_check_and_get_page(vaddr_t gva, unsigned long flag,
             break;
         else
             goto err;
+    case XENMEM_access_r_pw:
     case XENMEM_access_rx2rw:
     case XENMEM_access_rx:
     case XENMEM_access_r:
@@ -253,6 +255,7 @@ bool p2m_mem_access_check(paddr_t gpa, vaddr_t gla, const struct npfec npfec)
         violation = npfec.read_access || npfec.insn_fetch;
         break;
     case XENMEM_access_r:
+    case XENMEM_access_r_pw:
         violation = npfec.write_access || npfec.insn_fetch;
         break;
     default:
@@ -361,6 +364,7 @@ long p2m_set_mem_access(struct domain *d, gfn_t gfn, uint32_t nr,
         ACCESS(rwx),
         ACCESS(rx2rw),
         ACCESS(n2rwx),
+        ACCESS(r_pw),
 #undef ACCESS
     };
 
diff --git a/xen/arch/arm/mmu/p2m.c b/xen/arch/arm/mmu/p2m.c
index 28df6e5d03..7642dbc7c5 100644
--- a/xen/arch/arm/mmu/p2m.c
+++ b/xen/arch/arm/mmu/p2m.c
@@ -597,6 +597,7 @@ static void p2m_set_permission(lpae_t *e, p2m_type_t t, p2m_access_t a)
         e->p2m.read = 0;
         break;
     case p2m_access_r:
+    case p2m_access_r_pw:
         e->p2m.write = 0;
         e->p2m.xn = 1;
         break;
diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index 74e58c653e..495c8290ca 100644
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -1897,6 +1897,7 @@ int hvm_hap_nested_page_fault(paddr_t gpa, unsigned long gla,
             violation = npfec.read_access || npfec.write_access || npfec.insn_fetch;
             break;
         case p2m_access_r:
+        case p2m_access_r_pw:
             violation = npfec.write_access || npfec.insn_fetch;
             break;
         case p2m_access_w:
diff --git a/xen/arch/x86/hvm/monitor.c b/xen/arch/x86/hvm/monitor.c
index 74621000b2..523586ca98 100644
--- a/xen/arch/x86/hvm/monitor.c
+++ b/xen/arch/x86/hvm/monitor.c
@@ -295,6 +295,7 @@ bool hvm_monitor_check_p2m(unsigned long gla, gfn_t gfn, uint32_t pfec,
 
     case XENMEM_access_r:
     case XENMEM_access_n:
+    case XENMEM_access_r_pw:
         if ( pfec & PFEC_write_access )
             req.u.mem_access.flags |= MEM_ACCESS_R | MEM_ACCESS_W;
         if ( pfec & PFEC_insn_fetch )
diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c
index 147e998371..8c0ea789c1 100644
--- a/xen/arch/x86/hvm/vmx/vmcs.c
+++ b/xen/arch/x86/hvm/vmx/vmcs.c
@@ -203,6 +203,7 @@ static void __init vmx_display_features(void)
     P(cpu_has_vmx_bus_lock_detection, "Bus Lock Detection");
     P(cpu_has_vmx_notify_vm_exiting, "Notify VM Exit");
     P(cpu_has_vmx_virt_spec_ctrl, "Virtualize SPEC_CTRL");
+    P(cpu_has_vmx_ept_paging_write, "EPT Paging-Write");
 #undef P
 
     if ( !printed )
@@ -366,7 +367,8 @@ static int vmx_init_vmcs_config(bool bsp)
 
     if ( _vmx_cpu_based_exec_control & CPU_BASED_ACTIVATE_TERTIARY_CONTROLS )
     {
-        uint64_t opt = TERTIARY_EXEC_VIRT_SPEC_CTRL;
+        uint64_t opt = (TERTIARY_EXEC_VIRT_SPEC_CTRL |
+                        TERTIARY_EXEC_EPT_PAGING_WRITE);
 
         _vmx_tertiary_exec_control = adjust_vmx_controls2(
             "Tertiary Exec Control", 0, opt,
diff --git a/xen/arch/x86/include/asm/hvm/vmx/vmcs.h b/xen/arch/x86/include/asm/hvm/vmx/vmcs.h
index 939b87eb50..e1d3398141 100644
--- a/xen/arch/x86/include/asm/hvm/vmx/vmcs.h
+++ b/xen/arch/x86/include/asm/hvm/vmx/vmcs.h
@@ -273,6 +273,9 @@ extern uint64_t vmx_tertiary_exec_control;
 #define cpu_has_vmx_virt_spec_ctrl \
      (vmx_tertiary_exec_control & TERTIARY_EXEC_VIRT_SPEC_CTRL)
 
+#define cpu_has_vmx_ept_paging_write \
+     (vmx_tertiary_exec_control & TERTIARY_EXEC_EPT_PAGING_WRITE)
+
 #define VMX_EPT_EXEC_ONLY_SUPPORTED                         0x00000001
 #define VMX_EPT_WALK_LENGTH_4_SUPPORTED                     0x00000040
 #define VMX_EPT_MEMORY_TYPE_UC                              0x00000100
diff --git a/xen/arch/x86/include/asm/p2m.h b/xen/arch/x86/include/asm/p2m.h
index e6de37f108..aa1bf7c9d0 100644
--- a/xen/arch/x86/include/asm/p2m.h
+++ b/xen/arch/x86/include/asm/p2m.h
@@ -980,6 +980,7 @@ static inline unsigned int p2m_access_to_iommu_flags(p2m_access_t p2ma)
     case p2m_access_r:
     case p2m_access_rx:
     case p2m_access_rx2rw:
+    case p2m_access_r_pw:
         return IOMMUF_readable;
 
     case p2m_access_w:
diff --git a/xen/arch/x86/mm/hap/nested_hap.c b/xen/arch/x86/mm/hap/nested_hap.c
index cc7bc6e5ea..255fba7e1c 100644
--- a/xen/arch/x86/mm/hap/nested_hap.c
+++ b/xen/arch/x86/mm/hap/nested_hap.c
@@ -213,6 +213,9 @@ int nestedhvm_hap_nested_page_fault(
     case p2m_access_n2rwx:
         p2ma_10 = p2m_access_n;
         break;
+    case p2m_access_r_pw:
+        p2ma_10 = p2m_access_r;
+        break;
     default:
         p2ma_10 = p2m_access_n;
         /* For safety, remove all permissions. */
diff --git a/xen/arch/x86/mm/mem_access.c b/xen/arch/x86/mm/mem_access.c
index 60a0cce68a..21b5b7ecda 100644
--- a/xen/arch/x86/mm/mem_access.c
+++ b/xen/arch/x86/mm/mem_access.c
@@ -45,6 +45,7 @@ static int _p2m_get_mem_access(struct p2m_domain *p2m, gfn_t gfn,
             ACCESS(rwx),
             ACCESS(rx2rw),
             ACCESS(n2rwx),
+            ACCESS(r_pw),
 #undef ACCESS
     };
 
@@ -94,6 +95,7 @@ bool p2m_mem_access_emulate_check(struct vcpu *v,
             break;
 
         case XENMEM_access_r:
+        case XENMEM_access_r_pw:
             violation = data->flags & MEM_ACCESS_WX;
             break;
 
@@ -312,6 +314,7 @@ bool xenmem_access_to_p2m_access(const struct p2m_domain *p2m,
         ACCESS(rwx),
         ACCESS(rx2rw),
         ACCESS(n2rwx),
+        ACCESS(r_pw),
 #undef ACCESS
     };
 
diff --git a/xen/arch/x86/mm/p2m-ept.c b/xen/arch/x86/mm/p2m-ept.c
index 21728397f9..7ce8f3a1ca 100644
--- a/xen/arch/x86/mm/p2m-ept.c
+++ b/xen/arch/x86/mm/p2m-ept.c
@@ -154,27 +154,39 @@ static void ept_p2m_type_to_flags(const struct p2m_domain *p2m,
         case p2m_access_n:
         case p2m_access_n2rwx:
             entry->r = entry->w = entry->x = 0;
+            entry->pw = 0;
             break;
         case p2m_access_r:
             entry->w = entry->x = 0;
+            entry->pw = 0;
             break;
         case p2m_access_w:
             entry->r = entry->x = 0;
+            entry->pw = 0;
             break;
         case p2m_access_x:
             entry->r = entry->w = 0;
+            entry->pw = 0;
             break;
         case p2m_access_rx:
         case p2m_access_rx2rw:
             entry->w = 0;
+            entry->pw = 0;
             break;
         case p2m_access_wx:
             entry->r = 0;
+            entry->pw = 0;
             break;
         case p2m_access_rw:
             entry->x = 0;
+            entry->pw = 0;
             break;           
         case p2m_access_rwx:
+            entry->pw = 0;
+            break;
+        case p2m_access_r_pw:
+            entry->w = entry->x = 0;
+            entry->pw = !!cpu_has_vmx_ept_paging_write;
             break;
     }
     
diff --git a/xen/include/public/memory.h b/xen/include/public/memory.h
index 5e545ae9a4..bd9fc37b52 100644
--- a/xen/include/public/memory.h
+++ b/xen/include/public/memory.h
@@ -426,6 +426,15 @@ typedef enum {
      * pausing the vcpu
      */
     XENMEM_access_n2rwx,
+
+    /*
+     * Same as XENMEM_access_r, but on processors with
+     * the TERTIARY_EXEC_EPT_PAGING_WRITE support,
+     * CPU-initiated page-table walks can still
+     * write to it (e.g., update A/D bits)
+     */
+    XENMEM_access_r_pw,
+
     /* Take the domain default */
     XENMEM_access_default
 } xenmem_access_t;
diff --git a/xen/include/xen/mem_access.h b/xen/include/xen/mem_access.h
index 87d93b31f6..2231341b5d 100644
--- a/xen/include/xen/mem_access.h
+++ b/xen/include/xen/mem_access.h
@@ -64,6 +64,12 @@ typedef enum {
                            * generates an event but does not pause the
                            * vcpu */
 
+    p2m_access_r_pw = 10, /* Special: same as R, but on processors with
+                           * the TERTIARY_EXEC_EPT_PAGING_WRITE support,
+                           * CPU-initiated page-table walks can still
+                           * write to it (e.g., update A/D bits)
+                           */
+
     /* NOTE: Assumed to be only 4 bits right now on x86. */
 } p2m_access_t;
 
-- 
2.34.1

Re: [PATCH v3 2/2] x86: Add Support for Paging-Write Feature

[Jan Beulich]

On 02.01.2025 18:13, Petr Beneš wrote:
> --- a/xen/arch/x86/mm/p2m-ept.c
> +++ b/xen/arch/x86/mm/p2m-ept.c
> @@ -154,27 +154,39 @@ static void ept_p2m_type_to_flags(const struct p2m_domain *p2m,
>          case p2m_access_n:
>          case p2m_access_n2rwx:
>              entry->r = entry->w = entry->x = 0;
> +            entry->pw = 0;
>              break;
>          case p2m_access_r:
>              entry->w = entry->x = 0;
> +            entry->pw = 0;
>              break;
>          case p2m_access_w:
>              entry->r = entry->x = 0;
> +            entry->pw = 0;
>              break;
>          case p2m_access_x:
>              entry->r = entry->w = 0;
> +            entry->pw = 0;
>              break;
>          case p2m_access_rx:
>          case p2m_access_rx2rw:
>              entry->w = 0;
> +            entry->pw = 0;
>              break;
>          case p2m_access_wx:
>              entry->r = 0;
> +            entry->pw = 0;
>              break;
>          case p2m_access_rw:
>              entry->x = 0;
> +            entry->pw = 0;
>              break;           
>          case p2m_access_rwx:
> +            entry->pw = 0;
> +            break;
> +        case p2m_access_r_pw:
> +            entry->w = entry->x = 0;
> +            entry->pw = !!cpu_has_vmx_ept_paging_write;
>              break;
>      }

Hmm ... Instead of you touching the bit in every one of the case blocks,
I was expecting you to clear the bit ahead of the switch(), accepting a
double update in the p2m_access_r_pw case.

Jan

Re: [PATCH v3 2/2] x86: Add Support for Paging-Write Feature

[Petr Beneš]

On Tue, Jan 7, 2025 at 5:46 PM Jan Beulich <jbeulich@suse.com> wrote:
> Hmm ... Instead of you touching the bit in every one of the case blocks,
> I was expecting you to clear the bit ahead of the switch(), accepting a
> double update in the p2m_access_r_pw case.

I did consider it, but ultimately didn't like the double-update.
Similarly, the switch-case above does also set each bit in the
"case-s" individually. But I understand it's more justified there.
However, if you insist, I'll fix it.

P.

Re: [PATCH v3 2/2] x86: Add Support for Paging-Write Feature

[Jan Beulich]

On 07.01.2025 18:18, Petr Beneš wrote:
> On Tue, Jan 7, 2025 at 5:46 PM Jan Beulich <jbeulich@suse.com> wrote:
>> Hmm ... Instead of you touching the bit in every one of the case blocks,
>> I was expecting you to clear the bit ahead of the switch(), accepting a
>> double update in the p2m_access_r_pw case.
> 
> I did consider it, but ultimately didn't like the double-update.
> Similarly, the switch-case above does also set each bit in the
> "case-s" individually. But I understand it's more justified there.

Right - it's setting them to all different combinations each time.

> However, if you insist, I'll fix it.

Please do; it helps readability quite a bit in this case, imo.

Jan

Re: [PATCH v3 2/2] x86: Add Support for Paging-Write Feature

[Andrew Cooper]

On 08/01/2025 7:16 am, Jan Beulich wrote:
> On 07.01.2025 18:18, Petr Beneš wrote:
>> On Tue, Jan 7, 2025 at 5:46 PM Jan Beulich <jbeulich@suse.com> wrote:
>>> Hmm ... Instead of you touching the bit in every one of the case blocks,
>>> I was expecting you to clear the bit ahead of the switch(), accepting a
>>> double update in the p2m_access_r_pw case.
>> I did consider it, but ultimately didn't like the double-update.
>> Similarly, the switch-case above does also set each bit in the
>> "case-s" individually. But I understand it's more justified there.
> Right - it's setting them to all different combinations each time.
>
>> However, if you insist, I'll fix it.
> Please do; it helps readability quite a bit in this case, imo.

I agree.

These "writes" are just bit operations on a single register.  The
compiler is pretty good at rearranging such logic.

Seeing as this is the only issue, I'm happy to fix on commit?

~Andrew

Re: [PATCH v3 2/2] x86: Add Support for Paging-Write Feature

[Petr Beneš]

On Wed, Jan 8, 2025 at 1:23 PM Andrew Cooper <andrew.cooper3@citrix.com> wrote:
> Seeing as this is the only issue, I'm happy to fix on commit?

Fine by me!

P.

Re: [PATCH v3 0/2] x86: Add Support for Paging-Write Feature

[Oleksii Kurochko]

[-- Attachment #1: Type: text/plain, Size: 3589 bytes --]


On 1/2/25 6:13 PM, Petr Beneš wrote:
> From: Petr Beneš<w1benny@gmail.com>
>
> Changes since v2:
> - Reset entry->pw in all cases in p2m_set_entry, except for p2m_access_r_pw
>
> Changes since v1:
> - Added signed-off-by tags
>
> This patch introduces a new XENMEM_access_r_pw permission. Functionally, it is similar to XENMEM_access_r, but for processors with TERTIARY_EXEC_EPT_PAGING_WRITE support (Intel 12th Gen/Alder Lake and later), it also permits the CPU to write to the page during guest page-table walks (e.g., updating A/D bits) without triggering an EPT violation.
>
> This behavior works by both enabling the EPT paging-write feature and setting the EPT paging-write flag in the EPT leaf entry.
>
> This feature provides a significant performance boost for introspection tools that monitor guest page-table updates. Previously, every page-table modification by the guest—including routine updates like setting A/D bits—triggered an EPT violation, adding unnecessary overhead. The new XENMEM_access_r_pw permission allows these "uninteresting" updates to occur without EPT violations, improving efficiency.

Considering that this feature provides a significant performance boost 
for introspection tools probably we could consider to take it to current 
release.

I see that the patch series was acked-by "Acked-by: Tamas K Lengyel 
<tamas@tklengyel.com>" but based on the change log it is not clear when 
exactly

before Feature freeze date or not. ( and I don't see any reply from Tamas ).

Thanks.

~ Oleksii

>
> Additionally, this feature simplifies the handling of race conditions in scenarios where an introspection tool:
>
> - Sets an "invisible breakpoint" in the altp2m view for a function F
> - Monitors guest page-table updates to track whether the page containing F is paged out
> - Encounters a cleared Access (A) bit on the page containing F while the guest is about to execute the breakpoint
>
> In the current implementation:
>
> - If xc_monitor_inguest_pagefault() is enabled, the introspection tool must emulate both the breakpoint and the setting of the Access bit.
> - If xc_monitor_inguest_pagefault() is disabled, Xen handles the EPT violation without notifying the introspection tool, setting the Access bit and emulating the instruction. However, Xen fetches the instruction from the default view instead of the altp2m view, potentially causing the breakpoint to be missed.
>
> With this patch, setting XENMEM_access_r_pw for monitored guest page-tables prevents EPT violations in these cases. This change enhances performance and reduces complexity for introspection tools, ensuring seamless breakpoint handling while tracking guest page-table updates.
>
>
> Petr Beneš (2):
>    x86: Rename _rsvd field to pw and move it to the bit 58
>    x86: Add Support for Paging-Write Feature
>
>   xen/arch/arm/mem_access.c               |  4 ++++
>   xen/arch/arm/mmu/p2m.c                  |  1 +
>   xen/arch/x86/hvm/hvm.c                  |  1 +
>   xen/arch/x86/hvm/monitor.c              |  1 +
>   xen/arch/x86/hvm/vmx/vmcs.c             |  4 +++-
>   xen/arch/x86/include/asm/hvm/vmx/vmcs.h |  3 +++
>   xen/arch/x86/include/asm/hvm/vmx/vmx.h  |  4 ++--
>   xen/arch/x86/include/asm/p2m.h          |  1 +
>   xen/arch/x86/mm/hap/nested_hap.c        |  3 +++
>   xen/arch/x86/mm/mem_access.c            |  3 +++
>   xen/arch/x86/mm/p2m-ept.c               | 12 ++++++++++++
>   xen/include/public/memory.h             |  9 +++++++++
>   xen/include/xen/mem_access.h            |  6 ++++++
>   13 files changed, 49 insertions(+), 3 deletions(-)
>

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Re: [PATCH v3 0/2] x86: Add Support for Paging-Write Feature

[Tamas K Lengyel]

On Thu, Jan 9, 2025 at 9:30 AM Oleksii Kurochko
<oleksii.kurochko@gmail.com> wrote:
>
>
> On 1/2/25 6:13 PM, Petr Beneš wrote:
>
> From: Petr Beneš <w1benny@gmail.com>
>
> Changes since v2:
> - Reset entry->pw in all cases in p2m_set_entry, except for p2m_access_r_pw
>
> Changes since v1:
> - Added signed-off-by tags
>
> This patch introduces a new XENMEM_access_r_pw permission. Functionally, it is similar to XENMEM_access_r, but for processors with TERTIARY_EXEC_EPT_PAGING_WRITE support (Intel 12th Gen/Alder Lake and later), it also permits the CPU to write to the page during guest page-table walks (e.g., updating A/D bits) without triggering an EPT violation.
>
> This behavior works by both enabling the EPT paging-write feature and setting the EPT paging-write flag in the EPT leaf entry.
>
> This feature provides a significant performance boost for introspection tools that monitor guest page-table updates. Previously, every page-table modification by the guest—including routine updates like setting A/D bits—triggered an EPT violation, adding unnecessary overhead. The new XENMEM_access_r_pw permission allows these "uninteresting" updates to occur without EPT violations, improving efficiency.
>
> Considering that this feature provides a significant performance boost for introspection tools probably we could consider to take it to current release.
>
> I see that the patch series was acked-by "Acked-by: Tamas K Lengyel <tamas@tklengyel.com>" but based on the change log it is not clear when exactly
>
> before Feature freeze date or not. ( and I don't see any reply from Tamas ).

I've acked the patch Thu, Dec 19, 2024.

Cheers,
Tamas

Re: [PATCH v3 0/2] x86: Add Support for Paging-Write Feature

[Oleksii Kurochko]

On 1/9/25 4:25 PM, Tamas K Lengyel wrote:
> On Thu, Jan 9, 2025 at 9:30 AM Oleksii Kurochko
> <oleksii.kurochko@gmail.com> wrote:
>>
>> On 1/2/25 6:13 PM, Petr Beneš wrote:
>>
>> From: Petr Beneš <w1benny@gmail.com>
>>
>> Changes since v2:
>> - Reset entry->pw in all cases in p2m_set_entry, except for p2m_access_r_pw
>>
>> Changes since v1:
>> - Added signed-off-by tags
>>
>> This patch introduces a new XENMEM_access_r_pw permission. Functionally, it is similar to XENMEM_access_r, but for processors with TERTIARY_EXEC_EPT_PAGING_WRITE support (Intel 12th Gen/Alder Lake and later), it also permits the CPU to write to the page during guest page-table walks (e.g., updating A/D bits) without triggering an EPT violation.
>>
>> This behavior works by both enabling the EPT paging-write feature and setting the EPT paging-write flag in the EPT leaf entry.
>>
>> This feature provides a significant performance boost for introspection tools that monitor guest page-table updates. Previously, every page-table modification by the guest—including routine updates like setting A/D bits—triggered an EPT violation, adding unnecessary overhead. The new XENMEM_access_r_pw permission allows these "uninteresting" updates to occur without EPT violations, improving efficiency.
>>
>> Considering that this feature provides a significant performance boost for introspection tools probably we could consider to take it to current release.
>>
>> I see that the patch series was acked-by "Acked-by: Tamas K Lengyel <tamas@tklengyel.com>" but based on the change log it is not clear when exactly
>>
>> before Feature freeze date or not. ( and I don't see any reply from Tamas ).
> I've acked the patch Thu, Dec 19, 2024.

In this case, I believe we should consider including it in the current 
release, as it was technically ready for merging before the Feature 
Freeze deadline.

I would like to kindly ask the x86 maintainers for clarification on why 
this patch series was not merged.

~ Oleksii

Re: [PATCH v3 0/2] x86: Add Support for Paging-Write Feature

[Jan Beulich]

On 13.01.2025 18:18, Oleksii Kurochko wrote:
> I would like to kindly ask the x86 maintainers for clarification on why 
> this patch series was not merged.

v1 of this patch was submitted on Dec 19, when patch submission deadline
was Nov 29.

Jan