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From: Chen Wang <unicornxw@gmail.com>
To: u.kleine-koenig@baylibre.com, aou@eecs.berkeley.edu,
	arnd@arndb.de, unicorn_wang@outlook.com, conor+dt@kernel.org,
	guoren@kernel.org, inochiama@outlook.com, krzk+dt@kernel.org,
	palmer@dabbelt.com, paul.walmsley@sifive.com, robh@kernel.org,
	tglx@linutronix.de, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	chao.wei@sophgo.com, xiaoguang.xing@sophgo.com,
	fengchun.li@sophgo.com, samuel.holland@sifive.com,
	christophe.jaillet@wanadoo.fr
Subject: [PATCH v3 0/3] irqchip: Add Sophgo SG2042 MSI controller
Date: Wed, 15 Jan 2025 14:31:48 +0800	[thread overview]
Message-ID: <cover.1736921549.git.unicorn_wang@outlook.com> (raw)

From: Chen Wang <unicorn_wang@outlook.com>

This controller is on the Sophgo SG2042 SoC to transform interrupts from
PCIe MSI to PLIC interrupts.

Thanks,
Chen

---

Changes in v3:
  The patch series is based on v6.13-rc7.

  Fixed following issues as per comments from Krzysztof Kozlowski, Samuel Holland,
  Christophe JAILLET, Inochi Amaoto, thanks.

  - bindings: use reg for doorbell, fixed wrong usage of additionalProperties
    and misc. 
  - Improve driver code:
    - Fixed potentional memory leak issues.
    - Fixed some build warnings reported by test robot.
    - Optimize and simplify the code when allocating hwirq.
    - Use DECLARE_BITMAP instead of kzalloc.
    - Some other coding style improvements.

Changes in v2:
  The patch series is based on v6.13-rc2. You can simply review or test the
  patches at the link [2].

  Fixed following issues as per comments from Rob Herring, Thomas Gleixner, thanks.

  - Improve driver binding description, use msi-ranges instread.
  - Improve driver code:
    - Improve coding style.
    - Fixed bug that possible memory leak of bitmap when sg2042_msi_init_domains returns error.
    - Use guard(mutex).
    - Use the MSI parent model.

Changes in v1:
  The patch series is based on v6.12-rc7. You can simply review or test the
  patches at the link [1].

Link: https://lore.kernel.org/linux-riscv/cover.1731296803.git.unicorn_wang@outlook.com/ [1]
Link: https://lore.kernel.org/linux-riscv/cover.1733726057.git.unicorn_wang@outlook.com/ [2]
---

Chen Wang (3):
  dt-bindings: interrupt-controller: Add Sophgo SG2042 MSI
  irqchip: Add the Sophgo SG2042 MSI interrupt controller
  riscv: sophgo: dts: add msi controller for SG2042

 .../sophgo,sg2042-msi.yaml                    |  58 ++++
 arch/riscv/boot/dts/sophgo/sg2042.dtsi        |  10 +
 drivers/irqchip/Kconfig                       |  12 +
 drivers/irqchip/Makefile                      |   1 +
 drivers/irqchip/irq-sg2042-msi.c              | 268 ++++++++++++++++++
 5 files changed, 349 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml
 create mode 100644 drivers/irqchip/irq-sg2042-msi.c


base-commit: 5bc55a333a2f7316b58edc7573e8e893f7acb532
-- 
2.34.1


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WARNING: multiple messages have this Message-ID (diff)
From: Chen Wang <unicornxw@gmail.com>
To: u.kleine-koenig@baylibre.com, aou@eecs.berkeley.edu,
	arnd@arndb.de, unicorn_wang@outlook.com, conor+dt@kernel.org,
	guoren@kernel.org, inochiama@outlook.com, krzk+dt@kernel.org,
	palmer@dabbelt.com, paul.walmsley@sifive.com, robh@kernel.org,
	tglx@linutronix.de, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	chao.wei@sophgo.com, xiaoguang.xing@sophgo.com,
	fengchun.li@sophgo.com, samuel.holland@sifive.com,
	christophe.jaillet@wanadoo.fr
Subject: [PATCH v3 0/3] irqchip: Add Sophgo SG2042 MSI controller
Date: Wed, 15 Jan 2025 14:31:48 +0800	[thread overview]
Message-ID: <cover.1736921549.git.unicorn_wang@outlook.com> (raw)

From: Chen Wang <unicorn_wang@outlook.com>

This controller is on the Sophgo SG2042 SoC to transform interrupts from
PCIe MSI to PLIC interrupts.

Thanks,
Chen

---

Changes in v3:
  The patch series is based on v6.13-rc7.

  Fixed following issues as per comments from Krzysztof Kozlowski, Samuel Holland,
  Christophe JAILLET, Inochi Amaoto, thanks.

  - bindings: use reg for doorbell, fixed wrong usage of additionalProperties
    and misc. 
  - Improve driver code:
    - Fixed potentional memory leak issues.
    - Fixed some build warnings reported by test robot.
    - Optimize and simplify the code when allocating hwirq.
    - Use DECLARE_BITMAP instead of kzalloc.
    - Some other coding style improvements.

Changes in v2:
  The patch series is based on v6.13-rc2. You can simply review or test the
  patches at the link [2].

  Fixed following issues as per comments from Rob Herring, Thomas Gleixner, thanks.

  - Improve driver binding description, use msi-ranges instread.
  - Improve driver code:
    - Improve coding style.
    - Fixed bug that possible memory leak of bitmap when sg2042_msi_init_domains returns error.
    - Use guard(mutex).
    - Use the MSI parent model.

Changes in v1:
  The patch series is based on v6.12-rc7. You can simply review or test the
  patches at the link [1].

Link: https://lore.kernel.org/linux-riscv/cover.1731296803.git.unicorn_wang@outlook.com/ [1]
Link: https://lore.kernel.org/linux-riscv/cover.1733726057.git.unicorn_wang@outlook.com/ [2]
---

Chen Wang (3):
  dt-bindings: interrupt-controller: Add Sophgo SG2042 MSI
  irqchip: Add the Sophgo SG2042 MSI interrupt controller
  riscv: sophgo: dts: add msi controller for SG2042

 .../sophgo,sg2042-msi.yaml                    |  58 ++++
 arch/riscv/boot/dts/sophgo/sg2042.dtsi        |  10 +
 drivers/irqchip/Kconfig                       |  12 +
 drivers/irqchip/Makefile                      |   1 +
 drivers/irqchip/irq-sg2042-msi.c              | 268 ++++++++++++++++++
 5 files changed, 349 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml
 create mode 100644 drivers/irqchip/irq-sg2042-msi.c


base-commit: 5bc55a333a2f7316b58edc7573e8e893f7acb532
-- 
2.34.1


             reply	other threads:[~2025-01-15  6:32 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-15  6:31 Chen Wang [this message]
2025-01-15  6:31 ` [PATCH v3 0/3] irqchip: Add Sophgo SG2042 MSI controller Chen Wang
2025-01-15  6:33 ` [PATCH v3 1/3] dt-bindings: interrupt-controller: Add Sophgo SG2042 MSI Chen Wang
2025-01-15  6:33   ` Chen Wang
2025-01-20  2:42   ` Inochi Amaoto
2025-01-20  2:42     ` Inochi Amaoto
2025-01-22 13:51     ` Chen Wang
2025-01-22 13:51       ` Chen Wang
2025-01-22 22:42       ` Inochi Amaoto
2025-01-22 22:42         ` Inochi Amaoto
2025-01-23  0:47         ` Chen Wang
2025-01-23  0:47           ` Chen Wang
2025-01-23 21:29   ` Rob Herring
2025-01-23 21:29     ` Rob Herring
2025-02-18  1:26     ` Chen Wang
2025-02-18  1:26       ` Chen Wang
2025-01-15  6:33 ` [PATCH v3 2/3] irqchip: Add the Sophgo SG2042 MSI interrupt controller Chen Wang
2025-01-15  6:33   ` Chen Wang
2025-01-20  2:43   ` Inochi Amaoto
2025-01-20  2:43     ` Inochi Amaoto
2025-01-22 13:54     ` Chen Wang
2025-01-22 13:54       ` Chen Wang
2025-02-15  1:09   ` Inochi Amaoto
2025-02-15  1:09     ` Inochi Amaoto
2025-02-15  3:36     ` Chen Wang
2025-02-15  3:36       ` Chen Wang
2025-02-15  4:03       ` Inochi Amaoto
2025-02-15  4:03         ` Inochi Amaoto
2025-01-15  6:34 ` [PATCH v3 3/3] riscv: sophgo: dts: add msi controller for SG2042 Chen Wang
2025-01-15  6:34   ` Chen Wang

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